Substrate for mounting semiconductors
Description
FIG. 1 is a top perspective view of a substrate for mounting semi-conductors showing our new design;
FIG. 2 is a bottom perspective view thereof;
FIG. 3 is a right side elevational view thereof;
FIG. 4 is a left side elevational view thereof;
FIG. 5 is a rear elevational view thereof; and
FIG. 6 is a front elevational view thereof.
Referenced Cited
U.S. Patent Documents
Foreign Patent Documents
Other references
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- Disc Controller pictured on p. 190, Electronic Design, 10-16-86. NCR IC package pictured on p. 7, Electronic Design, 10-16-86. CMOS Chip pictured on p. 131, Electronics, 8-7-86. Electronics, p. 7, Feb. 24, 1986 by Fujitsu Microelectronics, Inc.
Patent History
Patent number: D318271
Type: Grant
Filed: Jan 4, 1988
Date of Patent: Jul 16, 1991
Inventors: Terutomi Hasegawa (Ogaki-City, Gifu Pref.), Nobumichi Goto (Seki City, Gifu Pref.)
Primary Examiner: Susan J. Lucas
Assistant Examiner: Joel Sincavage
Law Firm: Lorusso & Loud
Application Number: 7/140,348
Type: Grant
Filed: Jan 4, 1988
Date of Patent: Jul 16, 1991
Inventors: Terutomi Hasegawa (Ogaki-City, Gifu Pref.), Nobumichi Goto (Seki City, Gifu Pref.)
Primary Examiner: Susan J. Lucas
Assistant Examiner: Joel Sincavage
Law Firm: Lorusso & Loud
Application Number: 7/140,348
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)