Intergrated circuit tester
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FIG. 1 is a top, front and right side perspective view of a intergrated circuit tester showing our new design;
FIG. 2 is a top, front and right side perspective view, with the circuitry enclosure rotated 180 degrees;
FIG. 3 is a top plan view;
FIG. 4 is a right side elevational view;
FIG. 5 is a front elevational view;
FIG. 6 is a rear elevational view;
FIG. 7 is a top, front and right side perspective view of a second embodiment of our new design of FIGS. 1-6;
FIG. 8 is a top, front and right side perspective view, with the circuitry enclosure rotated 180 degrees;
FIG. 9 is a top plan view;
FIG. 10 is a right side elevational view, the left side elevational view being a mirror image;
FIG. 11 is a front elevational view;
FIG. 12 is a rear elevational view;
FIG. 13 is a top, front and right side perspective view of a third embodiment of our new design of FIGS. 1-6;
FIG. 14 is a top, front and right side perspective view, with the circuitry enclosure rotated 180 degrees;
FIG. 15 is a top plan view;
FIG. 16 is a right side elevational view, the left side elevational view being a mirror image;
FIG. 17 is a front elevational view; and
FIG. 18 is a rear elevational view thereof.
4504783 | March 12, 1985 | Zasio et al. |
4528504 | July 9, 1985 | Thornton, Jr. et al. |
4782289 | November 1, 1988 | Schwar et al. |
4782291 | November 1, 1988 | Blandin |
4970461 | November 13, 1990 | Lepage |
- HILEVEL Technology, Inc. news release dated Jun. 12, 1988. "VSLI Systems Design" publication dated Jun. 1988. HILEVEL Technology, Inc. advertising brochure for TOPAZ-V.
Type: Grant
Filed: Jan 11, 1989
Date of Patent: Oct 15, 1991
Assignee: Hilevel Technology (Irvine, CA)
Inventors: Bjorn M. Dahlberg (Irvine, CA), Charles H. Schwar (Irvine, CA), Mauro V. Tegethoff (Mission Viejo, CA)
Primary Examiner: Nelson C. Holtje
Assistant Examiner: Antoine D. Davis
Law Firm: Knobbe, Martens, Olson & Bear
Application Number: 7/296,185