3-in-1 IDE interface and power connector

- Seagate Technology, Inc.
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Description

FIG. 1 is a perspective view of a first embodiment showing our new design;

FIG. 2 is a front elevation view thereof;

FIG. 3 is a top plan view thereof;

FIG. 4 is a rear elevation view thereof;

FIG. 5 is an end elevation view thereof; the opposite end elevation view being a mirror image of the same;

FIG. 6 is a perspective view of a second embodiment showing our new design;

FIG. 7 is a front elevation view thereof;

FIG. 8 is a top plan view thereof;

FIG. 9 is a rear elevation view thereof; and,

FIG. 10 is an end elevation view thereof, the opposite end elevation view being a mirror image of the same.

The bottom of the connector forms no part of the claimed design.

Referenced Cited
U.S. Patent Documents
D271686 December 6, 1983 Casciotti et al.
D272145 January 10, 1984 Casciotti et al.
D273859 May 15, 1984 Casciotti et al.
D319427 August 27, 1991 Ichitsubo
5238413 August 24, 1993 McCaffrey et al.
5397248 March 14, 1995 Whiteman, Jr. et al.
Patent History
Patent number: D407688
Type: Grant
Filed: Sep 16, 1996
Date of Patent: Apr 6, 1999
Assignee: Seagate Technology, Inc. (Scotts Valley, CA)
Inventors: Wallis Allen Dague (Louisville, CO), Virat Thantrakul (La Crescenta, CA)
Primary Examiner: Alan P. Douglas
Assistant Examiner: Lavone D. Tabor
Law Firm: McDermott, Will & Emery
Application Number: 0/59,797
Classifications
Current U.S. Class: Linear Array Of Identical Repeating Ports Or Contacts (i.e., In-line Array) (D13/147)
International Classification: 1303;