Partially transparent IC card

- Kabushiki Kaisha Toshiba
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Description

FIG. 1 is a enlarged top, front and right side perspective view of partially transparent IC card showing our new design;

FIG. 2 is a top plan view thereof;

FIG. 3 is a front elevational view thereof;

FIG. 4 is a rear elevational view thereof;

FIG. 5 is a right side elevational view thereof;

FIG. 6 is a left side elevational view thereof;

FIG. 7 is a bottom plan view thereof;

FIG. 8 is a greatly enlarged cross-sectional view thereof, taken along line 8—8 in FIG. 7.

FIG. 9 is an enlarged top, front and right side perspective view of a second embodiment of the partially transparent IC card;

FIG. 10 is top plan view thereof;

FIG. 11 is a front elevational view thereof;

FIG. 12 is a rear elevational view thereof;

FIG. 13 is a right side elevational view thereof;

FIG. 14 is a left side elevational view thereof;

FIG. 15 is a bottom plan view thereof;

FIG. 16 is a greatly enlarged cross-sectional view thereof, taken along line 16—16 in FIG. 15.

FIG. 17 is an enlarged top, front and right side perspective view of a third embodiment of the partially transparent IC card;

FIG. 18 is a top plan view thereof;

FIG. 19 is a front elevational view thereof;

FIG. 20 is a rear elevational view thereof;

FIG. 21 is a right side elevational view thereof;

FIG. 22 is a left side elevational view thereof;

FIG. 23 is a bottom plan view thereof;

FIG. 24 is an enlarged cross-sectional view thereof, taken along line 24—24 in FIG. 23;

FIG. 25 is an enlarged top, front and right side perspective view of a fourth embodiment of the partially transparent IC card;

FIG. 26 is a top plan view thereof;

FIG. 27 is a front elevational view thereof;

FIG. 28 is a rear elevational view thereof;

FIG. 29 is a right side elevational view thereof;

FIG. 30 is a left side elevational view thereof;

FIG. 31 is a bottom plan view thereof; and,

FIG. 32 is a greatly enlarged cross-sectional view thereof, taken along line 32—32 in FIG. 31.

The broken line drawings in FIGS. 1, 2, 7, 9, 10, 15, 17, 18, 23, 25, 26 and 31 are for illustrative purposes only and form no part of the claimed design.

Claims

The ornamental design for partially transparent IC card, as shown and described.

Referenced Cited
U.S. Patent Documents
D271298 November 8, 1983 Fujimoto
D283893 May 20, 1986 Fujimoto
D347215 May 24, 1994 Ikenaga
D358586 May 23, 1995 Miyazaki et al.
D368903 April 16, 1996 Ohmori et al.
D369156 April 23, 1996 Ohmori et al.
D369157 April 23, 1996 Ohmori et al.
D375303 November 5, 1996 Gaumet
D379006 April 29, 1997 Gaumet
D389130 January 13, 1998 Ishihara
D392954 March 31, 1998 Ikenaga
D407392 March 30, 1999 Kleineidam
D416886 November 23, 1999 Hirai et al.
D427168 June 27, 2000 Iwasaki
D427577 July 4, 2000 Haas et al.
Other references
  • Toshiba MOS Digital Integrated Circuit Silicon Gate CMOS 128 Mbit (16M×8bit) CMOS NAND E 2 PROM (16M Byte SmartMedia™), Toshiba, Nov. 6, 1998.
  • Toshiba MOS Digital Integrated Circuit Silicon Gate CMOS 64 Mbit (8M×8bit) CMOS NAND E 2 PROM (8M byte SmartMedia™), Toshiba, Nov. 6, 1998.
Patent History
Patent number: D443622
Type: Grant
Filed: Nov 26, 1999
Date of Patent: Jun 12, 2001
Assignee: Kabushiki Kaisha Toshiba (Kawasaki)
Inventors: Hiroshi Iwasaki (Yokohama), Osami Suzuki (Tokyo)
Primary Examiner: M. H. Tung
Attorney, Agent or Law Firm: Oblon, Spivak, McClelland, Maier & Neustadt, P.C.
Application Number: 29/114,440
Classifications
Current U.S. Class: And Rectangular Cover (e.g., Floppy) (D14/479)
International Classification: 1402;