Face panel for a dual processor board

- Sun Microsystems, Inc.
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Description

FIG. 1 is a perspective view of the face panel for a dual processor board with the swiveling handle in a folded position, viewed from a position to the right of the face panel, with the portion shown in broken line forming no part of the claimed design.

FIG. 2 is a plan view of the face panel for a dual processor board with the swiveling handle in a folded position, with the portion shown in broken line forming no part of the claimed design.

FIG. 3 is a perspective view of the face panel for a dual processor board with the swiveling handle in a folded position, viewed from a position to the left of the face panel, with the portion shown in broken line forming no part of the claimed design.

FIG. 4 is a perspective view of the face panel for a dual processor board with the swiveling handle in an extended position, viewed from a position to the right of the face panel, with the portion shown in broken line forming no part of the claimed design.

FIG. 5 is a plan view of the face panel for a dual processor board with the swiveling handle in an extended position; and,

FIG. 6 is a perspective view of the face panel for a dual processor board with the swiveling handle in an extended position, viewed from a position to the left of the face panel, with the portion shown in broken line forming no part of the claimed design.

The design consists of the ornamental shape of a face panel for a dual processor board of a computer system. The face panel is the portion of the dual processor that remains visible after the dual processor board is fully inserted into a slot of a computer system. Surfaces behind the face panel are not a part of the design.

Claims

The ornamental design for a face panel for a dual processor board, as shown and described.

Referenced Cited
U.S. Patent Documents
5708552 January 13, 1998 Han et al.
5774343 June 30, 1998 Benson et al.
D409159 May 4, 1999 Wein, Jr.
D415116 October 12, 1999 Creutz et al.
6067225 May 23, 2000 Reznikov et al.
6080930 June 27, 2000 Lommen et al.
6304456 October 16, 2001 Wortman
6370035 April 9, 2002 De Cecco et al.
Patent History
Patent number: D475027
Type: Grant
Filed: May 17, 2002
Date of Patent: May 27, 2003
Assignee: Sun Microsystems, Inc. (Santa Clara, CA)
Inventors: Christopher H. Frank (Campbell, CA), Adam Richardson (Oakland, CA)
Primary Examiner: Ted Shooman
Assistant Examiner: Selina Sikder
Attorney, Agent or Law Firm: O'Melveny & Myers LLP
Application Number: 29/160,899
Classifications
Current U.S. Class: Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)
International Classification: 1303;