Substrate with surface patterns
Description
FIG. 1 is a top plan view of a substrate with surface patterns showing my new design;
FIG. 2 is a rear plan view;
FIG. 3 is an end elevation view of FIG. 1; and,
FIG. 4 is a side elevation side elevation of FIG. 1.
Claims
The ornamental design for a substrate with surface patterns, as shown and described.
Referenced Cited
U.S. Patent Documents
3337681 | August 1967 | Smith |
3499972 | March 1970 | Smith |
3619481 | November 1971 | Smith |
3692926 | September 1972 | Smith |
3701839 | October 1972 | Smith |
4135553 | January 23, 1979 | Evans et al. |
4209352 | June 24, 1980 | Diaz et al. |
4337374 | June 29, 1982 | Smith |
4338970 | July 13, 1982 | Krackeler et al. |
4472222 | September 18, 1984 | Moisson et al. |
4954213 | September 4, 1990 | Jos et al. |
4954670 | September 4, 1990 | Jensen et al. |
4962286 | October 9, 1990 | Jensen et al. |
5568584 | October 22, 1996 | Smith |
5793921 | August 11, 1998 | Wilkins et al. |
6177634 | January 23, 2001 | Smith |
Patent History
Patent number: D510327
Type: Grant
Filed: Feb 12, 2002
Date of Patent: Oct 4, 2005
Inventor: Donald J. Smith (Westlake Village, CA)
Primary Examiner: Philip S. Hyder
Assistant Examiner: Selina Sikder
Application Number: 29/150,501
Type: Grant
Filed: Feb 12, 2002
Date of Patent: Oct 4, 2005
Inventor: Donald J. Smith (Westlake Village, CA)
Primary Examiner: Philip S. Hyder
Assistant Examiner: Selina Sikder
Application Number: 29/150,501
Classifications
Current U.S. Class:
Semiconductor, Transistor Or Integrated Circuit (24) (D13/182)