Circuit pack
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Description
The top, bottom, and sides of the circuit pack are unornamented.
The broken lines are shown for illustrative purposes only and form no part of the claimed design.
Claims
The ornamental design for a circuit pack, as shown and described.
Referenced Cited
U.S. Patent Documents
5777846 | July 7, 1998 | Hayes et al. |
D405799 | February 16, 1999 | Ino |
5964611 | October 12, 1999 | Jacob et al. |
D424066 | May 2, 2000 | Wheatley et al. |
D449032 | October 9, 2001 | Kiesekamp et al. |
6370035 | April 9, 2002 | De Cecco et al. |
6683252 | January 27, 2004 | Sobel et al. |
D530316 | October 17, 2006 | Hsu et al. |
20050094359 | May 5, 2005 | Lee et al. |
20060045457 | March 2, 2006 | Ng et al. |
Patent History
Patent number: D564455
Type: Grant
Filed: Mar 3, 2004
Date of Patent: Mar 18, 2008
Assignee: Nortel Networks Limited (St. Laurent)
Inventors: Yim Kwong Ng (Nepean), Edward Chen (Manotick), Michael Campbell (Ottawa)
Primary Examiner: Selina Sikder
Attorney: Guerin & Rodriguez, LLP
Application Number: 29/200,741
Type: Grant
Filed: Mar 3, 2004
Date of Patent: Mar 18, 2008
Assignee: Nortel Networks Limited (St. Laurent)
Inventors: Yim Kwong Ng (Nepean), Edward Chen (Manotick), Michael Campbell (Ottawa)
Primary Examiner: Selina Sikder
Attorney: Guerin & Rodriguez, LLP
Application Number: 29/200,741
Classifications
Current U.S. Class:
Switch Or Casing Therefor (18) (D13/158)