Module with built-in integrated circuits for use with IC cards
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Description
The portions shown in broken lines are for illustrative purposes only and form no part of the claimed design.
Claims
We claim the ornamental design for a module with built-in integrated circuits for use with IC cards, as shown and described.
Referenced Cited
U.S. Patent Documents
Foreign Patent Documents
5027190 | June 25, 1991 | Haghiri-Tehrani et al. |
D327883 | July 14, 1992 | Gloton |
D328599 | August 11, 1992 | Gloton |
D357909 | May 2, 1995 | Gloton |
D358142 | May 9, 1995 | Gloton |
D365092 | December 12, 1995 | Mundigl et al. |
D387746 | December 16, 1997 | Ishihara |
D388066 | December 23, 1997 | Ishihara |
D389130 | January 13, 1998 | Ishihara |
D412164 | July 20, 1999 | Laviron et al. |
D412888 | August 17, 1999 | Coveley |
6076737 | June 20, 2000 | Gogami et al. |
D427577 | July 4, 2000 | Haas et al. |
D456414 | April 30, 2002 | Turin |
6641049 | November 4, 2003 | Luu |
981863 | May 1997 | JP |
1196836 | February 2004 | JP |
Patent History
Patent number: D571810
Type: Grant
Filed: Nov 15, 2006
Date of Patent: Jun 24, 2008
Assignee: Kabushiki Kaisha Toshiba
Inventor: Hidetaka Ikeda (Yokohama)
Primary Examiner: Melanie Tung
Assistant Examiner: Susan Moon Lee
Attorney: Banner & Witcoff, Ltd.
Application Number: 29/268,869
Type: Grant
Filed: Nov 15, 2006
Date of Patent: Jun 24, 2008
Assignee: Kabushiki Kaisha Toshiba
Inventor: Hidetaka Ikeda (Yokohama)
Primary Examiner: Melanie Tung
Assistant Examiner: Susan Moon Lee
Attorney: Banner & Witcoff, Ltd.
Application Number: 29/268,869
Classifications
Current U.S. Class:
Icu Chip (D14/437)