Ethernet tester

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Description

FIG. 1 is a front right isometric view of an ethernet tester showing my new design.

FIG. 2 is a front elevational view thereof.

FIG. 3 is a rear elevational view thereof.

FIG. 4 is a left elevational view thereof.

FIG. 5 is a right elevational view thereof.

FIG. 6 is a top plan view thereof; and,

FIG. 7 is a bottom plan view thereof.

Portions shown in phantom lines are for purposes of enablement and are not a part of the claimed design.

Claims

The ornamental design for an ethernet tester, as shown and described.

Referenced Cited
U.S. Patent Documents
D366220 January 16, 1996 Sakamoto
D383400 September 9, 1997 Wada
D386099 November 11, 1997 Billington
D397050 August 18, 1998 Mohammadian et al.
D443538 June 12, 2001 Wrisley et al.
D444084 June 26, 2001 Wrisley et al.
D444085 June 26, 2001 Wrisley et al.
D444086 June 26, 2001 Wrisley et al.
D474413 May 13, 2003 Hoofnagle et al.
Other references
  • Psiber Data Systems Inc., LanMaster 26 User's Guide, 2004.
  • Psiber Data Systems Inc., LanMaster 35 Power and Link Tester User Guide, Copyright 2006.
  • PowerDsine, Inc., PowerDsine Power over Ethernet Tester, Feb. 16, 2008, P/N 1005-0350-0001 Rev. A, www.microsemi.com/PowerDsine/Products/Midspan/PoE—Tester.asp, San Diego, CA.
Patent History
Patent number: D596969
Type: Grant
Filed: Apr 18, 2008
Date of Patent: Jul 28, 2009
Inventor: Darrell A. Igelmund (Newcastle, WA)
Primary Examiner: Antoine D Davis
Attorney: Black Lowe & Graham PLLC
Application Number: 29/307,413