Electronics enclosure
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Description
The broken line portion of the figure drawings is included to show unclaimed subject matter only and forms no part of the claimed designs.
Claims
The ornamental design for an electronics enclosure, as shown and described.
Referenced Cited
Patent History
Patent number: D802582
Type: Grant
Filed: Aug 8, 2016
Date of Patent: Nov 14, 2017
Assignee: General Electric Company (Schenectady, NY)
Inventors: Andrew Louis Krivonak (Erie, PA), Theodore Clark Brown (Ripley, NY), Shreenath Shekar Perlaguri (Bangalore), Rajendra Yammanuru (Bangalore), Michael Jay Grutkowski (Erie, PA), Arunpandi Radhakrishnan (Puliyampatti)
Primary Examiner: Freda S. Nunn
Application Number: 29/573,548
Type: Grant
Filed: Aug 8, 2016
Date of Patent: Nov 14, 2017
Assignee: General Electric Company (Schenectady, NY)
Inventors: Andrew Louis Krivonak (Erie, PA), Theodore Clark Brown (Ripley, NY), Shreenath Shekar Perlaguri (Bangalore), Rajendra Yammanuru (Bangalore), Michael Jay Grutkowski (Erie, PA), Arunpandi Radhakrishnan (Puliyampatti)
Primary Examiner: Freda S. Nunn
Application Number: 29/573,548
Classifications
Current U.S. Class:
Cabinet (D14/308)