Electronics enclosure
Description
The broken lines environment is for illustration only and forms no part of the claimed design.
Claims
The ornamental design for an electronics enclosure, as shown and described.
Referenced Cited
U.S. Patent Documents
D332443 | January 12, 1993 | Sharpe |
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D441735 | May 8, 2001 | Katayama |
D531190 | October 31, 2006 | Lee |
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Patent History
Patent number: D887448
Type: Grant
Filed: Nov 6, 2015
Date of Patent: Jun 16, 2020
Inventor: Bernard Jeffery Thompson (Bellevue, WA)
Primary Examiner: Prabhakar Deshmukh
Application Number: 29/544,910
Type: Grant
Filed: Nov 6, 2015
Date of Patent: Jun 16, 2020
Inventor: Bernard Jeffery Thompson (Bellevue, WA)
Primary Examiner: Prabhakar Deshmukh
Application Number: 29/544,910
Classifications