Analog multiplexer

Abstract

A fast analog multiplexer is disclosed which utilizes a plurality of paral MOSFETs coupled to a plurality of parallel analog inputs, the gates of said MOSFETs being controlled by a binary decoder to allow passage of only on analog voltage to be summed by an op amp while concomitantly shorting other analog voltages to ground, thereby attenuating the delaying summed capacitive effects of stacked parallel MOSFETs.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to the field of electronics. More specifically, the invention is directed to a circuit for a high speed analog multiplexer for data acquisition systems.

1. Description of the Prior Art

Analog multiplexers generally allow one of many signals to pass. This function lets many channels share one analog-to-digital, A/D, converter in a time slice fashion. Since the analog to digital converter is often the most expensive part of a data acquisition system, the ability to share the converter can significantly reduce the system cost. Known analog multiplexers provide a low resistance path from input to output for the chosen channel and a high resistance path to all other channels. Existing systems generally use analog switches comprised of parallel pairs of complementary channel MOSFETs. The outputs of such systems are all tied together to provide a single output. The sum of all MOSFET drain and source capacitances from all the off channels however, is seen at the output. Such an approach creates settling times that are too long to take advantage of state of the art analog-to-digital converters. Hence, current analog multiplexers have become the limiting factor in economical data acquisition system advancement.

Thus, there exists a continuing need for a faster analog multiplexer not limited by MOSFET source/drain capacitive discharge settling times to more efficiently take advantage of fast state-of-the-art analog-to-digital converters.

SUMMARY OF THE INVENTION

A high speed analog multiplexer circuit has a plurality of analog voltage inputs coupled through an equal number of series pairs of resistors to the inverting input of an op amp; the noninverting input of said op amp being coupled to ground. An equal plurality of MOSFETs coupled in parallel with each other are coupled between each respective resistor pair (source) to a common ground (drain). The gates of each said MOSFETs are coupled in parallel to a 4 bit binary decoder, and the substrates of each MOSFET are coupled in parallel to a -15 volt power source. A feedback resistor couples the output of the op amp to an analog voltage suimming node at the inverting input of the op amp. The decoder operates at a very high speed on the gates of each MOSFET concurrently, setting only one selected gate low (turning it off) while all other such gates are asserted high. The effect being that only one analog input is passed to the op amp while all other analog inputs are shorted to ground through the conducting MOSFETs.

OBJECT OF THE INVENTION

It is a primary object of the invention to provide a higher speed analog multiplexer than exist in the art.

A further object of the invention is to provide an analog multiplexer comprising fewer components, especially A/D converters, than exist in the art.

Yet another object of the invention is to provide an analog multiplexer greatly reduced cost.

These and further objects and more advantageous features of the present invention will become more readily apparent in view of the attached drawing illustrating a description of a preferred embodiment as described herein.

BRIEF DESCRIPTION OF THE DRAWING

The FIGURE illustrates a schematic of a preferred embodiment of the invention.

DESCRIPTION OF A PREFERRED EMBODIMENT

The invention employs a novel modification of an analog adder circuit. Referring to the FIGURE, a selected analog input signal, e.g. V.sub.3, is passed to a summing node (.SIGMA.n) while the other analog input signals (i.e. V.sub.0 through V.sub.2 and V.sub.4 through V.sub.15) in such a manner as to protect signal source summing node .SIGMA.n from also being grounded. Not only the portion of the circuit processing V.sub.0 through V.sub.3 is illustrated in the FIGURE since it would be obvious and redundant to show all 15 MOSFETs. All MOSFETs in this embodiment operate in the same manner as the four illustrated.

In the operational circuit illustrated a four-to-sixteen decoder 11, which may be a, 54HC154 will provide a low to one C output, e.g. C.sub.3 corresponding to a binary number input A B C D to decoder 11. The C.sub.0 through C.sub.15 outputs of decoder 11 are sequentially coupled to C.sub.0 through C.sub.15 inputs of a summing branch circuit 12. Summing branch circuit 12 comprises sixteen parallel MOSFETs, which may be of the same type, designated 5D5000, of which only are shown M.sub.0 through M.sub.3, yielding outputs at nodes N.sub.0 through N.sub.15. Only N.sub.0 through N.sub.3 are shown.

Considering the operation of a single section, a low asserted on, C.sub.3 will hold the gate (G) of M.sub.3 low, which will no longer permit current to flow from the drain (D) through the substrate (SU) to the source (SO) "ground" of MOSFET M.sub.3, thereby effectively turning off M.sub.3. Concurrently, all other outputs C.sub.0 through C.sub.2 and C.sub.4 through C.sub.15 of decoder 11 will be held high, and thereby holding the gates of M.sub.0 through M.sub.2 and M.sub.4 through M.sub.15 high, and holding M.sub.0 through M.sub.2 and M.sub.4 through M.sub.15 in an on state, effectively passing V.sub.0 through V.sub.2 and V.sub.4 through V.sub.15 analog signals to ground.

For clarity of understanding, MOSFETs M.sub.0 through M.sub.15 can be modeled as a variable resistance when turned off. In considering the path for V.sub.3, V.sub.G is a virtual ground present at the inverting input to an op amp 13 due to feedback through a feedback resistor R.sub.FB. Op amp 13 may be a CL200 if desire. Each input channel represented by input signals V.sub.0 through V.sub.15 provides a current (i) to V.sub.G. The sum of these currents times R.sub.B gives the output voltage V.sub.out of op amp 13.

All resistors illustrated in the circuit other than R.sub.FB are 100K .OMEGA., and R.sub.FB =200K .OMEGA..

Although there has been described hereinabove a particular arrangement of an analog multiplexer circuit for the purpose of illustrating the manner in which the invention may be used to advantage, it will be appreciated that the invention is not limited thereto. Accordingly, any and all modifications, variations, or equivalent arrangements which may occur to those skilled in the art should be considered to be within the scope of the invention as defined in the appended claim.

Claims

1. An analog multiplexer, comprising:

an op amp having an inverted and noninverting input and an output and further having a summing node coupled to said inverting input and a feedback resistor coupling said output to said inverting input;

at least two analog inputs each having a resistance coupling to said summing nodes;

an equal number of MOSFETs as said analog inputs, each said MOSFET having a drain, a source, a substrate, and a gate, said drain of each said MOSFET being connected to said resistance coupling, said source of each said MOSFET being only coupled to a common signal return, and said substrate of each said MOSFET being coupled to power source;

decoder-driving means having a plurality of digital inputs and a plurality of driver outputs, said driver outputs being equal in number to said MOSFETs, each said driver output being coupled to said gates of each said respective MOSFET, for receiving a digital command input, and for driving one said gate of each said MOSFET low and driving said gates of all other MOSFETs high.