Voltage-programming scheme for current-driven AMOLED displays

- Ignis Innovation Inc.

A system and method for driving an AMOLED display is provided. The AMOLED display includes a plurality of pixel circuits. A voltage-programming scheme, a current-programming scheme or a combination thereof is applied to drive the display. Threshold shift information, and/or voltage necessary to obtain hybrid driving circuit may be acquired. A data sampling may be implemented to acquire a current/voltage relationship. A feedback operation may be implemented to correct the brightness of the pixel.

Skip to: Description  ·  Claims  ·  References Cited  · Patent History  ·  Patent History
Description

Notice: More than one reissue application has been filed for the reissue of U.S. Pat. No. 8,232,939. The reissue applications are (1) Ser. No. 14/090,320, which is an application for reissue of U.S. Pat. No. 8,232,939 and has been reissued as U.S. Pat. No. RE45,291 E, (2) application Ser. No. 14/326,705 (the present application), which is a continuation reissue of U.S. Pat. No. 8,232,939, and (3) application Ser. No. 14/326,677, which is a divisional reissue of U.S. Pat. No. 8,232,939.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a continuation of U.S. patent application Ser. No. 11/571,480, which is a national stage application of international application no. PCT/CA2005/001007, filed Jun. 28, 2005, which claims the benefit of and priority to Canadian Patent Application No. 2,472,671, filed on Jun. 29, 2004, each of these applications being incorporated herein by reference in its entirety.

FIELD OF INVENTION

The present invention relates to a display technique, and more specifically to technology for driving pixel circuits.

BACKGROUND OF THE INVENTION

Active matrix organic light emitting diode (AMOLED) displays are well known in the art. The AMOLED displays have been increasingly used as a flat panel in a wide variety of tools.

The AMOLED displays are classified as either a voltage-programmed display or a current-programmed display. The voltage-programmed display is driven by a voltage-programmed scheme where data is applied to the display as a voltage. The current-programmed display is driven by a current-programmed scheme where data is applied to the display as a current.

The advantage of the current-programming scheme is that it can facilitate pixel designs where the brightness of the pixel remains more constant over time than with voltage programming. However, the current-programming requires longer time of charging capacitors associated with the column.

Therefore, there is a need to provide a new scheme for driving a current-driven AMOLED display, which ensures high speed and high quality.

SUMMARY OF THE INVENTION

The present invention relates to a system and method of driving a pixel circuit in an AMOLED display.

The system and method of the present invention uses Voltage-Programming Scheme For Current-Driven AMOLED Displays.

In accordance with an aspect of the present invention there is provided a system for driving a display which includes a plurality of pixel circuits, each having a plurality of thin film transistors (TFTs) and an organic light emitting diode (OLED), which includes: a voltage driver for generating a voltage to program the pixel circuit; a programmable current source for generating a current to program the pixel circuit; and a switching network for selectively connecting the data driver or the current source to one or more pixel circuits.

In accordance with a further aspect of the present invention there is provided a system for driving a pixel circuit having a plurality of thin film transistors (TFTs) and an organic light emitting diode (OLED), which includes: a pre-charge controller for pre-charging and discharging a data node of the pixel circuit to acquire threshold voltage information of the TFT from the data node; and a hybrid driving circuit for programming the pixel circuit based on the acquired threshold voltage information and video data information displayed on the pixel circuit.

In accordance with a further aspect of the present invention there is provided a system for driving a pixel circuit having a plurality of thin film transistors (TFTs) and an organic light emitting diode (OLED), which includes: a sampler for sampling, from a data node of the pixel circuit, a voltage required to program the pixel circuit; and a programming circuit for programming the pixel circuit based on the sampled voltage and video data information displayed on the pixel circuit.

In accordance with a further aspect of the present invention there is provided a method of driving a pixel circuit having a plurality of thin film transistors (TFTs) and an organic light emitting diode (OLED), which includes the steps of: selecting a pixel circuit and pre-charging a data node of the pixel circuit; allowing the pre-charged data node to be discharged; extracting a threshold voltage of the TFT through the discharging step; and programming the pixel circuit, including compensating a programming data based on the extracted threshold voltage.

This summary of the invention does not necessarily describe all features of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other features of the invention will become more apparent from the following description in which reference is made to the appended drawings wherein:

FIG. 1 is a block diagram showing a system for driving an AMOLED display in accordance with an embodiment of the present invention;

FIG. 2 is a schematic diagram showing one example of a pixel circuit of FIG. 1;

FIG. 3 is a schematic diagram showing an example of a hybrid driving circuit, which is applicable to FIG. 1;

FIG. 4 is an exemplary flow chart for showing the operation of the hybrid driving circuit of FIG. 3;

FIG. 5 is an exemplary timing chart for showing the operation of the hybrid driving circuit of FIG. 3;

FIG. 6 is a schematic diagram showing a further example of a hybrid driving circuit, which is applicable to FIG. 1;

FIG. 7 is an exemplary flow chart for showing the operation of the hybrid driving circuit of FIG. 6;

FIG. 8 is a schematic diagram showing a further example of a hybrid driving circuit, which is applicable to FIG. 1;

FIG. 9 is an exemplary flow chart for showing the operation of the hybrid driving circuit of FIG. 8;

FIG. 10 is an exemplary timing chart for showing the operation of the hybrid driving circuit of FIG. 8;

FIG. 11 is a schematic diagram showing a further example of the pixel circuit of FIG. 1;

FIG. 12 is a block diagram showing a system for driving an AMOLED display in accordance with a further embodiment of the present invention;

FIG. 13 is an exemplary flow chart for showing the operation of the system of FIG. 12;

FIG. 14 is an exemplary flow chart for showing the operation of the system of FIG. 12;

FIG. 15 is an exemplary timing chart for showing the operation of the system of FIG. 12;

FIG. 16 is an exemplary flow chart for a hidden refresh operation of the system of FIG. 12;

FIG. 17 is a diagram showing an example of a sample of the current/voltage correction curve;

FIG. 18 is a diagram showing the current/voltage correction curve of FIG. 17 and an example of a newly measured data point:

FIG. 19 is a diagram showing an example of a new current/voltage correction curve based on the measured point of FIG. 18;

FIG. 20 is a block diagram showing a further example of a programming circuit for implementing a combined current and voltage-programming technique;

FIG. 21 is a block diagram showing a system for driving an AMOLED display in accordance with a further embodiment of the invention;

FIG. 22 is a schematic diagram showing an example of a switch network of FIG. 21; and

FIG. 23 is a schematic diagram showing a system for correcting the current/voltage information of the pixel circuit.

 DETAILED DESCRIPTION

Embodiments of the present invention are described using an AMOLED display. Drive scheme described below is applicable to a current programmed (driven) pixel circuit and a voltage programmed (driven) pixel circuit.

In addition, hybrid technique described below can be applied to any existing driving scheme, including a) any drive schemes that use sophisticated timing of the data, select, or power inputs to the pixels to achieve increased brightness uniformity, b) any drive schemes that use current or voltage feedback, c) any drive schemes that use optical feedback.

The light emitting material of the pixel circuit can be any technology, specifically organic light emitting diode (OLED) technology, and in particular, but not limited to, fluorescent, phosphorescent, polymer, and dendrimer materials.

Referring to FIG. 1, there is illustrated a system 2 for driving an AMOLED display 5 in accordance with an embodiment of the present invention. The AMOLED display 5 includes a plurality of pixel circuits. In FIG. 1, four pixel circuits 10 are shown as an example.

The system 2 includes a hybrid driving circuit 12, a voltage source driver 14, a hybrid programming controller 16, a gate driver 18A and a power-supply 18B. The pixel circuit 10 is selected by the gate driver 18A (Vsel), and is programmed by either voltage mode using a node Vdata or current mode using a node Idata. The hybrid driving circuit 12 selects the mode of programming, and connects it to the pixel circuit 10 through a hybrid signal. A pre-charge signal (Vp) is applied to the pixel circuit 10 to acquire threshold Vt information (or Vt shift information) from the pixel circuit 10. The hybrid driving circuit 12 controls the pre-charging, if pre-charging technique is used. The pre-charge signal (Vp) may be generated within the hybrid driving circuit 12, which depends on the operation condition. The power-supply 18B (Vdd) supplies the current required to energize the display 5 and to monitor the power consumption of the display 5.

The hybrid controller 16 controls the individual components that make up the entire hybrid programming circuit. The hybrid controller 16 handles timing and controls the order in which the required functions occur. The hybrid controller 16 may generate data Idata and supplied to the hybrid driving circuit 12. The system 2 may have a reference current source, and the Idata may be supplied under the control of the hybrid controller 16.

The hybrid driver 12 may be implemented either as a switching matrix, or as the hybrid driving circuit(s) of FIG. 3, 6, 8 or 20 or combination thereof.

In the description, Vdata refers to data, a data signal, a data line or a node for supplying the data or data signal Vdata, or a voltage on the data line or the node. Similarly, Idata refers to data, a data signal, a data line or a node for supplying the data or data signal Idata, or a current on the data line or the node. Vp refers to a pre-charge signal, a pre-charge pulse, a pre-charge voltage for pre-charging/discharging, a line or a node for supplying the pre-charge signal, pre-charge pulse or pre-charge voltage Vp. Vsel refers to a pulse or a signal for selecting a pixel circuit or a line or a node for supplying the pulse or signal Vs. The terms “hybrid signal”, “hybrid signal node”, and “hybrid signal line” may be used interchangeably.

The pixel circuit 10 includes a plurality of TFTs, and an organic light emitting diode (OLED). The TFT may be an n-type TFT or a p-type TFT. The TFT is, for example, but not limited to, an amorphous silicon (a-Si:H) based TFT, a polycrystalline silicon based TFT, a crystalline silicon based TFT, or an organic semiconductor based TFT. The OLED may be regular (P-I-N) stack or inverted (N-I-P) stack. The OLED can be located in the source or the drain of one or more driving TFTs.

FIG. 2 illustrates an example of the pixel circuit 10 of FIG. 1. The pixel circuit of FIG. 2 includes four thin film transistors (TFTs) 20-26, a capacitor Cs 28 and an organic light emitter diode (OLED) 30. The TFT (Tdrive) 26 is a drive TFT that is connected to the OLED 30 and the capacitor Cs 28. The pixel circuit of FIG. 2 is selected by the select line Vsel, and is programmed by a data line DL. The data line DL is controlled by the hybrid signal output from the hybrid driving circuit 12 of FIG. 1.

In FIG. 2, four TFTs are illustrated. However, the pixel circuit 10 of FIG. 1 may include less than four TFTs or more than four TFTs.

In the description, the terms “data line DL” and “data node DL” may be used interchangeably.

Referring to FIGS. 1-2, the data node DL is pre-charged and discharged to acquire the threshold Vt of a drive TFT (e.g., Tdrive 26 of FIG. 2) or the threshold Vt shift. In the description, Vt shift, Vt shift information, Vt, and Vt information may be used interchangeably. The pixel circuit 10 is then consecutively programmed by the source driver 14 using voltage-programming. The acquired Vt shift information is utilized to compensate for degradation of the pixel circuit 10, thus maintaining uniform brightness of the display 5.

The process of acquiring Vt starts by applying Vsel to T1 20 and T2 22 to the pixel circuit illustrated in FIG. 2. Such action causes the drain and gate of T3 24 to be at the same voltage. This allows the Vt of T3 24 to be extracted by first applying the pre-charge voltage Vp to the data line DL, which is than allowed to be discharged. The rate of discharge is a function of Vt. Thus, by measure of the rate of discharge, Vt can be obtained.

FIG. 3 illustrates an example of a hybrid driving circuit, which is applicable to the hybrid driving circuit 12 of FIG. 1. The hybrid driving circuit 12A of FIG. 3 implements voltage programming technique.

The hybrid driving circuit 12A of FIG. 3 includes a charge programming capacitor Cc 32. The charge programming capacitor Cc 32 is provided between the data line Vdata and the data node DL. The pre-charge line Vp is also connected to the data node DL.

The hybrid driving circuit 12A is provided to a pixel circuit 10A having four TFTs (such as the pixel circuit of FIG. 2). However, the pixel circuit 10A may include more than four TFTs or less than four TFTs.

The charge programming capacitor Cc 32 is provided to program the pixel circuit 10A with a voltage that is equal to the sum of threshold Vt of the TFT and Vdata, scaled by a constant K. The constant is determined by the voltage division network formed by the charge storage capacitor (e.g. Cs 28 of FIG. 2) and the charge programming capacitor Cc 32.

FIG. 4 illustrates an exemplary flow chart for showing the operation of the hybrid driving circuit 12A of FIG. 3. At step S10, pre-charge mode is enabled. At step S12, a pixel circuit is selected and pre-charging (Vp) is started. At step S14, Vt acquisition mode is enabled, and at step S16, discharging (Vp) starts. The Vt information is acquired through Cc 32. Then at step S18, writing mode is enabled.

FIG. 5 illustrates an exemplary timing chart for showing the operation of the hybrid driving circuit 12A of FIG. 3. In the drawings, Vdata0 represents voltage at the data node (e.g. DL of FIG. 2) of the pixel circuit; Idata0 represents current at the data node (e.g. DL of FIG. 2) of the pixel circuit.

The programming procedure starts by selecting the pixel to be programmed with the pulse Vsel. At the same time, the pre-charge pulse Vp is applied to the pixel circuit's data input (e.g. DL of FIG. 2).

During the Vt acquisition phase, voltage on the data line (DL) is allowed to be discharged through the pixel circuit, which is in a current mirror connection with the Vsel line held high. The data line (DL) is discharged to a certain voltage, and the Vt of a drive TFT is extracted from that voltage. The voltage at Vdata is at ground.

During the programming (writing) phase, the calculated compensated voltage is applied to the data input line (DL) of the pixel circuit. The programming routine finishes with the lowering of the Vsel signal.

The calculated compensated voltage is obtained through analog means of a charge programming capacitor Cc32. However, any other analog means for obtaining compensated voltage may be used. Further, any (external) digital circuit (e.g. 50 of FIG. 7) may be used to obtain the calculated compensated voltage.

The source driver (14 of FIG. 1) supplies Vdata to the capacitor Cc 32. When Vdata is increased from ground to the desired voltage level, the voltage at Idata is equal to (Vt+Vdata)*K.

The structure of FIG. 3 is simple, and is easily implemented.

FIG. 6 illustrates a further example of a hybrid driving circuit, which is applicable to the hybrid driving circuit 12 of FIG. 1. The hybrid driving circuit 12B of FIG. 6 implements voltage programming technique.

The hybrid driving circuit 12B includes a summer 40, a sample and hold (S/H) circuit 42 and a switching element 44. The S/H circuit 42 samples Idata and holds it for a certain period. The summer 40 receives Vdata and the output of the S/H circuit 42. The switching element 44 connects the output of the summer 40 to the data node DL in response to a programming control signal 46.

The hybrid driving circuit 12B utilizes the summer 40, instead of the charge coupling capacitor Cc 32, to produce programming voltage that is equal to the sum of Vt and Vdata. As the hybrid driving circuit 12B does not utilize a capacity, programming voltage is not affected by the parasitic capacitance, and it has less charge feed-through effect. As the hybrid driving circuit 12B does not utilize a charge storage capacitor, programming voltage is not affected by the charge storage capacitance. As the hybrid driving circuit 12B does not utilize a charge programming capacitor, it achieves faster Vt acquisition time. Removal of the charge programming capacitor eliminates the charge dependency of the programming scheme. Thus the programming voltage is not affected by the charge being shared between the charge storage capacitor and the parasitic capacitance of the system. This results in a higher effective programming voltage.

FIG. 7 illustrates an exemplary flow chart for showing the operation of the hybrid driving circuit 12B of FIG. 6. During the Vt acquisition mode, the Vt is sampled at step S20, and new data is produced at step S22. When writing mode is enabled, the new data is supplied to the pixel circuit in response to the programming control signal (46) at S24. It is noted that the operation of the system having the hybrid driving circuit 12B is not limited to FIG. 7. The new data may be produced after step S18. The control signal 46 may be enabled before step S18.

During the Vt acquisition cycle, Vdata is at ground, and the voltage at the data node DL is equal to Vt of the TFT by the pre-charging/discharging operation (Vp). The voltage on the data node DL is sampled and holed by the S/H circuit 42. The Vt is provided to the summer 40 through the S/H circuit 42. When Vdata is increased from ground to the desired voltage level, the summer 40 outputs the sum of Vt and Vdata. The switch 44 turns on in response to the programming control signal 46. The voltage at the data node DL goes to (Vt+Vdata). Timing chart for showing the operation of the system 2 having the hybrid driving circuit 12B is similar to that of FIG. 5.

FIG. 8 illustrates a further example of a hybrid driving circuit, which is applicable to the hybrid driving circuit 12 of FIG. 1. The hybrid driving circuit 12C of FIG. 8 implements voltage programming technique.

The hybrid driving circuit 13C is a direct digital hybrid driving circuit. The direct digital programming circuit 13C includes a microComputer uC 50 which receives digital data (Vdada), a digital to analog (D/A) converter 52, a voltage follower 54 for increasing current without affecting voltage, and an analog to digital (A/D) converter 56.

The threshold Vt of the drive TFT may increase slowly. Thus, it may not be necessary to acquire the threshold Vt of the drive TFT every programming cycle. This effectively hides the Vt acquisition for the majority of the programming cycle. In the direct digital hybrid driving circuit 13C, the threshold Vt acquired from the pixel circuit 10A is digitalized at the A/D converter 56, and is stored in memory contained in the uC 50. The digital data that defines the brightness of the pixel is added to the Vt in the uC 50. The resulting voltage is then converted back to an analog value at the D/A 52, which is programmed into the pixel circuit 10A. This programming method is designed to compensate for the slow process of the Vt acquisition.

FIG. 9 illustrates an exemplary flow chart for showing the operation of the hybrid driving circuit 12C of FIG. 8. At the Vt acquisition mode, the Vt is sampled and recorded at step S30. When writing mode is enabled, new data is provided based on the recorded data. It is noted that the operation of the system having the hybrid driving circuit 12C of FIG. 8 is not limited to FIG. 9. At the writing mode, the data which have been recorded may be used without implementing the Vt acquisition.

FIG. 10 illustrates an exemplary timing chart for showing the operation of the hybrid driving circuit 12C of FIG. 8. During the Vt acquisition, sampling by the A/D converter 56 is implemented. In a next cycle, the hybrid driving circuit 13C may use the Vt that has been previously acquired and has been recorded in the uC 50.

The conversion of the output on the data node DL by A/D can remove the requirements of having to acquire the Vt every programming cycle. The Vt of the pixel circuit 10A may be acquired once every second or less. Thus, it may acquire Vt for only one row of the display per frame cycle. This effectively increases the amount of time for the pixel programming cycle. Less frequent need of Vt acquisition ensures faster programming time.

In the above description, FIG. 2 is used to describe the pixel circuit 10 of FIG. 1. However, the pixel circuit 10 is not limited to that of FIG. 2. The pixel circuit 10 may be a pixel circuit illustrated in FIG. 11 (J. Kanichi, J.-H. Kim, J. Y. Nahm, Y. He and R. Hattori “Amorphous Silicon Thin-Film Transistor Based Active-Matrix Organic Light Emitting Display” Asia Display IDW 2001 pp. 315). The pixel circuit of FIG. 11 includes four TFTs 64-70, a capacitor CST 72 and an OLED 74. The TFT 78 is a drive TFT that is connected to the OLED 74 and the capacitor CST 72. The pixel circuit of FIG. 11 is selected by Vselect1 and Vselect2, and is programmed by Idata. The voltage acquired is a combination of the voltage across the OLED 74 and T3 68. The technique compensates the voltage change of both the Vt and the OLED 74. Idata of FIG. 11 corresponds to the data node DL of FIG. 2.

FIG. 12 illustrates a system for driving an AMOLED display in accordance with a further embodiment of the invention. The system 82 of FIG. 12 includes a hybrid programming circuit having a correction table 80, a source driver 14 for implementing a voltage-programming scheme and a reference current source 94 for implementing a current-programming scheme. The system 82 drives a display having a plurality of pixel circuits using the voltage-programming scheme and the current-programming scheme.

A hybrid controller 98 is provided to control each component. In FIG. 12, the hybrid controller 98 is placed between the A/D converter 96 and the correction table 80, as an example. The hybrid controller 98 is similar to the hybrid controller 16 of FIG. 1.

The pixel circuit driven by the system 82 may be the pixel circuit 10 of FIG. 1, and may be a current programmed pixel circuit or a voltage programmed pixel circuit. The pixel circuit driven by the system 82 may be implemented by FIG. 2 or FIG. 11, however, is not limited to those of FIGS. 2 and 11.

The hybrid programming circuit includes a correction calculation module 92 for correcting data from the data source 90 based on the correction table 80 and an A/D converter 96. The data corrected by the correction calculation module 92 is applied to the source driver 14. The source driver 14 generates Vdata based on the corrected data output from the correction calculation module 92. Vdata from the source driver 14 and Idata from the reference current source 94 are supplied to the hybrid driver 12.

The data source 90 is, for example, but not limited to, a DVD. The hybrid driver 12 may be implemented either as a switching matrix, or as the digital programming circuit(s) of FIG. 8, 20 or combination thereof. The A/D converter 96 may be the A/D converter 56 of FIG. 8. The system 82 may implement the Vt acquisition technique described above using the A/D converter 96 (56).

The correction table 80 is a lookup table. The correction table 80 records the relationship between current required to program the pixel circuit and voltage necessary to obtain that current. The correction table 80 is built for every pixel in the entire display.

In the description, the relationship between the current required to program the pixel circuit and the voltage necessary to obtain that programming current, is referred to as “current/voltage correction information”, “current/voltage correction curve”, or “current/voltage information”, or “current voltage curve”.

In FIG. 12, the correction table 80 is illustrated separately from the correction calculation module 92. However, the correction table 80 may be included in the correction calculation module 92.

The operation of the system of FIG. 12 has two modes, namely display mode and calibration mode. In the display mode, the data from the data source 90 is corrected using the data in the correction table 80, and is applied to the source driver 14. The hybrid driver 12 is not involved in the display mode. In the calibration mode, the current from the reference current source 94 is applied to the pixel circuit, and the voltage associated with the current is read from the pixel circuit. The voltage is converted to a digital data by the A/D converter 96. The correction table 80 is updated with the correct value based on the digital data.

During the display mode, a voltage-programming scheme is implemented. The voltage on the data line (e.g. DL of FIG. 2) of the pixel circuit determines the brightness of the pixels. The voltage required to program the pixel circuit is calculated from the pixel brightness to be displayed (from the incoming video information) combined with the current/voltage correction information stored in the correction table 80. The information on the correction table 80 is combined with incoming video information to ensure that each pixel will maintain a constant brightness over long-term use.

After the display has been used for a fixed period of time, the display enters the calibration mode. The current source 94 is connected to the data input node (DL) of the pixel circuit via the hybrid driver 12. Each pixel is programmed through a current-programming scheme (where the level of current on the data line determines the brightness of the pixel), and the voltage required to achieve that current is read by the A/D converter 96.

The voltage required to program the pixel current is sampled at multiple current points by the A/D converter 96. The multiple points may be a subset of the possible current levels (e.g. 256 possible levels for 8-bit, or 64 levels for 6-bit). This subset of voltage measurements is used to construct the correction table 80 that is interpolated from the measurement points.

The calibration mode may be entered either through user's command or may be combined with the normal display mode so that the calibration takes place during the display refresh period.

In one example, the entire display may be calibrated at once. The display may stop showing incoming video information for a short period of time while each pixel was programmed with a current and the voltage recorded.

In a further example, a subset of the pixels may be calibrated, such as one pixel every fixed number of frames. This is virtually transparent to the user, and the correction information may still be acquired for each pixel.

When a conventional voltage-programming scheme is utilized, a pixel circuit is programmed in an open loop configuration, where there is no feedback from the pixel circuit regarding the threshold voltage shift of the TFTs. When a conventional current-programming scheme is utilized, the brightness of the pixel may remain constant over time. However, the current programming scheme is slow. Thus, the table lookup technique combines the technique of the current-programming scheme with the technique of the voltage-programming scheme. The pixel circuit is programmed with a current through a current-programming scheme. A voltage to maintain that current is read and is stored at a lookup table. The next time that particular level of current is applied to the pixel circuit, instead of programming with a current, the pixel circuit is programmed based on information on the lookup table. Accordingly, it attains the compensation inherent in the current programming scheme while attaining the fast programming time that is only possible with voltage-programming scheme.

In the above description, the correction table (lookup table) 80 is used to correct the current/voltage correction information. However, the system 82 of FIG. 12 may use the lookup table to correct the Vt shift and the current/voltage correction information at the same time in combination with the hybrid driving circuit of FIG. 3, 6, 8 or 20.

For example, several voltage measurements are captured at many different current points by the A/D converter 96 (56). The hybrid controller 98 extracts the Vt shift information by extending the voltage versus current curve to zero current point. The Vt shift information is stored in an array of tables (correction table 80) which is applied to incoming display data.

The uC 50 of FIG. 8 or 20 may utilize the lookup table to generate appropriate voltage and program the pixel circuit.

The hybrid circuits 12A of FIGS. 3 and 12B of FIG. 6 may be integrated into the system of FIG. 12.

FIGS. 13-14 illustrate exemplary flow charts for showing the operation of the system of FIG. 12. Referring to FIG. 13, at step S40, calibration mode is enabled. At step S42, a pixel circuit is selected and current programming is implemented to the selected pixel circuit. At step S44, a switch matrix enable signal is enabled. Then the connection to the pixel circuit is changed. The Vt is sampled at step s46, and then the correction table is created/corrected at step S48. Referring to FIG. 14, at step S50, video data are corrected based on the correction table. Then at step S52, new Vdata is produced based on the corrected data.

It is noted that the writing mode may be implemented based on the previously created correction table without implementing the calibration mode. It is noted that the operation of the system of FIG. 12 is not limited to FIGS. 13-14.

FIG. 15 illustrates an exemplary timing chart for showing a combination of the Vt shift acquisition and the current/voltage correction. A switch matrix enable signal in FIG. 15 represents a control signal for the hybrid driver 12 of FIG. 12.

Referring to FIGS. 12 and 15, the calibration mode (i.e. the current-programming scheme) is enabled when the switch matrix enable signal is high. The programming mode (i.e. the voltage-programming scheme) is enabled when the switch matrix enable signal is low. However, the calibration mode may be enabled when the switch matrix enable signal is low. The programming mode may be enabled when the switch matrix enable signal is high.

A/D sampling is implemented during the calibration mode. During the calibration mode, the current from the reference current source 94 is applied to the pixel circuit. The voltage on the data input node is converted to a digital voltage by the A/D converter 56. Based on the digital voltage and current associated with the digital voltage, current/voltage correction information is recorded at the lookup table. The Vt shift information is generated based on the data in the correction table 80 or the output from the A/D converter 96.

The system 82 of FIG. 12 may implement hidden refresh technique for refreshing current/voltage correction information in addition to the table lookup technique described above.

Under the hidden refresh operation, new current/voltage correction information is constructed while completely hidden from user's perception. This technique utilizes the information that is currently displayed on the screen (i.e. the incoming video data). By obtaining the pixel characteristics from the full calibration routine that has been performed during the manufacturing process of the display, the current/voltage correction information for each pixel in the display is known. During the display's usage, the current/voltage correction curve may shift due to the change in Vt. By measuring a single point along the current/voltage correction curve (which is the data currently displayed, that is part of the video image), a new current/voltage correction curve is extrapolated from the point so that it is fitted to the measured point. Based on the new current/voltage correction curve, the Vt shift information is extracted which is used to compensate for the shift in Vt.

FIG. 16 illustrates an exemplary flow chart for the hidden refresh operation of the system of FIG. 12. First, a current/voltage correction curve is produced during the calibration process that is implemented during the manufacturing of the display (step S62). FIG. 17 illustrates an example of a sample of the current voltage correction curve.

Referring to FIG. 16, the next step is to measure a point along the curve during the usage of the display. This point can be any point along the curve, so any data that the user currently has on the display can be used for calibration (step S64). FIG. 18 illustrates the current voltage correction of FIG. 17 and an example of a newly measured data point.

Referring to FIG. 16, the last step is to shift the current/voltage correction curve to fit the point of voltage verses current relationship that is measured (step S66). FIG. 19 illustrates an example of a new current voltage correction curve based on the measured point of FIG. 18.

The process associated with FIGS. 17-19 is implemented in the hybrid controller 98 of FIG. 12.

The system 82 of FIG. 12 may implement a combined current and voltage-programming technique. FIG. 20 illustrates one example of a hybrid driving circuit for implementing the combined current and voltage-programming technique. The hybrid driving circuit of FIG. 20 may be included in the hybrid driver 12 of FIG. 12.

In the hybrid driving circuit of FIG. 20, the digital hybrid driving circuit 12C and a current source 100 are provided to the data line DL of the pixel circuit.

To enhance the circuit's ability to compensate for a change in the current/voltage correction curve due to temperature, threshold voltage shift, or other factors, the pixel circuit programming is divided into two phases.

During the writing mode, the pixel circuit 10A is voltage-programmed first to set the gate voltage of the driving TFT to an approximate value, then followed by a current programming phase. The current programming phase can then fine-tune the output current. The system of FIG. 20 is faster than current programming and has the compensation capabilities of the current programming scheme.

In FIG. 20, the digital hybrid driving circuit 12C is provided. However, the combined current and voltage-programming technique may be implemented by combining the hybrid driving circuit 12A of FIG. 3 or 12B of FIG. 6 with the current source 100. The current source 100 may be the reference current source 94 of FIG. 12.

The system 2 of FIG. 1 may implement the hidden refresh technique described above. The system 2 of FIG. 1 may implement the combined current and voltage-programming technique. The system 2 of FIG. 1 may include the hybrid driving circuit of FIG. 20 to implement the combined current and voltage-programming technique.

Extension of the direct digital programming scheme is now described in detail. The direct digital programming scheme (FIGS. 6, 8 and 20) can be extended to drive an OLED array (e.g. a 4T OLED array) using voltage programmed column drivers, such as those used for driving Active Matrix Liquixd Crystal Display (AMLCD), or voltage-programmed Active-Matrix Organic Light Emitting Diode (AMOLED) displays, or any other voltage-output display driver.

FIG. 21 illustrates a system for driving an AMOLED array having a plurality of pixel circuits in accordance with a further embodiment of the invention. The system 105 of FIG. 21 includes a voltage column driver 112, a programmable current source 114, a switching network 116, an A/D converter 118 and a row driver 120.

The voltage column driver 112 is a voltage programmed column driver. Each of the voltage column driver 112 and the row driver 120 may be any driver that has a voltage output, such as those designed for the AMLCD. The voltage column driver 112 and the programmable current source 114 are connected to an OLED array 110 through the switching network 116. The OLED array 110 forms an AMOLED display, and contains a plurality of pixel circuits (such as 10 of FIG. 1). The pixel circuit may be a current programmed pixel circuit or a voltage programmed pixel circuit.

The A/D converter 118 is an interface that allows an analog signal (i.e. current driving the display 110) to be read back as a digital signal. The digital signal associated with the current can than be processed and/or stored. The A/D converter 118 may be the A/D converter 56 of FIGS. 8 and 20. The column driver 112 may be the source driver 14 of FIGS. 1 and 12.

The system 105 of FIG. 21 implements the calibration mode and the display mode as described above.

FIG. 22 illustrates an example of the switch network 116 of FIG. 21. The switching network 116 of FIG. 22 includes two MOSFET switches 122 and 124 that can switch the column of the display (110) from connecting to the column driver (112) to the combination of the current source (114) and the A/D converter (118), and vice versa. A shift register 126 is a source of the digital control signal that controls the operation of the MOS switches 122 and 124. An inverter 128 inverts an output from the shift register 126. Thus, when the switch 122 is on (off), the switch 124 is off (on).

The switching network 116 may be located either off the glass in the column driver (112) or directly on the glass using TFT switches.

Referring to FIGS. 21-22, the system 105 uses only one current source 114. The voltage-programming drivers (such as, AMLCD drivers, or any other voltage-output drivers) drive the rest of the display 110. The switching matrix (switching network 116) allows different pixels within the array of pixels to be connected to a single current source (114) through a time division method. This allows a single current source to be applied to the entire display. This lowers the cost of the driver circuit and speeds up the programming time for the pixel circuit.

The system 105 uses the A/D converter 118 to convert an analog output of the data node (e.g. DL of FIG. 2) of the pixel circuit to digital data. The conversion by the A/D converter 118 removes the requirements of having to acquire the Vt every programming cycle. The Vt of the pixel circuit may be acquired once every few minutes. Thus it may acquire one column of the panel every refresh cycle.

Only one A/D 118 may be implemented for all the columns. The circuit acquires only one pixel per frame refresh. For example, for a 320 by 240 panel, the number of pixels is 76, 8000. For a frame rate of 30 Hz, the time required to acquire Vt from all pixels for the entire frame is 43 minutes. This may be acceptable for some applications, providing that Vt does not shift substantially in an hour.

The parasitics only affect the amount of time to discharge the capacitor to acquire Vt. Since the circuit is voltage-programmed, it is not affected by the parasitics. Since Vt is only acquired one column per frame time, it can be long. For example, for a display with 320 columns that has a frame rate of 30 Hz, each frame time is 33 mS. For voltage programming, it is possible to program a pixel in 70 uS. For 320 columns, the time to update the display is 22 mS, which still leave 11 mS to complete a charge/discharge cycle.

The system 105 may implement the lookup table technique to compensate for Vt shift and/or to correct the current/voltage information as described above

The system 105 may implement the hidden refresh technique to acquire the Vt shift information and current/voltage correction information of each pixel circuit (10) in the display 110. This current/voltage correction information is used to populate a lookup table (e.g. a correction table 80 of FIG. 12) that will then be used to compensate for the degradation in the pixel circuit, which is caused by aging. To reduce cost, the number of current-programmed circuits has been reduced so there is only one per display instead of one per column driver.

The system 105 may implement the combined current and voltage-programming technique as described above.

The current/voltage information of the pixel circuit can be further corrected by implementing a system illustrated in FIG. 23. FIG. 23 illustrates a system for correcting the current/voltage information of the pixel circuit. In FIG. 23, a display 130 is depicted as a 2T or 4T OLED array. However, the display 130 may include a plurality of pixel circuits, each having three or more than four transistors. The display 130 may include voltage-driven pixel circuits or current-driven pixel circuits. The system of FIG. 23 is applicable to the systems 2, 82 and 105 of FIGS. 1, 12 and 22.

As illustrated in FIG. 23, a switch 132 is provided to disconnect the common electrode of the OLED. It is well known that two electrodes are provided for the OLED. One is connected to the pixel circuit, and the other is a common electrode connected to all OLEDs. It is noted that the common electrode may be Vdd or GND depending on the type of OLED. The switch 132 connects the common electrode of the OLED into a current sensing network 134 utilizing a high side common mode sensor (such as, INA168 by TI). The current sensing network 134 measures the current through the common electrode.

During the calibration phase, each pixel is lit individually and the current consumed is acquired by the sensing network 134. The acquired current is used to correct the lookup table (e.g. the correction table 80 of FIG. 12) populated by the direct digital hybrid driving circuit of FIG. 8 or 20.

A dark display current may be acquired to include the effect of dead pixel and leakage current of the array. During this procedure, all pixels are turned off, and the current (i.e. dark display current) is measured.

According to the embodiments of the present invention, the major issue with current-programmed pixel circuits, which is the slow programming time, is solved. The concept of using feedback to compensate the pixel circuit enhances the uniformity and stability of the display while retaining the fast programming capability of the voltage programmed drive scheme.

The present invention has been described with regard to one or more embodiments. However, it will be apparent to persons skilled in the art that a number of variations and modifications can be made without departing from the scope of the invention as defined in the claims.

Claims

1. A system for programming at least one pixel circuit in a display, the system comprising:

a voltage driver for generating a voltage to apply to a data node of the at least one pixel circuit to thereby program the at least one pixel circuit according to the generated voltage;
a programmable current source for providing a first current and a second current to apply to the data node of the at least one pixel circuit;
a sampler for reading a first voltage on the data node while the first current is maintained through the at least one pixel circuit via the programmable current source and for reading a second voltage on the data node while the second current is maintained through the at least one pixel circuit via the programmable current source; and
a controller configured to: generate a voltage versus current relationship for the at least one pixel circuit based on the first current and the second current and based on the sampled first and second voltages, extract, based on the voltage versus current relationship for the at least one pixel circuit, a voltage corresponding to a zero current level, and program the at least one pixel circuit via the data node with a programming voltage generated by the voltage driver that is set according to display data and according to the extracted voltage corresponding to the zero current level.

2. The system according to claim 1, wherein the at least one pixel circuit is configured to be alternately programmed by a programming current applied to the data node or by a programming voltage applied to the data node.

3. The system according to claim 2, wherein the at least one pixel circuit includes a mirror transistor having a gate coupled to a gate terminal of the driving transistor, the at least one pixel circuit configured such that the data node is coupled to a gate terminal of the mirror transistor via one or more switch transistors, the applied current being conveyed via the one or more switch transistors through the mirror transistor while the gate terminal of the mirror transistor adjusts to a voltage for maintaining the applied current through the mirror transistor.

4. The system according to claim 3, wherein the one or more switch transistors include a first switch transistor and a second transistor,

the first switch transistor operated according to a select signal and configured to couple the data node to the gate terminal of the mirror transistor while the first switch transistor is switched on,
the second switch transistor operated according to the select signal and configured to couple the data node to a drain or a source terminal of the mirror transistor while the second switch transistor is switched on.

5. The system according to claim 2, wherein the at least one pixel circuit includes one or more switch transistors configured to couple the data node to a drain or a source terminal of the driving transistor while the programming current is applied to the at least one pixel circuit via the data node,

the one or more switch transistors further configured to couple the data node to a gate terminal of the driving transistor while the programming current is applied, such that the gate terminal of the driving transistor adjusts to a voltage for maintaining the applied current through the driving transistor,
the one or more switch transistors further configured to couple the data node to a gate terminal of the driving transistor while the programming voltage is applied to the at least one pixel circuit via the data node.

6. The system according to claim 1, wherein the sampler includes an analog to digital converter configured to capture digital information indicative of the first and second voltages on the data node.

7. The system according to claim 6, further comprising a memory for storing the digital information indicative of the first and second voltages, the digital information being stored in a lookup table that associates the first and second voltages with the first and second currents to thereby characterize the voltage versus current relationship of the at least one pixel circuit.

8. The system according to claim 1, wherein the controller is further configured to instruct the voltage driver to set the programming voltage for the at least one pixel circuit by adding the voltage corresponding to the zero current level to a voltage indicated by the display data.

9. The system according to claim 1, wherein the at least one pixel circuit is a plurality of pixel circuits arranged in an array of rows and columns, each of the plurality of pixel circuits having a data node coupled to a data line, and wherein the programmable current source is configured to generate a plurality currents to apply to each of the plurality of pixel circuits and the sampler is configured to read a corresponding plurality of voltages for each of the plurality of pixel circuits while each of the plurality of currents is maintained through respective ones of the plurality of pixel circuits.

10. The system according to claim 1, wherein the controller is configured to extract the threshold voltage of the driving transistor of the at least one pixel circuit by extending the voltage versus current relationship for the at least one pixel circuit to the zero current level and determining the voltage corresponding to the zero current level, the voltage corresponding to the zero current level providing an estimate of the threshold voltage of the driving transistor of the at least one pixel circuit.

11. The system according to claim 1, further comprising a memory communicatively coupled to the controller for digitally storing digital information indicative of the first and second voltages.

12. The system according to claim 1, wherein the at least one pixel circuit includes an organic light emitting diode for emitting light according to the display data and one or more thin film transistors for conveying a current through the organic light emitting diode according to the display data.

13. A method of operating a display having at least one pixel circuit, the at least one pixel circuit having a light emitting device coupled in series with a driving transistor configured to convey a driving current through the light emitting device according to display information, the at least one pixel circuit configured to be alternately programmed according to the display information by a programming current applied to a data node of the at least one pixel circuit or by a programming voltage applied to the data node, the method comprising:

applying a first current to the data node of the at least one pixel circuit;
reading a first voltage on the data node while the first current is maintained through the at least one pixel circuit;
applying a second current to the data node of the at least one pixel circuit;
reading a second voltage on the data node while the second current is maintained through the at least one pixel circuit;
storing digital information indicative of the first and second voltages such that the first and second voltages are associated with the first and second currents;
generating a voltage versus current relationship for the at least one pixel circuit based on the first and second voltages and the first and second currents;
extracting, based on the generated voltage versus current relationship for the at least one pixel circuit, a voltage corresponding to a zero current level; and
programming the at least one pixel circuit by applying, to the data node of the at least one pixel circuit, a programming voltage that is based on the display data and the voltage corresponding to the zero current level.

14. The method according to claim 13, wherein the at least one pixel circuit is at least one of a plurality of pixel circuits arranged in an array of rows and columns in the display, and wherein the applying the first and second current, the reading the first and second voltages, the storing, the generating, and the extracting are applied to each of the plurality of pixel circuits such that voltages corresponding to the zero current level are extracted for each of the plurality of pixel circuits.

15. The method according to claim 14, wherein the voltage corresponding to the zero current level is an estimate of a threshold voltage of the driving transistor in the at least one pixel circuit, and wherein the programming is applied to each of the plurality of pixel circuits based on the display data for each of the plurality of pixel circuits and based on the estimate of the threshold voltage of the driving transistor for each of the plurality of pixel circuits such that the display is operated to compensate for the threshold voltages of the driving transistors in each of the plurality of pixel circuits.

16. The method according to claim 13, wherein the storing is carried out by digitally storing the digital information indicative of the first and second voltages in a lookup table associated with the at least one pixel circuit.

17. The method according to claim 13, wherein the applying the first current and the applying the second current are performed during a calibration mode of the display that is distinct from a normal display mode, the calibration mode being a period during which images are not shown on the display.

18. The method according to claim 13, wherein at least one of the first current or the second current is a programming current applied to the at least one pixel circuit during a programming operation of a normal display mode to program the at least one pixel circuit to emit light according to the display information.

19. The method according to claim 13, wherein the at least one pixel circuit is at least one of a plurality of pixel circuits arranged in an array of rows and columns in the display, and wherein at least one of the first current or the second current is a programming current applied to the at least one pixel circuit during a programming operation of a normal display mode while others of the plurality of pixel circuits are voltage programmed with programming voltages, thereby hiding the applying the at least one of the first current or the second current to the at least one pixel circuit.

20. The method according to claim 13, further comprising:

responsive to the extracting, applying a third current to the data node of the at least one pixel circuit;
reading a third voltage on the data node while the third current is maintained through the at least one pixel circuit;
storing digital information indicative of the third voltage such that the third voltage is associated with the third current;
updating the voltage versus current relationship for the at least one pixel circuit based on at least the third voltage and the third current;
extracting, based on the updated voltage versus current relationship for the at least one pixel circuit, a voltage corresponding to a zero current level, the voltage corresponding to the zero current level being an updated estimate of a threshold voltage of the driving transistor in the at least one pixel circuit; and
programming the at least one pixel circuit to compensate for the threshold voltage of the driving transistor by applying, to the data node of the at least one pixel circuit, a programming voltage that is based on the display data and the updated estimated threshold voltage.

21. A system for programming at least one pixel circuit in a display, the system comprising:

a voltage driver for generating a voltage to apply to a data node of the at least one pixel circuit to thereby program the at least one pixel circuit according to the generated voltage;
a programmable current source for providing a first current to apply to the data node of the at least one pixel circuit;
a sampler for reading a first voltage on the data node while the first current is maintained through the at least one pixel circuit via the programmable current source; and
a controller configured to:
receive calibration data indicative of a voltage versus current relationship for the at least one pixel circuit;
generate an updated voltage versus current relationship for the at least one pixel circuit based on the first current and the first voltage and based on the received calibration data,
extract, based on the updated voltage versus current relationship for the at least one pixel circuit, a voltage corresponding to a zero current level, and
program the at least one pixel circuit via the data node with a programming voltage generated by the voltage driver that is set according to display data and according to the extracted voltage corresponding to the zero current level.

22. The system according to claim 21, wherein the first current is a programming current applied to the at least one pixel circuit during a programming operation of a normal display mode to program the at least one pixel circuit to emit light according to the display information.

23. The system according to claim 21, wherein the at least one pixel circuit is configured to be alternately programmed by a programming current applied to the data node or by a programming voltage applied to the data node.

24. The system according to claim 21, wherein the at least one pixel circuit is a plurality of pixel circuits arranged in an array of rows and columns, each of the plurality of pixel circuits having a data node coupled to a data line, and wherein the programmable current source is configured to generate a plurality currents to apply to each of the plurality of pixel circuits and the sampler is configured to read a corresponding plurality of voltages for each of the plurality of pixel circuits while each of the plurality of currents is maintained through respective ones of the plurality of pixel circuits.

25. The system according to claim 21, wherein the sampler includes an analog to digital converter configured to capture digital information indicative of the first and second voltages on the data node.

26. The system according to claim 25, further comprising a memory for storing the digital information indicative of the first voltage, the digital information being stored in a lookup table that associates the first voltage with the first current to thereby characterize the voltage versus current relationship of the at least one pixel circuit.

27. The system according to claim 21, wherein the at least one pixel circuit includes an organic light emitting diode for emitting light according to the display data and one or more thin film transistors for conveying a current through the organic light emitting diode according to the display data.

28. A method of operating a display having at least one pixel circuit, the at least one pixel circuit having a light emitting device coupled in series with a driving transistor configured to convey a driving current through the light emitting device according to display information, the at least one pixel circuit configured to be alternately programmed according to the display information by a programming current applied to a data node of the at least one pixel circuit or by a programming voltage applied to the data node, the method comprising:

applying a first current to the data node of the at least one pixel circuit;
reading a first voltage on the data node while the first current is maintained through the at least one pixel circuit;
storing digital information indicative of the first voltage such that the first voltage is associated with the first current;
receiving calibration data indicative of a voltage versus current relationship for the at least one pixel circuit;
generating an updated voltage versus current relationship for the at least one pixel circuit based on the first voltage, the first current, and the received calibration data;
extracting, based on the updated voltage versus current relationship for the at least one pixel circuit, a voltage corresponding to a zero current level; and
programming the at least one pixel circuit by applying, to the data node of the at least one pixel circuit, a programming voltage that is based on the display data and the voltage corresponding to the zero current level.

29. The method according to claim 28, wherein the at least one pixel circuit is at least one of a plurality of pixel circuits arranged in an array of rows and columns in the display, and wherein the applying the first current, the reading the first voltage, the storing, the receiving, the generating, and the extracting are applied to each of the plurality of pixel circuits such that voltages corresponding to the zero current level are extracted for each of the plurality of pixel circuits.

30. The method according to claim 29, wherein the voltage corresponding to the zero current level is an estimate of a threshold voltage of the driving transistor in the at least one pixel circuit, and wherein the programming is applied to each of the plurality of pixel circuits based on the display data for each of the plurality of pixel circuits and based on the estimate of the threshold voltage of the driving transistor for each of the plurality of pixel circuits such that the display is operated to compensate for the threshold voltages of the driving transistors in each of the plurality of pixel circuits.

31. A method of calibrating a display panel having a plurality of pixel circuits, each of the pixel circuits including a drive transistor coupled to an organic light emitting device, comprising:

measuring a degradation of each pixel circuit of a subset of the pixel circuits during a frame while displaying a video image with the pixel circuits on the display panel;
extracting, for each of the pixel circuits of the subset, a current/voltage point for the pixel circuit from the degradation measurement;
determining, for each of the pixel circuits of the subset, corresponding compensation information from a fitting of a previously stored voltage versus current relationship for the pixel circuit to the extracted current/voltage point for the pixel circuit; and
compensating each of the pixel circuits of the subset based on the respective compensation information for each of the pixel circuits of the subset.

32. The method of claim 31, wherein each of the pixel circuits are programmed using current, while the degradation measurement is a voltage measurement.

33. The method of claim 31, wherein the measuring is carried out without stopping video information from being displayed on the display panel.

34. The method of claim 33, wherein the measuring is carried out during a refresh period of the display panel.

35. The method of claim 31, wherein the measuring, extracting, and determining are carried out externally from the pixel circuit.

Referenced Cited
U.S. Patent Documents
3506851 April 1970 Polkinghorn et al.
3774055 November 1973 Bapat et al.
4090096 May 16, 1978 Nagami
4160934 July 10, 1979 Kirsch
4354162 October 12, 1982 Wright
4758831 July 19, 1988 Kasahara et al.
4943956 July 24, 1990 Noro
4963860 October 16, 1990 Stewart
4975691 December 4, 1990 Lee
4996523 February 26, 1991 Bell et al.
5051739 September 24, 1991 Hayashida et al.
5153420 October 6, 1992 Hack et al.
5198803 March 30, 1993 Shie et al.
5204661 April 20, 1993 Hack et al.
5206633 April 27, 1993 Zalph
5222082 June 22, 1993 Plus
5266515 November 30, 1993 Robb et al.
5489918 February 6, 1996 Mosier
5498880 March 12, 1996 Lee et al.
5572444 November 5, 1996 Lentz et al.
5589847 December 31, 1996 Lewis
5619033 April 8, 1997 Weisfield
5648276 July 15, 1997 Hara et al.
5670973 September 23, 1997 Bassetti et al.
5686935 November 11, 1997 Weisbrod
5691783 November 25, 1997 Numao et al.
5712653 January 27, 1998 Katoh et al.
5714968 February 3, 1998 Ikeda
5723950 March 3, 1998 Wei et al.
5744824 April 28, 1998 Kousai et al.
5745660 April 28, 1998 Kolpatzik et al.
5747928 May 5, 1998 Shanks et al.
5748160 May 5, 1998 Shieh et al.
5784042 July 21, 1998 Ono et al.
5790234 August 4, 1998 Matsuyama
5815303 September 29, 1998 Berlin
5870071 February 9, 1999 Kawahata
5874803 February 23, 1999 Garbuzov et al.
5880582 March 9, 1999 Sawada
5903248 May 11, 1999 Irwin
5917280 June 29, 1999 Burrows et al.
5923794 July 13, 1999 McGrath et al.
5945972 August 31, 1999 Okumura et al.
5949398 September 7, 1999 Kim
5952789 September 14, 1999 Stewart et al.
5952991 September 14, 1999 Akiyama et al.
5982104 November 9, 1999 Sasaki et al.
5990629 November 23, 1999 Yamada et al.
6023259 February 8, 2000 Howard et al.
6069365 May 30, 2000 Chow et al.
6081131 June 27, 2000 Ishii
6091203 July 18, 2000 Kawashima et al.
6097360 August 1, 2000 Holloman
6144222 November 7, 2000 Ho
6157583 December 5, 2000 Starnes et al.
6166489 December 26, 2000 Thompson et al.
6177915 January 23, 2001 Beeteson et al.
6225846 May 1, 2001 Wada et al.
6229506 May 8, 2001 Dawson et al.
6229508 May 8, 2001 Kane
6232939 May 15, 2001 Saito et al.
6246180 June 12, 2001 Nishigaki
6252248 June 26, 2001 Sano et al.
6259424 July 10, 2001 Kurogane
6262589 July 17, 2001 Tamukai
6271825 August 7, 2001 Greene et al.
6274887 August 14, 2001 Yamazaki et al.
6288696 September 11, 2001 Holloman
6300928 October 9, 2001 Kim
6303963 October 16, 2001 Ohtani et al.
6304039 October 16, 2001 Appelberg et al.
6306694 October 23, 2001 Yamazaki et al.
6307322 October 23, 2001 Dawson et al.
6310962 October 30, 2001 Chung et al.
6316786 November 13, 2001 Mueller et al.
6320325 November 20, 2001 Cok et al.
6323631 November 27, 2001 Juang
6323832 November 27, 2001 Nishizawa et al.
6345085 February 5, 2002 Yeo et al.
6348835 February 19, 2002 Sato et al.
6356029 March 12, 2002 Hunter
6365917 April 2, 2002 Yamazaki
6373453 April 16, 2002 Yudasaka
6373454 April 16, 2002 Knapp et al.
6384427 May 7, 2002 Yamazaki et al.
6392617 May 21, 2002 Gleason
6399988 June 4, 2002 Yamazaki
6414661 July 2, 2002 Shen et al.
6417825 July 9, 2002 Stewart et al.
6420758 July 16, 2002 Nakajima
6420834 July 16, 2002 Yamazaki et al.
6420988 July 16, 2002 Azami et al.
6433488 August 13, 2002 Bu
6437106 August 20, 2002 Stoner et al.
6445369 September 3, 2002 Yang et al.
6445376 September 3, 2002 Parrish
6468638 October 22, 2002 Jacobsen et al.
6473065 October 29, 2002 Fan
6475845 November 5, 2002 Kimura
6489952 December 3, 2002 Tanaka et al.
6501098 December 31, 2002 Yamazaki
6501466 December 31, 2002 Yamagishi et al.
6512271 January 28, 2003 Yamazaki et al.
6518594 February 11, 2003 Nakajima et al.
6522315 February 18, 2003 Ozawa et al.
6524895 February 25, 2003 Yamazaki et al.
6525683 February 25, 2003 Gu
6531713 March 11, 2003 Yamazaki
6531827 March 11, 2003 Kawashima
6542138 April 1, 2003 Shannon et al.
6559594 May 6, 2003 Fukunaga et al.
6573195 June 3, 2003 Yamazaki et al.
6573584 June 3, 2003 Nagakari et al.
6576926 June 10, 2003 Yamazaki et al.
6577302 June 10, 2003 Hunter et al.
6580408 June 17, 2003 Bae et al.
6580657 June 17, 2003 Sanford et al.
6583398 June 24, 2003 Harkin
6583775 June 24, 2003 Sekiya et al.
6583776 June 24, 2003 Yamazaki et al.
6587086 July 1, 2003 Koyama
6593691 July 15, 2003 Nishi et al.
6594606 July 15, 2003 Everitt
6597203 July 22, 2003 Forbes
6611108 August 26, 2003 Kimura
6617644 September 9, 2003 Yamazaki et al.
6618030 September 9, 2003 Kane et al.
6639244 October 28, 2003 Yamazaki et al.
6641933 November 4, 2003 Yamazaki et al.
6661180 December 9, 2003 Koyama
6661397 December 9, 2003 Mikami et al.
6668645 December 30, 2003 Gilmour et al.
6670637 December 30, 2003 Yamazaki et al.
6677713 January 13, 2004 Sung
6680577 January 20, 2004 Inukai et al.
6680580 January 20, 2004 Sung
6687266 February 3, 2004 Ma et al.
6690000 February 10, 2004 Muramatsu et al.
6690344 February 10, 2004 Takeuchi et al.
6693388 February 17, 2004 Oomura
6693610 February 17, 2004 Shannon et al.
6697057 February 24, 2004 Koyama et al.
6720942 April 13, 2004 Lee et al.
6724151 April 20, 2004 Yoo
6734636 May 11, 2004 Sanford et al.
6738034 May 18, 2004 Kaneko et al.
6738035 May 18, 2004 Fan
6753655 June 22, 2004 Shih et al.
6753834 June 22, 2004 Mikami et al.
6756741 June 29, 2004 Li
6756952 June 29, 2004 Decaux et al.
6756985 June 29, 2004 Hirotsune et al.
6771028 August 3, 2004 Winters
6777712 August 17, 2004 Sanford et al.
6777888 August 17, 2004 Kondo
6780687 August 24, 2004 Nakajima et al.
6781567 August 24, 2004 Kimura
6806497 October 19, 2004 Jo
6806638 October 19, 2004 Lin et al.
6806857 October 19, 2004 Sempel et al.
6809706 October 26, 2004 Shimoda
6815975 November 9, 2004 Nara et al.
6828950 December 7, 2004 Koyama
6853371 February 8, 2005 Miyajima et al.
6859193 February 22, 2005 Yumoto
6861670 March 1, 2005 Ohtani et al.
6873117 March 29, 2005 Ishizuka
6873320 March 29, 2005 Nakamura
6876346 April 5, 2005 Anzai et al.
6878968 April 12, 2005 Ohnuma
6885356 April 26, 2005 Hashimoto
6900485 May 31, 2005 Lee
6903734 June 7, 2005 Eu
6909114 June 21, 2005 Yamazaki
6909243 June 21, 2005 Inukai
6909419 June 21, 2005 Zavracky et al.
6911960 June 28, 2005 Yokoyama
6911964 June 28, 2005 Lee et al.
6914448 July 5, 2005 Jinno
6919871 July 19, 2005 Kwon
6924602 August 2, 2005 Komiya
6937215 August 30, 2005 Lo
6937220 August 30, 2005 Kitaura et al.
6940214 September 6, 2005 Komiya et al.
6943500 September 13, 2005 LeChevalier
6947022 September 20, 2005 McCartney
6954194 October 11, 2005 Matsumoto et al.
6956547 October 18, 2005 Bae et al.
6975142 December 13, 2005 Azami et al.
6975332 December 13, 2005 Arnold et al.
6995510 February 7, 2006 Murakami et al.
6995519 February 7, 2006 Arnold et al.
7022556 April 4, 2006 Adachi
7023408 April 4, 2006 Chen et al.
7027015 April 11, 2006 Booth, Jr. et al.
7027078 April 11, 2006 Reihl
7034793 April 25, 2006 Sekiya et al.
7038392 May 2, 2006 Libsch et al.
7057359 June 6, 2006 Hung et al.
7061451 June 13, 2006 Kimura
7064733 June 20, 2006 Cok et al.
7071932 July 4, 2006 Libsch et al.
7079091 July 18, 2006 Kondakov et al.
7088051 August 8, 2006 Cok
7088052 August 8, 2006 Kimura
7102378 September 5, 2006 Kuo et al.
7106285 September 12, 2006 Naugler
7112820 September 26, 2006 Chang et al.
7116058 October 3, 2006 Lo et al.
7119493 October 10, 2006 Fryer et al.
7122835 October 17, 2006 Ikeda et al.
7127380 October 24, 2006 Iverson et al.
7129914 October 31, 2006 Knapp et al.
7129917 October 31, 2006 Yamazaki et al.
7141821 November 28, 2006 Yamazaki et al.
7164417 January 16, 2007 Cok
7193589 March 20, 2007 Yoshida et al.
7199516 April 3, 2007 Seo et al.
7220997 May 22, 2007 Nakata
7224332 May 29, 2007 Cok
7227519 June 5, 2007 Kawase et al.
7235810 June 26, 2007 Yamazaki et al.
7245277 July 17, 2007 Ishizuka
7248236 July 24, 2007 Nathan et al.
7262753 August 28, 2007 Tanghe et al.
7264979 September 4, 2007 Yamagata et al.
7274345 September 25, 2007 Imamura et al.
7274363 September 25, 2007 Ishizuka et al.
7279711 October 9, 2007 Yamazaki et al.
7304621 December 4, 2007 Oomori et al.
7310092 December 18, 2007 Imamura
7315295 January 1, 2008 Kimura
7317429 January 8, 2008 Shirasaki et al.
7319465 January 15, 2008 Mikami et al.
7321348 January 22, 2008 Cok et al.
7339560 March 4, 2008 Sun
7339636 March 4, 2008 Voloschenko et al.
7355574 April 8, 2008 Leon et al.
7358941 April 15, 2008 Ono et al.
7368868 May 6, 2008 Sakamoto
7402467 July 22, 2008 Kadono et al.
7411571 August 12, 2008 Huh
7414600 August 19, 2008 Nathan et al.
7423617 September 9, 2008 Giraldo et al.
7432885 October 7, 2008 Asano et al.
7474285 January 6, 2009 Kimura
7485478 February 3, 2009 Yamagata et al.
7502000 March 10, 2009 Yuki et al.
7528812 May 5, 2009 Tsuge et al.
7535449 May 19, 2009 Miyazawa
7554512 June 30, 2009 Steer
7569849 August 4, 2009 Nathan et al.
7576718 August 18, 2009 Miyazawa
7580012 August 25, 2009 Kim et al.
7589707 September 15, 2009 Chou
7609239 October 27, 2009 Chang
7619594 November 17, 2009 Hu
7619597 November 17, 2009 Nathan et al.
7633470 December 15, 2009 Kane
7656370 February 2, 2010 Schneider et al.
7697052 April 13, 2010 Yamazaki et al.
7800558 September 21, 2010 Routley et al.
7825419 November 2, 2010 Yamagata et al.
7847764 December 7, 2010 Cok et al.
7859492 December 28, 2010 Kohno
7868859 January 11, 2011 Tomida et al.
7876294 January 25, 2011 Sasaki et al.
7924249 April 12, 2011 Nathan et al.
7932883 April 26, 2011 Klompenhouwer et al.
7948170 May 24, 2011 Striakhilev et al.
7969390 June 28, 2011 Yoshida
7978187 July 12, 2011 Nathan et al.
7994712 August 9, 2011 Sung et al.
7995010 August 9, 2011 Yamazaki et al.
8026876 September 27, 2011 Nathan et al.
8044893 October 25, 2011 Nathan et al.
8049420 November 1, 2011 Tamura et al.
8077123 December 13, 2011 Naugler, Jr.
8115707 February 14, 2012 Nathan et al.
8194063 June 5, 2012 Levey
8223177 July 17, 2012 Nathan et al.
8232939 July 31, 2012 Nathan et al.
8259044 September 4, 2012 Nathan et al.
8264431 September 11, 2012 Bulovic et al.
8279143 October 2, 2012 Nathan et al.
8339386 December 25, 2012 Leon et al.
8378362 February 19, 2013 Heo et al.
8493295 July 23, 2013 Yamazaki et al.
8497525 July 30, 2013 Yamagata et al.
8514212 August 20, 2013 Chou
8624805 January 7, 2014 McCreary
20010002703 June 7, 2001 Koyama
20010004190 June 21, 2001 Nishi et al.
20010009283 July 26, 2001 Arao et al.
20010013806 August 16, 2001 Notani
20010015653 August 23, 2001 De Jong et al.
20010020926 September 13, 2001 Kujik
20010024181 September 27, 2001 Kubota
20010024186 September 27, 2001 Kane et al.
20010026127 October 4, 2001 Yoneda et al.
20010026179 October 4, 2001 Saeki
20010026257 October 4, 2001 Kimura
20010026725 October 4, 2001 Petteruti et al.
20010030323 October 18, 2001 Ikeda
20010033199 October 25, 2001 Aoki
20010038098 November 8, 2001 Yamazaki et al.
20010040541 November 15, 2001 Yoneda et al.
20010043173 November 22, 2001 Troutman
20010045929 November 29, 2001 Prache et al.
20010052606 December 20, 2001 Sempel et al.
20010052898 December 20, 2001 Osame et al.
20010052940 December 20, 2001 Hagihara et al.
20020000576 January 3, 2002 Inukai
20020011796 January 31, 2002 Koyama
20020011799 January 31, 2002 Kimura
20020011981 January 31, 2002 Kuijk
20020012057 January 31, 2002 Kimura
20020014851 February 7, 2002 Tai et al.
20020015031 February 7, 2002 Fujita et al.
20020015032 February 7, 2002 Koyama et al.
20020018034 February 14, 2002 Ohki et al.
20020030190 March 14, 2002 Ohtani et al.
20020030528 March 14, 2002 Matsumoto et al.
20020030647 March 14, 2002 Hack et al.
20020036463 March 28, 2002 Yoneda et al.
20020047565 April 25, 2002 Nara et al.
20020047852 April 25, 2002 Inukai et al.
20020048829 April 25, 2002 Yamazaki et al.
20020050795 May 2, 2002 Imura
20020052086 May 2, 2002 Maeda
20020053401 May 9, 2002 Ishikawa et al.
20020067134 June 6, 2002 Kawashima
20020070909 June 13, 2002 Asano et al.
20020080108 June 27, 2002 Wang
20020084463 July 4, 2002 Sanford et al.
20020101172 August 1, 2002 Bu
20020101433 August 1, 2002 McKnight
20020105279 August 8, 2002 Kimura
20020113248 August 22, 2002 Yamagata et al.
20020117722 August 29, 2002 Osada et al.
20020122308 September 5, 2002 Ikeda
20020130686 September 19, 2002 Forbes
20020154084 October 24, 2002 Tanaka et al.
20020158587 October 31, 2002 Komiya
20020158666 October 31, 2002 Azami et al.
20020158823 October 31, 2002 Zavracky et al.
20020163314 November 7, 2002 Yamazaki et al.
20020167474 November 14, 2002 Everitt
20020180369 December 5, 2002 Koyama
20020180721 December 5, 2002 Kimura et al.
20020186214 December 12, 2002 Siwinski
20020190332 December 19, 2002 Lee et al.
20020190924 December 19, 2002 Asano et al.
20020190971 December 19, 2002 Nakamura et al.
20020195967 December 26, 2002 Kim et al.
20020195968 December 26, 2002 Sanford et al.
20030020413 January 30, 2003 Oomura
20030030603 February 13, 2003 Shimoda
20030043088 March 6, 2003 Booth et al.
20030057895 March 27, 2003 Kimura
20030058226 March 27, 2003 Bertram et al.
20030062524 April 3, 2003 Kimura
20030063081 April 3, 2003 Kimura et al.
20030071821 April 17, 2003 Sundahl et al.
20030076048 April 24, 2003 Rutherford
20030090445 May 15, 2003 Chen et al.
20030090447 May 15, 2003 Kimura
20030090481 May 15, 2003 Kimura
20030095087 May 22, 2003 Libsch
20030107560 June 12, 2003 Yumoto et al.
20030111966 June 19, 2003 Mikami et al.
20030122745 July 3, 2003 Miyazawa
20030122813 July 3, 2003 Ishizuki et al.
20030140958 July 31, 2003 Yang et al.
20030142088 July 31, 2003 LeChevalier
20030151569 August 14, 2003 Lee et al.
20030156101 August 21, 2003 Le Chevalier
20030169219 September 11, 2003 LeChevalier
20030174152 September 18, 2003 Noguchi
20030179626 September 25, 2003 Sanford et al.
20030197663 October 23, 2003 Lee et al.
20030206060 November 6, 2003 Suzuki
20030210256 November 13, 2003 Mori et al.
20030230141 December 18, 2003 Gilmour et al.
20030230980 December 18, 2003 Forrest et al.
20030231148 December 18, 2003 Lin et al.
20040027063 February 12, 2004 Nishikawa
20040032382 February 19, 2004 Cok et al.
20040056604 March 25, 2004 Shih et al.
20040066357 April 8, 2004 Kawasaki
20040070557 April 15, 2004 Asano et al.
20040070558 April 15, 2004 Cok et al.
20040070565 April 15, 2004 Nayar et al.
20040080262 April 29, 2004 Park et al.
20040080470 April 29, 2004 Yamazaki et al.
20040090186 May 13, 2004 Kanauchi et al.
20040090400 May 13, 2004 Yoo
20040095297 May 20, 2004 Libsch et al.
20040100427 May 27, 2004 Miyazawa
20040108518 June 10, 2004 Jo
20040113903 June 17, 2004 Mikami et al.
20040129933 July 8, 2004 Nathan et al.
20040130516 July 8, 2004 Nathan et al.
20040135749 July 15, 2004 Kondakov et al.
20040145547 July 29, 2004 Oh
20040150592 August 5, 2004 Mizukoshi et al.
20040150594 August 5, 2004 Koyama et al.
20040150595 August 5, 2004 Kasai
20040155841 August 12, 2004 Kasai
20040174347 September 9, 2004 Sun et al.
20040174349 September 9, 2004 Libsch
20040174354 September 9, 2004 Ono et al.
20040178743 September 16, 2004 Miller et al.
20040183759 September 23, 2004 Stevenson et al.
20040189627 September 30, 2004 Shirasaki et al.
20040196275 October 7, 2004 Hattori
20040201554 October 14, 2004 Satoh
20040207615 October 21, 2004 Yumoto
20040239595 December 2, 2004 Vulto
20040239596 December 2, 2004 Ono et al.
20040246019 December 9, 2004 Nakano et al.
20040252089 December 16, 2004 Ono et al.
20040257313 December 23, 2004 Kawashima et al.
20040257353 December 23, 2004 Imamura et al.
20040257355 December 23, 2004 Naugler
20040263437 December 30, 2004 Hattori
20040263444 December 30, 2004 Kimura
20040263445 December 30, 2004 Inukai et al.
20040263541 December 30, 2004 Takeuchi et al.
20050007355 January 13, 2005 Miura
20050007357 January 13, 2005 Yamashita et al.
20050017650 January 27, 2005 Fryer et al.
20050024081 February 3, 2005 Kuo et al.
20050024393 February 3, 2005 Kondo et al.
20050030267 February 10, 2005 Tanghe et al.
20050035709 February 17, 2005 Furuie et al.
20050057484 March 17, 2005 Diefenbaugh et al.
20050057580 March 17, 2005 Yamano et al.
20050067970 March 31, 2005 Libsch et al.
20050067971 March 31, 2005 Kane
20050068270 March 31, 2005 Awakura et al.
20050068275 March 31, 2005 Kane
20050073264 April 7, 2005 Matsumoto
20050083323 April 21, 2005 Suzuki et al.
20050088103 April 28, 2005 Kageyama et al.
20050093567 May 5, 2005 Nara et al.
20050110420 May 26, 2005 Arnold et al.
20050110720 May 26, 2005 Akimoto et al.
20050110807 May 26, 2005 Chang
20050117096 June 2, 2005 Voloschenko et al.
20050140598 June 30, 2005 Kim et al.
20050140610 June 30, 2005 Smith et al.
20050145891 July 7, 2005 Abe
20050156831 July 21, 2005 Yamazaki et al.
20050168416 August 4, 2005 Hashimoto et al.
20050179626 August 18, 2005 Yuki et al.
20050179628 August 18, 2005 Kimura
20050185200 August 25, 2005 Tobol
20050200575 September 15, 2005 Kim et al.
20050206590 September 22, 2005 Sasaki et al.
20050219184 October 6, 2005 Zehner et al.
20050225686 October 13, 2005 Brummack et al.
20050248515 November 10, 2005 Naugler et al.
20050260777 November 24, 2005 Brabec et al.
20050269959 December 8, 2005 Uchino et al.
20050269960 December 8, 2005 Ono et al.
20050280615 December 22, 2005 Cok et al.
20050280766 December 22, 2005 Johnson et al.
20050285822 December 29, 2005 Reddy et al.
20050285825 December 29, 2005 Eom et al.
20060001613 January 5, 2006 Routley et al.
20060007072 January 12, 2006 Choi et al.
20060012310 January 19, 2006 Chen et al.
20060012311 January 19, 2006 Ogawa
20060027807 February 9, 2006 Nathan et al.
20060030084 February 9, 2006 Young
20060038758 February 23, 2006 Routley et al.
20060038762 February 23, 2006 Chou
20060066527 March 30, 2006 Chou
20060066533 March 30, 2006 Sato et al.
20060077135 April 13, 2006 Cok et al.
20060082523 April 20, 2006 Guo et al.
20060092185 May 4, 2006 Jo et al.
20060097628 May 11, 2006 Suh et al.
20060097631 May 11, 2006 Lee
20060103611 May 18, 2006 Choi
20060149493 July 6, 2006 Sambandan et al.
20060170623 August 3, 2006 Naugler, Jr. et al.
20060176250 August 10, 2006 Nathan et al.
20060208961 September 21, 2006 Nathan et al.
20060232522 October 19, 2006 Roy et al.
20060244697 November 2, 2006 Lee et al.
20060261841 November 23, 2006 Fish
20060264143 November 23, 2006 Lee et al.
20060273997 December 7, 2006 Nathan et al.
20060284801 December 21, 2006 Yoon et al.
20060284895 December 21, 2006 Marcu et al.
20060290618 December 28, 2006 Goto
20070001937 January 4, 2007 Park et al.
20070001939 January 4, 2007 Hashimoto et al.
20070008268 January 11, 2007 Park et al.
20070008297 January 11, 2007 Bassetti
20070057873 March 15, 2007 Uchino et al.
20070069998 March 29, 2007 Naugler et al.
20070075727 April 5, 2007 Nakano et al.
20070076226 April 5, 2007 Klompenhouwer et al.
20070080905 April 12, 2007 Takahara
20070080906 April 12, 2007 Tanabe
20070080908 April 12, 2007 Nathan et al.
20070080918 April 12, 2007 Kawachi et al.
20070097038 May 3, 2007 Yamazaki et al.
20070097041 May 3, 2007 Park et al.
20070103419 May 10, 2007 Uchino et al.
20070115221 May 24, 2007 Buchhauser et al.
20070182671 August 9, 2007 Nathan et al.
20070236517 October 11, 2007 Kimpe
20070241999 October 18, 2007 Lin
20070273294 November 29, 2007 Nagayama
20070285359 December 13, 2007 Ono
20070290958 December 20, 2007 Cok
20070296672 December 27, 2007 Kim et al.
20080001525 January 3, 2008 Chao et al.
20080001544 January 3, 2008 Murakami et al.
20080036708 February 14, 2008 Shirasaki et al.
20080042942 February 21, 2008 Takahashi
20080042948 February 21, 2008 Yamashita et al.
20080048951 February 28, 2008 Naugler, Jr. et al.
20080055209 March 6, 2008 Cok
20080074413 March 27, 2008 Ogura
20080088549 April 17, 2008 Nathan et al.
20080088648 April 17, 2008 Nathan et al.
20080117144 May 22, 2008 Nakano et al.
20080150847 June 26, 2008 Kim et al.
20080158115 July 3, 2008 Cordes et al.
20080231558 September 25, 2008 Naugler
20080231562 September 25, 2008 Kwon
20080252571 October 16, 2008 Hente et al.
20080290805 November 27, 2008 Yamada et al.
20080297055 December 4, 2008 Miyake et al.
20090032807 February 5, 2009 Shinohara et al.
20090058772 March 5, 2009 Lee
20090160743 June 25, 2009 Tomida et al.
20090174628 July 9, 2009 Wang et al.
20090184901 July 23, 2009 Kwon
20090195483 August 6, 2009 Naugler, Jr. et al.
20090201281 August 13, 2009 Routley et al.
20090213046 August 27, 2009 Nam
20100004891 January 7, 2010 Ahlers et al.
20100039422 February 18, 2010 Seto
20100060911 March 11, 2010 Marcu et al.
20100079711 April 1, 2010 Tanaka
20100165002 July 1, 2010 Ahn
20100194670 August 5, 2010 Cok
20100207960 August 19, 2010 Kimpe et al.
20100277400 November 4, 2010 Jeong
20100315319 December 16, 2010 Cok et al.
20100328294 December 30, 2010 Sasaki et al.
20110069051 March 24, 2011 Nakamura et al.
20110069089 March 24, 2011 Kopf et al.
20110074750 March 31, 2011 Leon et al.
20110090210 April 21, 2011 Sasaki et al.
20110149166 June 23, 2011 Botzas et al.
20110227964 September 22, 2011 Chaji et al.
20110273399 November 10, 2011 Lee
20110293480 December 1, 2011 Mueller
20120056558 March 8, 2012 Toshiya et al.
20120056869 March 8, 2012 Cha et al.
20120062565 March 15, 2012 Fuchs et al.
20120299978 November 29, 2012 Chaji
20130027381 January 31, 2013 Nathan et al.
20130032831 February 7, 2013 Chaji et al.
20130057595 March 7, 2013 Nathan et al.
Foreign Patent Documents
1 294 034 January 1992 CA
2 109 951 November 1992 CA
2 249 592 July 1998 CA
2 368 386 September 1999 CA
2 242 720 January 2000 CA
2 354 018 June 2000 CA
2 432 530 July 2002 CA
2 436 451 August 2002 CA
2 438 577 August 2002 CA
2 483 645 December 2003 CA
2 463 653 January 2004 CA
2 498 136 March 2004 CA
2 522 396 November 2004 CA
2 443 206 March 2005 CA
2 472 671 December 2005 CA
2 567 076 January 2006 CA
2 526 782 April 2006 CA
2 541 531 July 2006 CA
2 550 102 April 2008 CA
2 773 699 October 2013 CA
1381032 November 2002 CN
1448908 October 2003 CN
1760945 April 2006 CN
102656621 September 2012 CN
20 2006 005427 June 2006 DE
0 158 366 October 1985 EP
0 940 796 September 1999 EP
1 028 471 August 2000 EP
1 103 947 May 2001 EP
1 111 577 June 2001 EP
1 130 565 September 2001 EP
1 184 833 March 2002 EP
1 194 013 March 2002 EP
1 194 013 April 2002 EP
1 310 939 May 2003 EP
1 335 430 August 2003 EP
1 372 136 December 2003 EP
1 381 019 January 2004 EP
1 418 566 May 2004 EP
1 429 312 June 2004 EP
1 439 520 July 2004 EP
145 0341 August 2004 EP
1 465 143 October 2004 EP
1 467 408 October 2004 EP
1 469 448 October 2004 EP
1 517 290 March 2005 EP
1 521 203 April 2005 EP
1 594 347 November 2005 EP
1 784 055 May 2007 EP
1854338 November 2007 EP
1 879 169 January 2008 EP
1 879 172 January 2008 EP
2 205 431 December 1988 GB
2 389 951 December 2003 GB
1272298 October 1989 JP
4-042619 February 1992 JP
6-314977 November 1994 JP
8-340243 December 1996 JP
09 090405 April 1997 JP
10-153759 June 1998 JP
10-254410 September 1998 JP
11-202295 July 1999 JP
11-219146 August 1999 JP
11 231805 August 1999 JP
11-282419 October 1999 JP
2000-056847 February 2000 JP
2000-077192 March 2000 JP
2000-81607 March 2000 JP
2000-089198 March 2000 JP
2000-352941 December 2000 JP
2001-134217 May 2001 JP
2001-195014 July 2001 JP
2002-055654 February 2002 JP
2002-91376 March 2002 JP
2002-514320 May 2002 JP
2002-268576 September 2002 JP
2002-278513 September 2002 JP
2002-333862 November 2002 JP
2003-022035 January 2003 JP
2003-076331 March 2003 JP
2003-124519 April 2003 JP
2003-150082 May 2003 JP
2003-177709 June 2003 JP
2003177709 June 2003 JP
2003-271095 September 2003 JP
2003-308046 October 2003 JP
2003-317944 November 2003 JP
2004-004675 January 2004 JP
2004-145197 May 2004 JP
2004-287345 October 2004 JP
2005-057217 March 2005 JP
2007-65015 March 2007 JP
2008102335 May 2008 JP
4-158570 October 2008 JP
2004-0100887 December 2004 KR
342486 October 1998 TW
473622 January 2002 TW
485337 May 2002 TW
502233 September 2002 TW
538650 June 2003 TW
569173 January 2004 TW
1221268 September 2004 TW
200727247 July 2007 TW
WO 1994-25954 November 1994 WO
WO 1998-48403 October 1998 WO
WO 1999-48079 September 1999 WO
WO 2001-06484 January 2001 WO
WO 2001-27910 April 2001 WO
WO 2001-63587 August 2001 WO
03/063124 March 2002 WO
WO 2002-067327 August 2002 WO
WO 2003-001496 January 2003 WO
03/034389 April 2003 WO
WO 2003-034389 April 2003 WO
WO 2003-058594 July 2003 WO
WO 2003-063124 July 2003 WO
WO 2003-077231 September 2003 WO
WO 2003-105117 December 2003 WO
WO 2004-003877 January 2004 WO
WO 2004-025615 March 2004 WO
WO 2004-034364 April 2004 WO
WO 2004-047058 June 2004 WO
WO 2004-104975 December 2004 WO
WO 2005-022498 March 2005 WO
WO 2005-022500 March 2005 WO
WO 2005-029455 March 2005 WO
WO 2005-029456 March 2005 WO
WO 2005-055185 June 2005 WO
WO 2006-000101 January 2006 WO
WO 2006-053424 May 2006 WO
2006/063448 June 2006 WO
WO 2006-063448 June 2006 WO
WO 2006-084360 August 2006 WO
WO 2006-137337 December 2006 WO
WO 2007-003877 January 2007 WO
WO 2007-079572 July 2007 WO
WO 2007-120849 October 2007 WO
WO 2009-048618 April 2009 WO
WO 2009-055920 May 2009 WO
WO 2010-023270 March 2010 WO
WO 2011-041224 April 2011 WO
WO 2011-046761 June 2011 WO
WO 2011-067729 June 2011 WO
WO 2012-160424 November 2012 WO
WO 2012-160471 November 2012 WO
WO 2012-164474 December 2012 WO
WO 2012-164475 December 2012 WO
Other references
  • Ahnood et al.: “Effect of threshold voltage instability on field effect mobility in thin film transistors deduced from constant current measurements”; dated Aug. 2009 (3 pages).
  • Alexander et al.: “Unique Electrical Measurement Technology for Compensation, Inspection, and Process Diagnostics of AMOLED HDTV”; dated May 2010 (4 pages).
  • Chaji et al.: “A Current-Mode Comparator for Digital Calibration of Amorphous Silicon AMOLED Displays”; dated Jul. 2008 (5 pages).
  • Chaji et al.: “A fast settling current driver based on the CCII for AMOLED displays”; dated Dec. 2009 (6 pages).
  • Chaji et al.: “A low-power high-performance digital circuit for deep submicron technologies”; dated Jun. 2005 (4 pages).
  • Chaji et al.: “A novel a-Si:H AMOLED pixel circuit based on short-term stress stability of a-Si:H TFTs”; dated Oct. 2005 (3 pages).
  • Chaji et al.: “An Enhanced and Simplified Optical Feedback Pixel Circuit for AMOLED Displays”; dated Oct. 2006.
  • Chaji et al.: “Compensation technique for DC and transient instability of thin film transistor circuits for large-area devices”; dated Aug. 2008.
  • Chaji et al.: “eUTDSP: a design study of a new VLIW-based DSP architecture”; dated My 2003 (4 pages).
  • Chaji et al.: “Fast and Offset-Leakage Insensitive Current-Mode Line Driver for Active Matrix Displays and Sensors”; dated Feb. 2009 (8 pages).
  • Chaji et al.: “Low-Cost AMOLED Television with Ignis Compensating Technology”; dated May 2008 (4 pages).
  • Chaji et al.: “Low-Power Low-Cost Voltage-Programmed a-Si:H AMOLED Display”; dated Jun. 2008 (5 pages).
  • Chaji et al.: “Merged phototransistor pixel with enhanced near infrared response and flicker noise reduction for biomolecular imaging”; dated Nov. 2008 (3 pages).
  • Chaji et al.: “Stable Pixel Circuit for Small-Area High-Resolution a-Si:H AMOLED Displays”; dated Oct. 2008 (6 pages).
  • Chaji et al.: “Stable RGBW AMOLED display with OLED degradation compensation using electrical feedback”; dated Feb. 2010 (2 pages).
  • European Search Report and Written Opinion for Application No. 08 86 5338 dated Nov. 2, 2011 (7 pages).
  • European Search Report for Application No. 10 00 0421, dated Mar. 26, 2012 (6 pages).
  • European Search Report for Application No. EP 01 11 22313 dated Sep. 14, 2005 (4 pages).
  • European Search Report for Application No. EP 04 78 6661, dated Mar. 9, 2009.
  • European Search Report for Application No. EP 05 75 9141, dated Oct. 30, 2009.
  • European Search Report for Application No. EP 05 81 9617 dated Jan. 30, 2009.
  • European Search Report for Application No. EP 05 82 1114, dated Mar. 27, 2009 (2 pages).
  • European Search Report for Application No. EP 06 70 5133 dated Jul. 18, 2008.
  • European Search Report for Application No. EP 06 72 1798 dated Nov. 12, 2009 (2 pages).
  • European Search Report for Application No. EP 07 71 0608 dated Mar. 19, 2010 (7 pages).
  • European Search Report for Application No. EP 07 71 9579 dated May 20, 2009.
  • European Search Report for Application No. EP 07 81 5784 dated Jul. 20, 2010 (2 pages).
  • European Search Report for Application No. EP 10 16 6143, dated Sep. 3, 2010 (2 pages).
  • European Search Report for Application No. EP 10 83 4294.0-1903, dated Apr. 8, 2013, (9 pages).
  • European Search Report for Application No. PCT/CA2006/000177 dated Jun. 2, 2006.
  • European Supplementary Search Report for Application No. EP 04 78 6662 dated Jan. 19, 2007 (2 pages).
  • Extended European Search Report for Application No. 11 73 9485.8 dated Aug. 6, 2013(14 pages).
  • Extended European Search Report for Application No. EP 09 73 3076.5, dated Apr. 27, 2011 (13 pages).
  • Extended European Search Report for Application No. EP 11 16 8677.0, dated Nov. 29, 2012, (13 page).
  • Extended European Search Report for Application No. EP 11 19 1641.7 dated Jul. 11, 2012 (14 pages).
  • Extended European Search Report for Application No. EP 14 15 8051.4, dated Jul. 29, 2014, (4 pages).
  • Fossum, Eric R.. “Active Pixel Sensors: Are CCD's Dinosaurs?” SPIE: Symposium on Electronic Imaging. Feb. 1, 1993 (13 pages).
  • Goh et al., “A New a-Si:H Thin-Film Transistor Pixel Circuit for Active-Matrix Organic Light-Emitting Diodes”, IEEE Electron Device Letters, vol. 24, No. 9, Sep. 2003, pp. 583-585.
  • International Search Report for Application No. PCT/IB2014/060879, Canadian Intellectual Property Office, dated Jul. 17, 2014 (3 pages).
  • International Preliminary Report on Patentability for Application No. PCT/CA2005/001007 dated Oct. 16, 2006, 4 pages.
  • International Search Report for Application No. PCT/CA02/00180 dated Jul. 31, 2002 (3 pages).
  • International Search Report for Application No. PCT/CA2004/001741 dated Feb. 21, 2005.
  • International Search Report for Application No. PCT/CA2004/001742, Canadian Patent Office, dated Feb. 21, 2005 (2 pages).
  • International Search Report for Application No. PCT/CA2005/001007 dated Oct. 18, 2005.
  • International Search Report for Application No. PCT/CA2005/001844 dated Mar. 28, 2006 (2 pages).
  • International Search Report for Application No. PCT/CA2005/001897, dated Mar. 21, 2006 (2 pages).
  • International Search Report for Application No. PCT/CA2007/000652 dated Jul. 25, 2007.
  • International Search Report for Application No. PCT/CA2008/002307, dated Apr. 28. 2009 (3 pages).
  • International Search Report for Application No. PCT/CA2009/000501, dated Jul. 30, 2009 (4 pages).
  • International Search Report for Application No. PCT/CA2009/001769, dated Apr. 8, 2010 (3 pages).
  • International Search Report for Application No. PCT/IB2010/055481, dated Apr. 7, 2011, 3 pages.
  • International Search Report for Application No. PCT/IB2010/055486, dated Apr. 19, 2011, 5 pages.
  • International Search Report for Application No. PCT/IB2010/055541 filed Dec. 1, 2010, dated May 26, 2011; 5 pages.
  • International Search Report for Application No. PCT/IB2011/050502, dated Jun. 27, 2011 (6 pages).
  • International Search Report for Application No. PCT/IB2011/051103, dated Jul. 8, 2011, 3 pages.
  • International Search Report for Application No. PCT/IB2011/055135, Canadian Patent Office, dated Apr. 16, 2012 (5 pages).
  • International Search Report for Application No. PCT/IB2012/052372, dated Sep. 12, 2012 (3 pages).
  • International Search Report for Application No. PCT/IB2013/054251, Canadian Intellectual Property Office, dated Sep. 11, 2013; (4 pages).
  • International Search Report for Application No. PCT/IB2014/058244, Canadian Intellectual Property Office, dated Apr. 11, 2014; (6 pages).
  • International Search Report for Application No. PCT/IB2014/059409, Canadian Intellectual Property Office, dated Jun. 12, 2014 (4 pages).
  • International Search Report for Application No. PCT/IB2014/059753, Canadian Intellectual Property Office, dated Jun. 23, 2014; (6 pages).
  • International Search Report for Application No. PCT/JP02/09668, dated Dec. 3, 2002, (4 pages).
  • International Written Opinion for Application No. PCT/CA2004/001742, Canadian Patent Office, dated Feb. 21, 2005 (5 pages).
  • International Written Opinion for Application No. PCT/CA2005/001897, dated Mar. 21, 2006 (4 pages).
  • International Written Opinion for Application No. PCT/CA2009/000501 dated Jul. 30, 2009 (6 pages).
  • International Written Opinion for Application No. PCT/IB2010/055481, dated Apr. 7, 2011, 6 pages.
  • International Written Opinion for Application No. PCT/IB2010/055486, dated Apr. 19, 2011, 8 pages.
  • International Written Opinion for Application No. PCT/IB2010/055541, dated May 26, 2011; 6 pages.
  • International Written Opinion for Application No. PCT/IB2011/050502, dated Jun. 27, 2011 (7 pages).
  • International Written Opinion for Application No. PCT/IB2011/051103, dated Jul. 8, 2011, 6 pages.
  • International Written Opinion for Application No. PCT/IB2011/055135, Canadian Patent Office, dated Apr. 16, 2012 (5 pages).
  • International Written Opinion for Application No. PCT/IB2012/052372, dated Sep. 12, 2012 (6 pages).
  • International Written Opinion for Application No. PCT/IB2013/054251, Canadian Intellectual Property Office, dated Sep. 11, 2013; (5 pages).
  • International Written Opinion for Application No. PCT/IB2014/059409, Canadian Intellectual Property Office, dated Jun. 12, 2014 (5 pages).
  • International Written Opinion for Application No. PCT/IB2014/059753, Canadian Intellectual Property Office, dated Jun. 12, 2014 (6 pages).
  • International Written Opinion for Application No. PCT/IB2014/060879, Canadian Intellectual Property Office, dated Jul. 17, 2014; (4 pages).
  • Jafarabadiashtiani et al.: “A New Driving Method for a-Si AMOLED Displays Based on Voltage Feedback”; dated 2005 (4 pages).
  • Kanicki, J., et al. “Amorphous Silicon Thin-Film Transistors Based Active-Matrix Organic Light-Emitting Displays.” Asia Display: International Display Workshops, Sep. 2001 (pp. 315-318).
  • Karim, K. S., et al. “Amorphous Silicon Active Pixel Sensor Readout Circuit for Digital Imaging.” IEEE: Transactions on Electron Devices. vol. 50, No. 1, Jan. 2003 (pp. 200-208).
  • Ma e y et al: “Organic Light-Emitting Diode/Thin Film Transistor Integration for foldable Displays” Conference record of the 1997 International display research conference and international workshops on LCD technology and emissive technology. Toronto, Sep. 15-19, 1997 (6 pages).
  • Machine English translation of JP 2002-333862, 49 pages.
  • Matsueda y et al.: “35.1: 2.5-in. AMOLED with Integrated 6-bit Gamma Compensated Digital Data Driver”; dated May 2004.
  • Mendes E., et al. “A High Resolution Switch-Current Memory Base Cell.” IEEE: Circuits and Systems. vol. 2, Aug. 1999 (pp. 718-721).
  • Nathan et al., “Amorphous Silicon Thin Film Transistor Circuit Integration for Organic LED Displays on Glass and Plastic”, IEEE Journal of Solid-State Circuits, vol. 39, No. 9, Sep. 2004, pp. 1477-1486.
  • Nathan et al.: “Call for papers second international workshop on compact thin-film transistor (TFT) modeling for circuit simulation”; dated Sep. 2009 (1 page).
  • Nathan et al.: “Thin film imaging technology on glass and plastic” ICM 2000, Proceedings of the 12th International Conference on Microelectronics, (IEEE Cat. No. 00EX453), Tehran Iran; dated Oct. 31-Nov. 2, 2000, pp. 11-14, ISBN: 964-360-057-2, p. 13, col. 1, line 11-48; (4 pages).
  • Office Action in Japanese patent application No. JP2006-527247 dated Mar. 15, 2010. (8 pages).
  • Office Action in Japanese patent application No. JP2007-545796 dated Sep. 5, 2011. (8 pages).
  • Office Action in Japanese patent application No. JP2012-541612 dated Jul. 15, 2014. (3 pages).
  • Office Action issued in Chinese Patent Application 200910246264.4 dated Jul. 5, 2013; 8 pages.
  • Partial European Search Report for Application No. EP 11 168 677.0, dated Sep. 22, 2011 (5 pages).
  • Partial European Search Report for Application No. EP 11 19 1641.7, dated Mar. 20, 2012 (8 pages).
  • Patent Abstracts of Japan, vol. 1997, No. 08, Aug. 29, 1997, & JP 09 090405 A, Apr. 4, 1997 Abstract.
  • Patent Abstracts of Japan, vol. 1999, No. 13, Nov. 30, 1999, & JP 11 231805 A, Aug. 27, 1999 Abstract.
  • Patent Abstracts of Japan, vol. 2000, No. 09, Oct. 13, 2000—JP 2000 172199 A, Jun. 3, 2000, abstract.
  • Patent Abstracts of Japan, vol. 2002, No. 03, Apr. 3, 2002 (Apr. 4, 2004 & JP 2001 318627 A (Semiconductor EnergyLab Do Ltd), Nov. 16, 2001, abstract, paragraphs '01331-01801, paragraph '01691, paragraph '01701, paragraph '01721 and figure 10.
  • Philipp: “Charge transfer sensing” Sensor Review, vol. 19, No. 2, Dec. 31, 1999 (1999-1231), 10 pages.
  • Safavian et al.: “3-TFT active pixel sensor with correlated double sampling readout circuit for real-time medical x-ray imaging”; dated Jun. 2006 (4 pages).
  • Safavian et al.: “A novel current scaling active pixel sensor with correlated double sampling readout circuit for real time medical x-ray imaging”; dated May 2007 (7 pages).
  • Safavian et al.: “A novel hybrid active-passive pixel with correlated double sampling CMOS readout circuit for medical x-ray imaging”; dated May 2008 (4 pages).
  • Safavian et al.: “Self-compensated a-Si:H detector with current-mode readout circuit for digital X-ray fluoroscopy”; dated Aug. 2005 (4 pages).
  • Safavian et al.: “TFT active image sensor with current-mode readout circuit for digital x-ray fluoroscopy [5969D-82]”; dated Sep. 2005 (9 pages).
  • Safavian et al.: “Three-TFT image sensor for real-time digital X-ray imaging”; dated Feb. 2, 2006 (2 pages).
  • Sanford, James L., et al., “4.2 TFT AMOLED Pixel Circuits and Driving Methods”, SID 03 Digest, ISSN/0003, 2003, pp. 10-13.
  • Search Report for Taiwan Invention Patent Application No. 093128894 dated May 1, 2012. (1 page).
  • Search Report for Taiwan Invention Patent Application No. 94144535 dated Nov. 1, 2012. (1 page).
  • Singh, et al., “Current Conveyor: Novel Universal Active Block”, Samriddhi, S-JPSET vol. I, Issue 1, 2010, pp. 41-48.
  • Smith, Lindsay I., “A tutorial on Principal Components Analysis,” dated Feb. 26, 2001 (27 pages).
  • Spindler et al., System Considerations for RGBW OLED Displays, Journal of the SID 14/1, 2006, pp. 37-48.
  • Stewart M. et al., “polysilicon TFT technology for active matrix oled displays” IEEE transactions on electron devices, vol. 48, No. 5, dated May 2001 (7 pages).
  • Tatsuya Sasaoka et al., 24.4L; Late-News Paper: A 13.0-inch AM-Oled Display with Top Emitting Structure and Adaptive Current Mode Programmed Pixel Circuit (TAC)', SID 01 Digest, (2001), pp. 384-387.
  • Vygranenko et al.: “Stability of indium-oxide thin-film transistors by reactive ion beam assisted deposition”; dated 2009.
  • Wang et al.: “Indium oxides by reactive ion beam assisted evaporation: From material study to device application”; dated Mar. 2009 (6 pages).
  • Yi He et al., “Current-Source a-Si:H Thin Film Transistor Circuit for Active-Matrix Organic Light-Emitting Displays”, IEEE Electron Device Letters, vol. 21, No. 12, Dec. 2000, pp. 590-592.
  • Yu, Jennifer: “Improve OLED Technology for Display”, Ph.D. Dissertation, Massachusetts Institute of Technology, Sep. 2008 (151 pages).
  • Zhiguo Meng et al; “24.3: Active-Matrix Organic Light-Emitting Diode Display implemented Using Metal-Induced Unilaterally Crystallized Polycrystalline Silicon Thin-Film Transistors”, SID 01Digest, (2001), pp. 380-383.
  • Alexander et al.: “Pixel circuits and drive schemes for glass and elastic AMOLED displays”; dated Jul. 2005 (9 pages).
  • Ashtiani et al.: “AMOLED Pixel Circuit With Electronic Compensation of Luminance Degradation”; dated Mar. 2007 (4 pages).
  • Chaji et al.: “A Low-Cost Stable Amorphous Silicon AMOLED Display with Full V?T- and V˜O˜L˜E˜D Shift Compensation”; dated May 2007 (4 pages).
  • Chaji et al.: “A low-power driving scheme for a-Si:H active-matrix organic light-emitting diode displays”; dated Jun. 2005 (4 pages).
  • Chaji et al.: “A Novel Driving Scheme and Pixel Circuit for AMOLED Displays”; dated Jun. 2006 (4 pages).
  • Chaji et al.: “A novel driving scheme for high-resolution large-area a-Si:H AMOLED displays”; dated Aug. 2005 (4 pages).
  • Chaji et al.: “A Stable Voltage-Programmed Pixel Circuit for a-Si:H AMOLED Displays”; dated Dec. 2006 (12 pages).
  • Chaji et al.: “A Sub-μA fast-settling current-programmed pixel circuit for AMOLED displays”; dated Sep. 2007.
  • Chaji et al.: “Driving; scheme for stable operation of 2-TFT a-Si AMOLED pixel”; dated Apr. 2005 (2 pages).
  • Chaji et al.: “Dynamic-effect compensating technique for stable a-Si:H AMOLED displays”; dated Aug. 2005 (4 pages).
  • Chaji et al.: “Electrical Compensation of OLED Luminance Degradation”; dated Dec. 2007 (3 pages).
  • Chaji et al.: “High Speed Low Power Adder Design With A New Logic Style: Pseudo Dynamic Logic (SDL)”; dated Oct. 2001 (4 pages).
  • Chaji et al.: “High-precision, fast current source for large-area current-programmed a-Si flat panels”; dated Sep. 2006 (4 pages).
  • Chaji et al.: “Low-Cost Stable a-Si:H AMOLED Display for Portable Applications”; dated Jun. 2006 (4 pages).
  • Chaji et al.: “Parallel Addressing Scheme for Voltage-Programmed Active-Matrix OLED Displays”; dated May 2007 (6 pages).
  • Chaji et al.: “Pseudo dynamic logic (SDL): a high-speed and low-power dynamic logic family”; dated 2002 (4 pages).
  • Chaji et al.: “Stable a-Si:H circuits based on short-term stress stability of amorphous silicon thin film transistors”; dated May 2006 (4 pages).
  • Chaji et al.: “Stable Pixel Circuit for Small-Area High-Resolution a-Si:H AMOLED Displays”; dated 2008 (7 pages).
  • Chaji et al.: “Thin-Film Transistor Integration for Biomedical Imaging and AMOLED Displays”; dated 2008 (177 pages).
  • International Search Report for International Application No. PCT/CA2005/001007 dated Oct. 18, 2005.
  • Jafarabadiashtiani et al.: “A New Driving Method for a-Si AMOLED Displays Based on Voltage Feedback”; May 27, 2005 (4 pages).
  • Lee et al.: “Ambipolar Thin-Film Transistors Fabricated by PECVD Nanocrystalline Silicon”; dated 2006 (6 pages).
  • Nathan et al.: “Backplane Requirements for Active Matrix Organic Light Emitting Diode Displays”; dated 2006 (16 pages).
  • Nathan et al.: “Driving schemes for a-Si and LTPS AMOLED displays”; dated Dec. 2005 (11 pages).
  • Nathan et al.: “Invited Paper: a-Si for AMOLED—Meeting the Performance and Cost Demands of Display Applications (Cell Phone to HDTV)”; dated 2006 (4 pages).
  • Rafati et al.: “Comparison of a 17 b multiplier in Dual-rail domino and in Dual-rail D L (D L) logic styles”; dated 2002 (4 pages).
  • International Preliminary Report on Patentability for International Application No. PCT/CA2005/001007 dated Oct. 16, 2006, 4 pages.
Patent History
Patent number: RE47257
Type: Grant
Filed: Jul 9, 2014
Date of Patent: Feb 26, 2019
Assignee: Ignis Innovation Inc. (Waterloo, Ontario)
Inventors: Arokia Nathan (Cambridge), Richard I-Heng Huang (Waterloo), Stefan Alexander (Elmira)
Primary Examiner: Adam L Basehoar
Application Number: 14/326,705
Classifications
Current U.S. Class: Thin Film Tansistor (tft) (345/92)
International Classification: G09G 3/30 (20060101); G09G 3/3233 (20160101); G09G 3/3283 (20160101); G09G 3/3291 (20160101); G09G 3/3241 (20160101);