Abstract: A display device is provided. The display device includes a first display panel and a second display panel stacked in a first direction. The first display panel includes a first substrate, and light-emitting units on a side of the first substrate away from the second display panel. The light-emitting units include first light-emitting units and second light-emitting units. One first light-emitting unit includes a first light-emitting layer, and a distance between the first light-emitting layer and the first substrate in the first direction is D1. One second light-emitting unit includes a second light-emitting layer, and a distance between the second light-emitting layer and the first substrate in the first direction is D2, where D1>D2. The second display panel includes a reflective surface on a side of the first substrate away from the light-emitting units.

Abstract: An image sensor is provided. The image sensor may include a substrate including first and second surfaces opposite to each other, a device isolation layer extending through the substrate and having a surface level with the second surface of the substrate, an active region comprising first and second pixel regions spaced apart and separated from each other by the device isolation layer, a photoelectric device located in the substrate and configured to convert light into electric charges, a microlens on the first surface, a first select transistor and a first source follower transistor in the first pixel region, a second source follower transistor in the second pixel region, a first node between the first select transistor and the first source follower transistor, on the first pixel region, and a second node on one side of the first select transistor on the first pixel region.

Abstract: A circuit stage including a first transistor including a first electrode and a gate electrode, the first electrode being coupled to a first input terminal and the gate electrode being coupled to a second input terminal configured to receive a first clock signal, an output circuit coupled to the second input terminal and a second power input terminal, an input circuit coupled to a second electrode of the first transistor and to a third input terminal, the third input terminal being configured to receive a first control clock signal, the input circuit being configured to control voltages of the second node and a third node, a first driving circuit coupled to a first power input terminal and to a fourth input terminal configured to receive a second control clock signal, and a second driving circuit coupled to the fourth input terminal and the third node.

Abstract: Disclosed are a display substrate and a display device. The display substrate includes a pixel circuit and a scan drive circuit, wherein the pixel circuit includes a write transistor and a scan signal line, the scan signal line is electrically connected with a control electrode of the write transistor, and the scan drive circuit includes a first scan clock signal line and a second scan clock signal line. A signal of the first scan clock signal line is a first clock signal, a signal of the second scan clock signal line is a second clock signal, and both of the first clock signal and the second clock signal are periodic clock signals. A duration of the first clock signal being a low-level signal in one period is different from a duration of the second clock signal being a low-level signal in one period.

Abstract: A method and a device for detecting the position of an object are disclosed. According to an embodiment of the present disclosure, the method for detecting the position of an object includes: detecting a position of the object in a sensing zone, which is divided into multiple divided sensing zones along one direction, by causing multiple light-emitting elements disposed along the one direction to emit light sequentially along the one direction and measuring an intensity and a reception time point of a reflected signal by using a light-receiving element; and reflecting and displaying the detected position of the object on a display screen.

Abstract: A liquid crystal display device includes a substrate, first through third thin-film transistors (“TFTs”) disposed on the substrate, and first and second sub-pixel electrodes disposed above the first through third TFTs. The second and third TFTs share a single output terminal as their output terminals, the first sub-pixel electrode is electrically connected to an output terminal of the first TFT, and the second sub-pixel electrode is electrically connected to the single output terminal of the second and third TFTs.

Abstract: A pixel circuitry, a pixel driving method and a display device are provided. The pixel circuitry includes a first light-emission control circuitry, a driving circuitry, a second light-emission control circuitry, a resetting control circuitry and a light-emitting element. The resetting control circuitry is electrically connected to a resetting control line, a connection node and a first initial voltage end for providing a first initial voltage, and configured to apply the first initial voltage to the connection node under the control of a resetting control signal from the resetting control line. The connection node is a first node, a third node or a fourth node. According to the present disclosure, it is able to suppress the occurrence of flicker.

Abstract: Disclosed in embodiments of the present application are a pixel driving circuit, a pixel driving method, and a display panel, comprising a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, a first capacitor, a second capacitor, and a light-emitting device. The first thin film transistor is used as a driving thin film transistor of the light-emitting device. A threshold voltage of a driving thin film transistor in each pixel may be compensated.

Abstract: The present disclosure discloses a driving circuit and a display device. The driving circuit of the present disclosure inputs a level signal to a first node under the control of a first signal control terminal and a second signal control terminal, and then outputs a signal of a first power supply terminal or a second power supply terminal to the output terminal under the control of the level signal of the first node, so as to output different level signals under the control of two the control signals, thereby resolving a problem that one timing controller cannot be directly matched with different gate driving chips in use.

Abstract: An electronic device includes a display panel, a gate driving circuit and a control unit. The display panel includes a display scan line and a dummy scan line. The gate driving circuit includes a first output unit for providing a display scan signal to the display scan line, and a second output unit for providing a test scan signal to the dummy scan line. The control unit is electrically connected to the gate driving circuit for receiving the test scan signal, updating a driving voltage according to the test scan signal, and driving the gate driving circuit according to the updated driving voltage.

Abstract: A display device, includes: a display area including an upper side, a lower side, a left side, a right side, and inclined corner portions where the upper, lower, left, and right sides meet; a demultiplexing circuit unit adjacent to the lower side of the display area and the corner portion connected thereto; and a scan transmission line which extends toward the display area from an outer side of the left side and overlaps with the demultiplexing circuit unit outside the corner portion, wherein the demultiplexing circuit unit includes a demultiplexer transistor, and the scan transmission line is formed of a different conductive layer from an electrode of a demultiplexer transistor.

Abstract: Embodiments of the present disclosure are related to a touch display device, as implementing a portion of a touch link line by using a metal disposed on a layer different from a layer where a data link line is disposed and disposing a color filter layer between the touch link line and the data link line, a plurality of link lines can be disposed effectively and a parasitic capacitance between the touch link line and the data link line can be reduced. Furthermore, as blocking a light of specific wavelength band by the color filter layer, a light-leakage due to an abnormal driving of a display according to a driving of the touch link line on an area where the touch link line is disposed can be prevented or at least reduced.

Abstract: A pixel includes: a light emitting element; a first transistor including a gate electrode electrically connected to a first node, a second node to which a first power voltage for driving the light emitting element is to be applied, and a third node electrically connected to the light emitting element; and a bias control transistor configured to be controlled in operating timing thereof by a bias control signal, and configured to switch electrical connection between the second node and a bias power line for transmitting a bias voltage. In one frame period, a voltage level of the bias voltage to be applied to the second node sequentially increases.

Abstract: An array substrate and display device are provided. The array substrate includes a base substrate, and gate lines, data lines, compensation blocks and sub-pixels located on the base substrate. Two gate lines are arranged between two adjacent rows of sub-pixels. The data lines are provided with multiple first extensions and second extensions arranged alternately. The extending direction of the first extensions intersects with the extending direction of the second extensions.

Abstract: A display device includes a display panel and an input sensor on the display panel, the input sensor including sensing electrodes, signal lines connected to the sensing electrodes, an insulating layer on the signal lines, and inspection lines on the insulating layer and electrically connected to each other, each of the inspection lines respectively overlapping a corresponding one of the signal lines.

Abstract: Disclosed is a clock generator including an oscillator configured to output a reference clock signal to a first line, an EMI reduction controller configured to generate an EMI reduction signal offset with the reference clock signal and to output the EMI reduction signal to a second line, and a driving clock generator configured to generate an operation clock based on the reference clock signal, which is one of the reference clock signal input through the first line and the EMI reduction signal input through the second line.

Abstract: A method for driving a pixel matrix is provided, and the pixel matrix includes multiple sub-pixels arranged in a matrix. Voltages applied along any one of data lines change in polarity once every four sub-pixels or every two sub-pixels, any one of the data lines controls voltage inputs of sub-pixel respectively connected to two sides thereof or controls voltage inputs of two sub-pixels both connected to one side thereof. The method includes: receiving an image data and acquiring original pixel data according to the image data; generating a first driving voltage and a second driving voltage according to the original pixel data; and loading the first driving voltage or the second driving voltage to the pixel matrix along any one of the data lines. The invention also provides a display device corresponding to the method. The invention can avoid crosstalk, bright dark lines and improve display effect.

Abstract: A display panel including: a plurality of pixels arranged in a longitudinal direction and a lateral direction; a plurality of pixel electrodes; a common electrode; a first, second, third, and fourth gate lines extending in the lateral direction; and a first and second data lines, and a common line extending in the longitudinal direction, in which the plurality of pixels include a first pixel having a first pixel electrode and a second pixel adjacent to the first pixel in the lateral direction and having a second pixel electrode, the third gate line is arranged to overlap the first and the second pixel electrodes, the common line is arranged between the first and the second pixel electrodes, and the display panel further includes a first switching element connected to the first pixel electrode, the common line, and the third gate line, and a second switching element connected to the second pixel electrode, the common line, and the third gate line.

Abstract: A display apparatus includes a plurality of pixels. A pixel includes a first capacitor connected between a first voltage line receiving a first driving signal and a first node, a first transistor comprising a control electrode connected to the first node, a first electrode connected to a second voltage line receiving a first power source signal and a second electrode connected to a second node, an organic light emitting diode comprising an anode electrode connected to the second node and a cathode electrode receiving a second power source signal, a second capacitor connected between an m-th data line and the second node (wherein, ‘m’ is a natural number) and a second transistor comprising a control electrode connected to an n-th scan line (wherein, ‘n’ is a natural number), a first electrode connected to the first node and a second electrode connected to the second node.

Abstract: A driving circuit, a driving method and a display device are disclosed. The driving circuit includes a memory, a timing controller and a power chip. The memory is connected to each of the timing controller and the power chip. The power chip includes a first analyzing module and a working module. The working module includes a fault output terminal. The timing controller includes a second analyzing module and a reset terminal. During a power-on phase, the timing controller reads and analyzes the driving data located in the memory through the second analyzing module, and transmits the analyzed driving data to the first analyzing module of the power chip for use by the power chip. During a fault phase, the fault output terminal outputs a fault signal, and the reset terminal receives the fault signal to control the timing controller and the power chip to reset in tandem.

Abstract: Disclosed are a driving substrate, a display panel, and a display device. The driving substrate is applied to a display panel and includes a base; data lines and row scanning lines, arranged on a side of the base; and a scanning driving circuit, arranged on the side of the base and including a plurality of scanning driving units that are cascaded. Each row scanning line includes at least two sub-scanning lines, and the scanning driving circuit is configured to output a gate scanning signal to each sub-scanning line. The present disclosure may save power by dividing each row scanning line into multiple sub-scanning lines and separately outputting the gate scanning signal for each sub-scanning line, making it possible to drive only part of the thin-film transistor in each row when only part of the display region of the display panel is used for displaying images.

Abstract: A display panel and a mobile terminal are provided. The display panel includes a base and a thin film transistor (TFT) layer that is disposed on the base and includes at least two TFTs arranged in parallel. According to the present disclosure, the TFT layer includes at least two TFTs arranged in parallel, thereby resolving the problem that a short circuit between a gate and a source and/or a short circuit between the gate and a drain in the TFT cannot be repaired.

Abstract: A backlight regulating circuit includes a first dimming circuit, a second dimming circuit and a selecting circuit, where the first dimming circuit is configured to conduct a PWM signal line and a driving chip in response to a signal of the scanning signal line; the second dimming circuit is configured to conduct a DC signal line and the driving chip in response to the signal of the scanning signal line; the first dimming circuit and the second dimming circuit are connected to the scanning signal line through the selecting circuit; and the selecting circuit is configured to proportionally distribute the signal of the scanning signal line to the first dimming circuit and the second dimming circuit in response to a control signal dynamically output by a control signal line according to an image.

Abstract: A display device, a manufacturing method thereof and a driving substrate are provided. The display device includes: a base substrate, an active area and an edge area; the active area includes a plurality of sub-pixels on the base substrate; each sub-pixel includes: a first reflecting electrode, a light-emitting element a second electrode layer, an insulating layer, a pixel circuit, and a storing capacitor. The edge area includes a plurality of second reflecting electrodes and a light shielding layer.

Abstract: An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a substrate and an active pattern formed over the substrate and including first to fourth regions. A gate insulation layer is formed over the active pattern and the substrate, and a first gate electrode is formed over the gate insulation layer and partially overlapping the active pattern. The first gate electrode, the first region and the second region define a first transistor. A second gate electrode is formed on the same layer as the first gate electrode. The second gate electrode, the third region and the fourth region define a second transistor, and the second gate electrode, the second region and the fourth region define a third transistor. A first insulating interlayer is formed over the first gate electrode, the second gate electrode, and the gate insulation layer.

Abstract: A display panel and a display device are provided. The display panel includes a plurality of data lines, a plurality of first scan line; and a plurality of sub-pixels, wherein each of the sub-pixels includes a pixel driving circuit and a pixel electrode electrically connected to the pixel driving circuit, the pixel driving circuit is electrically connected to a corresponding one of the data lines and a corresponding one of the first scan lines. The display panel further includes a plurality of plates. At least one of the plates is disposed between the corresponding data line electrically connected to the pixel driving circuit and an adjacent data line, and is electrically connected to the adjacent data line. The at least one of the plates and the pixel electrode define a first capacitance.

Abstract: A display device includes a display panel including a pixel array including a plurality of pixels and a plurality of sub-pixel circuits, each pixel of the plurality of pixels including a plurality of inorganic light emitting elements and a sub-pixel circuit of the plurality of sub-pixel circuits being provided for an inorganic light emitting element of the plurality of inorganic light emitting elements, a driver configured to set the image data voltage to sub-pixel circuits included in each of the plurality of row lines in an order of the row lines, a sensing unit configured to sense a current flowing in a driving transistor included in the sub-pixel circuit based on a specific voltage applied to the sub-pixel circuit, and output sensing data corresponding to the sensed current, and a correction unit configured to correct the image data voltage applied to the sub-pixel circuit based on the sensing data.

Abstract: A driver includes a data voltage output terminal, a capacitor drive circuit that outputs each of first to n-th capacitor drive voltages corresponding to gradation data to a respective one of first to n-th capacitor driving nodes, a capacitor circuit including first to n-th capacitors each provided between an output node and a respective one of the first to n-th capacitor driving nodes, a processing circuit that generates a correction signal for correcting a voltage difference between an output voltage and a target voltage corresponding to the gradation data, and a correction circuit that corrects the voltage difference with a correction voltage corresponding to the voltage difference by injecting a charge corresponding to the correction signal into the output node or discharging the charge from the output node by using the correction capacitor circuit.

Abstract: A display device and a bezel thereof are provided. The display device includes a display panel and a bezel. The display panel has a first surface and a second surface. The first surface includes at least one pixel pad section, and the second surface includes at least one circuit pad section. The bezel includes a first surface connecting portion, a second surface connecting portion and at least one conductive wire. The edge of the display panel having the pixel pad section and the circuit pad section is accommodated between the first surface connecting portion and the second surface connecting portion. Each conductive wire has a first end and a second end. The first end is disposed on the first surface connecting portion and the second end is disposed on the second surface connecting portion. The part of the first connecting portion having the first end corresponds to the pixel pad section, and the part of the second connecting portion having the second end corresponds to the circuit pad section.

Abstract: The present application refers to a control method and control device of a drive circuit, and a drive circuit. The control method of the drive circuit includes: acquiring a bus address in a bus signal. The bus signal is a signal transmitted over an I2C bus, and the I2C bus is connected to a timing controller. The control method further includes: if the timing controller determining that the bus address matches an address of the timing controller, transmitting a frequency adjustment signal to a controllable power supply with an adjustable operating frequency and connected to the timing controller. The frequency adjustment signal is configured to indicate that an operating frequency of the controllable power supply is adjusted from a first operating frequency to a second operating frequency. The second operating frequency is higher than the first operating frequency.

Abstract: Display data of pixels is updated at different timings. A scan line is connected to a first pixel and a second pixel, a first wiring is connected to the first pixel, and a second wiring is connected to the second pixel. In a first period, a signal for selecting the first pixel and the second pixel is supplied to the scan line. Setting data for setting a state where the display data of the first pixel is updated is supplied to the first wiring, and setting data for setting a state where the display data of the second pixel is updated is supplied to the second wiring. In a second period, a signal for selecting the first pixel and the second pixel is supplied to the scan line. Setting data for setting a state where the display data of the first pixel is not updated is supplied to the first wiring, and the setting data for setting the state where the display data of the second pixel is updated is supplied to the second wiring.

Abstract: A display device includes: a substrate including a display area and a peripheral area outside the display area; a power wiring portion including a first power line in the peripheral area, a second power line spaced apart from the first power line and closer to the display area than the first power line, and connection power lines connecting the first power line to the second power line; and data lines in the peripheral area and having portions located between the connection power lines when viewed from a direction perpendicular to the substrate.

Abstract: The present disclosure provides a display device including a display panel and a scan signal generator configured to generate a (1-1)th scan signal and a (1-2)th scan signal to be supplied to a first horizontal line of the display panel and a (2-1)th scan signal and a (2-2)th scan signal to be supplied to a second horizontal line of the display panel, wherein the scan signal generator includes a switch circuit, and an output circuit.

Abstract: A gate driver and a display device comprising the same are discussed. The gate driver can comprise a plurality of stages for individually driving a plurality of gate lines by a combination of a plurality of group signals, a plurality of block signals, and a plurality of clock signals. Each of the plurality of stages driven independently can include an output buffer including a pull-up transistor configured to generate and output a gate-on level of a scan signal under the control of a first node, and a pull-down transistor configured to generate and output a gate-off level of the scan signal under the control of a second node. Each stage can further include a first controller configured to control the first node, and a second controller configured to control the second node to be opposite to the operation of the first node.

Abstract: The present disclosure relates to a protection circuit for a display device, a display device thereof, and a method for protecting a display device using a protection circuit. The display device includes a gate driving circuit, a level shift circuit, and a power management circuit. The level shift circuit is configured to provide an input signal to a signal input terminal of the gate driving circuit. The power management circuit is configured to provide power to the gate driving circuit. The protection circuit is configured to provide a power control signal to the power management circuit based on a current at the signal input terminal of the gate driving circuit, so that the power management circuit stops providing the power to the gate driving circuit.

Abstract: A display device includes display pixels arranged in a display area of a display panel, light-sensing pixels arranged alternately with the display pixels in the display area, light-sensing scan lines, each divided into at least two horizontal lines disposed adjacent to each other and connected to light-sensing pixels disposed proximate to the at least two horizontal lines, a display scan driver configured to sequentially supply display scan signals to display pixels connected to each horizontal line through display scan lines corresponding to each horizontal line, a blood-pressure detecting circuit configured to measure a user's blood pressure using light-sensing signals input through the light-sensing pixels, and a display driving circuit configured to control a timing at which the display scan signals are supplied to the display scan lines and a timing at which sensing scan signals are supplied to the light-sensing scan lines.

Abstract: The present disclosure provides common voltage compensation method and device for display panel, a display panel, and a display device. The display panel includes a common electrode, a common voltage compensation unit, and common electrode lines. The common electrode lines are sequentially numbered according to a distance from the common voltage compensation unit, a number of the common electrode lines is n, and n is an integer greater than 8. The method includes: the common voltage compensation unit providing common voltage to the common electrode; the common voltage compensation unit detecting actual common voltage on one of N1-th common electrode line to N2-th common electrode line, N1 being a value rounded down from n/8, and N2 being a value rounded down from n/4; the common voltage compensation unit compensating the common voltage of the common electrode according to the detected actual common voltage.

Abstract: Various implementations disclosed herein include devices, systems, and methods implemented by an electronic device with an imaging sensor that includes both an arrangement of first pixels and a plurality of second pixels at or near the perimeter (e.g., in a surrounding rectangle) of the arrangement. In some implementations, the second pixels, which may be larger in size than the arrangement of first pixels, can be intermittently positioned, for example, with intervening space in between groups of one or more second pixels along the side columns, top rows, or bottom rows of the arrangement. In some implementations, detected movement in a physical environment is determined to correspond to a person approaching the electronic device based on data of the second pixels. In some implementations, detecting the person approaching the electronic device initiates a user verification process at the electronic device.

Abstract: A pixel circuit provided corresponding to a scanning line and a data line includes a transistor and an OLED that is an example of a light emitting element. In a compensation period, a gate node and a drain node of the transistor are electrically coupled, and the gate node of the transistor has a voltage corresponding to a threshold voltage. In a writing period, the gate node of the transistor is changed from the voltage corresponding to the threshold voltage by a voltage corresponding to luminance of the light emitting element, and in a discharge period, a reset voltage is applied to a drain node of the transistor via a data line.

Abstract: An array substrate and a liquid crystal display panel are provided. The array substrate includes a substrate, a thin film transistor layer disposed on the substrate, and a pixel electrode disposed on the thin film transistor layer. The thin film transistor layer includes a plurality of data lines. The pixel electrode includes a first trunk electrode and a second trunk electrode. Portions of the data line corresponding to the first trunk electrode and the second trunk electrode overlap or partially overlap with the first trunk electrode and the second trunk electrode.

Abstract: An active matrix substrate includes, in each pixel region, a pixel TFT of an oxide semiconductor layer having source and drain regions, a first insulating layer disposed on top of the oxide semiconductor layer, an extraction electrode, disposed on top of the first insulating layer, that includes a transparent conductive film, and a pixel electrode connected to the extraction electrode. The first insulating layer includes first and second contact holes located above the source and drain regions, respectively. Part of a source bus line overlaps part of the source region and is connected to the source region via the first contact hole. The extraction electrode is connected to the drain region via the second contact hole. Shapes of bottoms of the first and second contact holes are different from each other, and the shape of the bottom of the second contact hole includes two orthogonal sides.

Abstract: A novel display panel that is highly convenient or reliable is provided. A pixel circuit includes a first switch, a node, a first capacitor, a second capacitor, and a second switch. The first switch includes a first terminal to which a first signal is supplied and a second terminal electrically connected to the node. The first capacitor includes a first terminal electrically connected to the node. The second capacitor includes a first terminal electrically connected to the node and a second terminal electrically connected to the second switch. The second switch includes a first terminal to which a second signal is supplied and a second terminal electrically connected to the second terminal of the second capacitor. In addition, the second switch has a function of changing from a non-conducting state to a conducting state when the first switch is in a non-conducting state and a function of changing from a conducting state to a non-conducting state when the first switch is in a non-conducting state.

Abstract: Provided is a novel display panel that is highly convenient or reliable, a novel data processor that is highly convenient or reliable, or a method for manufacturing a novel display panel that is highly convenient or reliable. The display panel includes a pixel and a terminal electrically connected to the pixel. The pixel includes a first insulating film, a first contact portion in a first opening provided in the first insulating film, a pixel circuit electrically connected to the first contact portion, a second contact portion electrically connected to the pixel circuit, a first display element electrically connected to the first contact portion, and a second display element electrically connected to the second contact portion. The first insulating film includes a region lying between the first display element and the second display element. The terminal includes a surface at which contact with other component can be made.

Abstract: The present disclosure provides a pixel driving circuit and a display panel. After pre-charging a first node to a first electrical potential, raising it to a second electrical potential through a first capacitor by a current row gate output signal G(n), and then raising it to a third electrical potential which is a high electrical potential greater than an electrical potential of the current row gate output signal G(n), so that a first transistor is turned on and data is written, raising an original electrical potential of a gate and improving driving capability since a gate electrical potential of the first transistor can be raised to greater than the G(n).

Abstract: A charge sharing circuit, a charge sharing method, a display driving module and a display device are provided. The charge sharing circuit includes a control unit and a switch unit. The control unit is electrically connected to first output control ends of two clock signal generation units, and configured to provide, when a first output module controls to not output a first voltage signal under the control of a first output control signal, an on control signal to the switch unit through a control signal output end. The switch unit is configured to control clock signal output ends of the two clock signal generation units to be electrically connected to each other under the control of the on control signal.

Abstract: A detector for imaging and efficiently digitizing a spatial distribution of photon flux includes pixel circuits that compressively encode pixel values generated by integrated analog to digital converters (ADCs). On-pixel digital compression circuits (DCCs) implement compression to increase continuous frame rate by reducing the number of bits per pixel while keeping quantization error below Poisson noise. Several mapping algorithms for photon-counting and charge-integrating detectors and compact digital logic implementations are presented.

Abstract: A display panel, a drive method, and a display apparatus are provided in the present disclosure. The display region of the display panel includes a plurality of scan line units; and each scan line unit includes two scan lines which extend along the first direction and are arranged along a second direction. The method includes, for displaying M frames of pictures, receiving a scan drive signal sequentially by a plurality of scan lines arranged along the second direction; and for displaying N frames of pictures adjacent to the M frames of pictures, receiving the scan drive signal sequentially by the plurality of scan line units arranged along the second direction; and along the second direction, for each same scan line unit, receiving the scan drive signal by an ith scan line after an (i+1)th scan line receives the scan drive signal.

Abstract: In an electro-optical device, a first light shielding wall and a second light shielding wall pass through sides of a semiconductor layer of a transistor respectively, and reach a scan line on a lower layer side. In a second interlayer insulating layer, a first contact hole and a second contact hole that reach a first source drain region and a second source drain region of the semiconductor layer respectively are provided. Respective widths of the first source drain region and the second source drain region are equal to or less than respective widths of the first contact hole and the second contact hole. Accordingly, the first light shielding wall and the second light shielding wall extend to sides of the first contact hole and the second contact hole respectively.

Abstract: A gate driver includes a plurality of gate stages. Each of the plurality of gate stages includes a carry generating circuit outputting a second carry signal having a phase which is later than a phase of a first carry signal, on the basis of a first clock signal and a second clock signal having different phases and a scan generating circuit outputting a scan signal having a phase which differs from phases of the first and second carry signals, on the basis of the first clock signal, the second clock signal, and the first carry signal. Each of the first clock signal, the second clock signal, the first carry signal, and the second carry signal may be a P-type pulse, and the scan signal may be an N-type pulse.

Abstract: A gate driver includes a first shift register connected to gate lines, and configured to supply a gate signal to the gate lines in response to a first start pulse, and a second shift register connected to the gate lines and sensing control lines, and configured to supply the gate signal and a sensing signal to the gate lines and the sensing control lines in response to a second start pulse, in which the second shift register is configured to supply the second start pulse at different times in sequential frames.