Abstract: The present application refers to a control method and control device of a drive circuit, and a drive circuit. The control method of the drive circuit includes: acquiring a bus address in a bus signal. The bus signal is a signal transmitted over an I2C bus, and the I2C bus is connected to a timing controller. The control method further includes: if the timing controller determining that the bus address matches an address of the timing controller, transmitting a frequency adjustment signal to a controllable power supply with an adjustable operating frequency and connected to the timing controller. The frequency adjustment signal is configured to indicate that an operating frequency of the controllable power supply is adjusted from a first operating frequency to a second operating frequency. The second operating frequency is higher than the first operating frequency.

Abstract: Display data of pixels is updated at different timings. A scan line is connected to a first pixel and a second pixel, a first wiring is connected to the first pixel, and a second wiring is connected to the second pixel. In a first period, a signal for selecting the first pixel and the second pixel is supplied to the scan line. Setting data for setting a state where the display data of the first pixel is updated is supplied to the first wiring, and setting data for setting a state where the display data of the second pixel is updated is supplied to the second wiring. In a second period, a signal for selecting the first pixel and the second pixel is supplied to the scan line. Setting data for setting a state where the display data of the first pixel is not updated is supplied to the first wiring, and the setting data for setting the state where the display data of the second pixel is updated is supplied to the second wiring.

Abstract: A display device includes: a substrate including a display area and a peripheral area outside the display area; a power wiring portion including a first power line in the peripheral area, a second power line spaced apart from the first power line and closer to the display area than the first power line, and connection power lines connecting the first power line to the second power line; and data lines in the peripheral area and having portions located between the connection power lines when viewed from a direction perpendicular to the substrate.

Abstract: The present disclosure provides a display device including a display panel and a scan signal generator configured to generate a (1-1)th scan signal and a (1-2)th scan signal to be supplied to a first horizontal line of the display panel and a (2-1)th scan signal and a (2-2)th scan signal to be supplied to a second horizontal line of the display panel, wherein the scan signal generator includes a switch circuit, and an output circuit.

Abstract: A gate driver and a display device comprising the same are discussed. The gate driver can comprise a plurality of stages for individually driving a plurality of gate lines by a combination of a plurality of group signals, a plurality of block signals, and a plurality of clock signals. Each of the plurality of stages driven independently can include an output buffer including a pull-up transistor configured to generate and output a gate-on level of a scan signal under the control of a first node, and a pull-down transistor configured to generate and output a gate-off level of the scan signal under the control of a second node. Each stage can further include a first controller configured to control the first node, and a second controller configured to control the second node to be opposite to the operation of the first node.

Abstract: A display device includes display pixels arranged in a display area of a display panel, light-sensing pixels arranged alternately with the display pixels in the display area, light-sensing scan lines, each divided into at least two horizontal lines disposed adjacent to each other and connected to light-sensing pixels disposed proximate to the at least two horizontal lines, a display scan driver configured to sequentially supply display scan signals to display pixels connected to each horizontal line through display scan lines corresponding to each horizontal line, a blood-pressure detecting circuit configured to measure a user's blood pressure using light-sensing signals input through the light-sensing pixels, and a display driving circuit configured to control a timing at which the display scan signals are supplied to the display scan lines and a timing at which sensing scan signals are supplied to the light-sensing scan lines.

Abstract: The present disclosure relates to a protection circuit for a display device, a display device thereof, and a method for protecting a display device using a protection circuit. The display device includes a gate driving circuit, a level shift circuit, and a power management circuit. The level shift circuit is configured to provide an input signal to a signal input terminal of the gate driving circuit. The power management circuit is configured to provide power to the gate driving circuit. The protection circuit is configured to provide a power control signal to the power management circuit based on a current at the signal input terminal of the gate driving circuit, so that the power management circuit stops providing the power to the gate driving circuit.

Abstract: The present disclosure provides common voltage compensation method and device for display panel, a display panel, and a display device. The display panel includes a common electrode, a common voltage compensation unit, and common electrode lines. The common electrode lines are sequentially numbered according to a distance from the common voltage compensation unit, a number of the common electrode lines is n, and n is an integer greater than 8. The method includes: the common voltage compensation unit providing common voltage to the common electrode; the common voltage compensation unit detecting actual common voltage on one of N1-th common electrode line to N2-th common electrode line, N1 being a value rounded down from n/8, and N2 being a value rounded down from n/4; the common voltage compensation unit compensating the common voltage of the common electrode according to the detected actual common voltage.

Abstract: Various implementations disclosed herein include devices, systems, and methods implemented by an electronic device with an imaging sensor that includes both an arrangement of first pixels and a plurality of second pixels at or near the perimeter (e.g., in a surrounding rectangle) of the arrangement. In some implementations, the second pixels, which may be larger in size than the arrangement of first pixels, can be intermittently positioned, for example, with intervening space in between groups of one or more second pixels along the side columns, top rows, or bottom rows of the arrangement. In some implementations, detected movement in a physical environment is determined to correspond to a person approaching the electronic device based on data of the second pixels. In some implementations, detecting the person approaching the electronic device initiates a user verification process at the electronic device.

Abstract: A pixel circuit provided corresponding to a scanning line and a data line includes a transistor and an OLED that is an example of a light emitting element. In a compensation period, a gate node and a drain node of the transistor are electrically coupled, and the gate node of the transistor has a voltage corresponding to a threshold voltage. In a writing period, the gate node of the transistor is changed from the voltage corresponding to the threshold voltage by a voltage corresponding to luminance of the light emitting element, and in a discharge period, a reset voltage is applied to a drain node of the transistor via a data line.

Abstract: An array substrate and a liquid crystal display panel are provided. The array substrate includes a substrate, a thin film transistor layer disposed on the substrate, and a pixel electrode disposed on the thin film transistor layer. The thin film transistor layer includes a plurality of data lines. The pixel electrode includes a first trunk electrode and a second trunk electrode. Portions of the data line corresponding to the first trunk electrode and the second trunk electrode overlap or partially overlap with the first trunk electrode and the second trunk electrode.

Abstract: An active matrix substrate includes, in each pixel region, a pixel TFT of an oxide semiconductor layer having source and drain regions, a first insulating layer disposed on top of the oxide semiconductor layer, an extraction electrode, disposed on top of the first insulating layer, that includes a transparent conductive film, and a pixel electrode connected to the extraction electrode. The first insulating layer includes first and second contact holes located above the source and drain regions, respectively. Part of a source bus line overlaps part of the source region and is connected to the source region via the first contact hole. The extraction electrode is connected to the drain region via the second contact hole. Shapes of bottoms of the first and second contact holes are different from each other, and the shape of the bottom of the second contact hole includes two orthogonal sides.

Abstract: A novel display panel that is highly convenient or reliable is provided. A pixel circuit includes a first switch, a node, a first capacitor, a second capacitor, and a second switch. The first switch includes a first terminal to which a first signal is supplied and a second terminal electrically connected to the node. The first capacitor includes a first terminal electrically connected to the node. The second capacitor includes a first terminal electrically connected to the node and a second terminal electrically connected to the second switch. The second switch includes a first terminal to which a second signal is supplied and a second terminal electrically connected to the second terminal of the second capacitor. In addition, the second switch has a function of changing from a non-conducting state to a conducting state when the first switch is in a non-conducting state and a function of changing from a conducting state to a non-conducting state when the first switch is in a non-conducting state.

Abstract: Provided is a novel display panel that is highly convenient or reliable, a novel data processor that is highly convenient or reliable, or a method for manufacturing a novel display panel that is highly convenient or reliable. The display panel includes a pixel and a terminal electrically connected to the pixel. The pixel includes a first insulating film, a first contact portion in a first opening provided in the first insulating film, a pixel circuit electrically connected to the first contact portion, a second contact portion electrically connected to the pixel circuit, a first display element electrically connected to the first contact portion, and a second display element electrically connected to the second contact portion. The first insulating film includes a region lying between the first display element and the second display element. The terminal includes a surface at which contact with other component can be made.

Abstract: The present disclosure provides a pixel driving circuit and a display panel. After pre-charging a first node to a first electrical potential, raising it to a second electrical potential through a first capacitor by a current row gate output signal G(n), and then raising it to a third electrical potential which is a high electrical potential greater than an electrical potential of the current row gate output signal G(n), so that a first transistor is turned on and data is written, raising an original electrical potential of a gate and improving driving capability since a gate electrical potential of the first transistor can be raised to greater than the G(n).

Abstract: A charge sharing circuit, a charge sharing method, a display driving module and a display device are provided. The charge sharing circuit includes a control unit and a switch unit. The control unit is electrically connected to first output control ends of two clock signal generation units, and configured to provide, when a first output module controls to not output a first voltage signal under the control of a first output control signal, an on control signal to the switch unit through a control signal output end. The switch unit is configured to control clock signal output ends of the two clock signal generation units to be electrically connected to each other under the control of the on control signal.

Abstract: A detector for imaging and efficiently digitizing a spatial distribution of photon flux includes pixel circuits that compressively encode pixel values generated by integrated analog to digital converters (ADCs). On-pixel digital compression circuits (DCCs) implement compression to increase continuous frame rate by reducing the number of bits per pixel while keeping quantization error below Poisson noise. Several mapping algorithms for photon-counting and charge-integrating detectors and compact digital logic implementations are presented.

Abstract: A display panel, a drive method, and a display apparatus are provided in the present disclosure. The display region of the display panel includes a plurality of scan line units; and each scan line unit includes two scan lines which extend along the first direction and are arranged along a second direction. The method includes, for displaying M frames of pictures, receiving a scan drive signal sequentially by a plurality of scan lines arranged along the second direction; and for displaying N frames of pictures adjacent to the M frames of pictures, receiving the scan drive signal sequentially by the plurality of scan line units arranged along the second direction; and along the second direction, for each same scan line unit, receiving the scan drive signal by an ith scan line after an (i+1)th scan line receives the scan drive signal.

Abstract: In an electro-optical device, a first light shielding wall and a second light shielding wall pass through sides of a semiconductor layer of a transistor respectively, and reach a scan line on a lower layer side. In a second interlayer insulating layer, a first contact hole and a second contact hole that reach a first source drain region and a second source drain region of the semiconductor layer respectively are provided. Respective widths of the first source drain region and the second source drain region are equal to or less than respective widths of the first contact hole and the second contact hole. Accordingly, the first light shielding wall and the second light shielding wall extend to sides of the first contact hole and the second contact hole respectively.

Abstract: A gate driver includes a plurality of gate stages. Each of the plurality of gate stages includes a carry generating circuit outputting a second carry signal having a phase which is later than a phase of a first carry signal, on the basis of a first clock signal and a second clock signal having different phases and a scan generating circuit outputting a scan signal having a phase which differs from phases of the first and second carry signals, on the basis of the first clock signal, the second clock signal, and the first carry signal. Each of the first clock signal, the second clock signal, the first carry signal, and the second carry signal may be a P-type pulse, and the scan signal may be an N-type pulse.

Abstract: A gate driver includes a first shift register connected to gate lines, and configured to supply a gate signal to the gate lines in response to a first start pulse, and a second shift register connected to the gate lines and sensing control lines, and configured to supply the gate signal and a sensing signal to the gate lines and the sensing control lines in response to a second start pulse, in which the second shift register is configured to supply the second start pulse at different times in sequential frames.

Abstract: A display substrate and a display device are provided. The display substrate includes sub-pixels and a light emitting control signal line. The sub-pixel includes an organic light emitting element and a pixel circuit, the organic light emitting element includes a second electrode, the pixel circuit includes a driving transistor and a first light emitting control transistor, and the pixel circuit further includes a connection structure. In the second color sub-pixel, a first electrode of the first light emitting control transistor is electrically connected with the connection structure through a first connection hole, and the connection structure is electrically connected with the second electrode through a second connection hole, the first connection hole and the second connection hole are located on both sides of the light emitting control signal line. In the third color sub-pixel, the second electrode does not overlap with a channel of the driving transistor.

Abstract: A display device can include a display panel including a plurality of subpixels; a feedback part; and a power source configured to output a first power voltage to the feedback part and the display panel, in which the feedback part is configured to output a virtual feedback voltage to the power source, the virtual feedback voltage being based on the first power, and the power source is further configured to adjust a magnitude of the first power voltage to generate an adjusted first power voltage based on the virtual feedback voltage.

Abstract: A display panel, a manufacturing method of the display panel, and a display device are disclosed. The display panel includes a first substrate and a second substrate. The first substrate includes a first base, a light-shielding layer disposed on the first base, and a color filter layer disposed on the first base, and a common electrode layer disposed on the light-shielding layer and the color filter layer. The common electrode layer is provided with an opening at a position opposite to the color filter layer.

Abstract: The present application provides a control component, a display screen, and a control device. The control component is integrated in a display screen and includes a substrate and a light control structure and a touch control structure arranged side by side on the substrate; the light control structure includes a signal input line, a signal output line, and a photosensitive circuit electrically connected between the signal input line and the signal output line; the touch control structure includes a plurality of receiving electrodes and a plurality of transmitting electrodes; and the receiving electrodes are multiplexed as the signal output line.

Abstract: A display device includes a display panel having scan lines, data lines, and sub-pixels disposed therein; a scan driver which drives the scan lines; and a data driver which drives the data lines. Each of the sub-pixels includes: a light emitting element; a driving transistor which drives the light emitting element; a 3-1th transistor electrically connected between a first node of the driving transistor and a high potential voltage; a 1-1th transistor and a 1-2th transistor each electrically connected between a second node of the driving transistor and a 1-1th or 1-2th data line, respectively; a second transistor electrically connected between a third node of the driving transistor and an initialization voltage line; a first capacitor connected between the second node and an anode electrode of the light emitting element; and a second capacitor connected between the high potential voltage and the anode electrode.

Abstract: According to an exemplary embodiment, a display device includes: a plurality of gate lines; a plurality of data lines; and a plurality of pixels connected to the gate lines and the data lines, wherein each of the pixels includes: a transistor configured to include a gate electrode, a first electrode, a second electrode, and a channel semiconductor; a pixel electrode connected to the second electrode and including a plurality of fine branch portions and a connector connected to the second electrode; and a target pattern overlapping a fine slit dispose between adjacent fine branch portions. At least one of the adjacent fine branch portions is directly connected to the connector.

Abstract: A pixel includes a switching transistor transmitting a data voltage to a first node, a storage capacitor electrically connected between a first power supply line and the first node and storing the data voltage, first and second driving transistors electrically connected to the first power supply line, the first node, and a second node, and first and second light emitting elements electrically connected between the second node and a second power supply line. An anode of the first light emitting element and a cathode of the second light emitting element are electrically connected to the second node, a cathode of the first light emitting element and an anode of the second light emitting element are electrically connected to the second power supply line, the first driving transistor is a P-type transistor, and the second driving transistor is an N-type transistor.

Abstract: Gate Driver on Array (GOA) circuit and display device solving problem of electrical stress easily biasing threshold voltage of thin film transistor (TFT), are provided. The GOA circuit including m cascaded GOA units, wherein an nth GOA unit includes a pull-up control unit, a pull-up unit, a compensation control unit, and a pull-down unit.

Abstract: A display panel includes a substrate, a first thin film transistor including a first semiconductor layer and a first gate electrode, a data line extending in a first direction, a scan line extending in a second direction, a second thin film transistor electrically connected to the data line and including a second semiconductor layer and a second gate electrode, a third thin film transistor including a third semiconductor layer and a first upper gate electrode arranged on the third semiconductor layer, a node connection line electrically connecting the first thin film transistor and the third thin film transistor, and a shield line located between the data line and the node connection line in a plan view and including the same material as the first upper gate electrode of the third thin film transistor. The first semiconductor layer includes a silicon semiconductor, and the third semiconductor layer includes an oxide semiconductor.

Abstract: An electronic device includes a display panel, a scan driving circuit, and a data driving circuit. The display panel includes a plurality of scan lines, a plurality of data lines, and a plurality of pixels. The scan driving circuit is configured to apply a scan signal to the scan lines. The data driving circuit is configured to apply a data signal to the data lines. The scan lines extend in a first direction. The scan driving circuit and the data driving circuit are arranged in the first direction.

Abstract: An organic light emitting diode (OLED) display is disclosed. In one aspect, the display includes a scan line transmitting a scan signal, a data line crossing the scan line and transmitting a data voltage, and a driving voltage line crossing the scan line and configured to transmit a driving voltage. The display also includes a switching transistor electrically connected to the scan line and the data line. The display further includes a driving transistor and a compensation transistor. A driving gate electrode and a driving drain electrode are respectively connected to a compensation source electrode and a compensation drain electrode. The display also includes a light blocking layer at least partially covering the compensation transistor and an OLED electrically connected to the driving transistor.

Abstract: A display device includes a display panel and an input sensor on the display panel, the input sensor including sensing electrodes, signal lines connected to the sensing electrodes, an insulating layer on the signal lines, and inspection lines on the insulating layer and electrically connected to each other, each of the inspection lines respectively overlapping a corresponding one of the signal lines.

Abstract: A light shielding area including a first conductive layer, a second conductive layer, a first conductor part disposed between the first conductive layer and the second conductive layer, and a transistor surrounded by the first conductive layer, the second conductive layer, and the first conductor part, and a light transmission area surrounded by the light shielding area are provided, wherein an edge of the first conductor part forms a part of a boundary between the light shielding area and the light transmission area.

Abstract: A panel control circuit for controlling a display panel comprising a first data line and a second data line includes a timing controller configured to generate input data comprising a first input data and a second input data, a first driving circuit configured to output a first video signal corresponding to the first input data into the first data line, and a second driving circuit configured to output a second video signal corresponding to the second input data into the second data line, wherein the timing controller is configured to turn off the second driving circuit based on a first deviation, a second deviation, or a third deviation.

Abstract: Disclosed are an array substrate drive circuit, a display module and a display device. The array substrate drive circuit includes: a signal driver configured for receiving a test signal, and generating a drive signal for driving a pixel array according to the test signal; and a signal isolator configured for dividing the drive signal into an even-numbered row drive signal and an odd-numbered row drive signal for driving the pixel array according to a preset control signal to drive the pixel array in rows. Since adjacent metal conductive layers will not output drive signals at the same time, even if the adjacent metal conductive layers are short-circuited, it can be detected during the test, thus improving the yield of the display panel.

Abstract: A driving circuit for a display panel includes a common voltage generating circuit. The common voltage generating circuit is coupled to multiple common electrodes of the display panel and configured to provide multiple common voltages respectively to the common electrodes. During a frame period, the common voltage generating circuit respectively changes a voltage level of the common voltages at different time.

Abstract: An array substrate includes a plurality of driving units, where each of the plurality of driving units includes a first electrode, a second electrode and at least one thin film transistor; the first electrode and the second electrode are configured to be connected to an anode and a cathode of a light-emitting diode, respectively, such that a vertical projection of the light-emitting diode on the array substrate overlaps with the at least one thin film transistor, and in a light-emitting direction of the light-emitting diode, the at least one thin film transistor is disposed on a backlight side of the light-emitting diode; and each of the plurality of driving units controls the light-emitting diode to be turned on or off according to a driving signal.

Abstract: A display device is provided and includes first and second pixel electrodes in first direction; first and second signal lines in first direction configured to be supplied with first or second binary signals inverted relative to each other; first potential line in second direction crossing first direction configured to be supplied with first potential; second potential line extending in second direction and configured to be supplied with second potential; first switching circuit configured to couple first pixel electrode to first or second potential lines; and second switching circuit configured to couple second pixel electrode to first or second potential lines.

Abstract: A display device includes: a panel including a plurality of panel pads; a circuit board including a plurality of connection pads corresponding to the plurality of panel pads, respectively; and a layer disposed between the panel and the circuit board and including a plurality of conductive particles. The layer includes: an overlapping portion that overlaps the plurality of panel pads and the plurality of connection pads in a first direction; and a non-overlapping portion that does not overlap the plurality of panel pads and the plurality of connection pads in the first direction. In the non-overlapping portion, the conductive particles are adjacent to one side of one panel pad of adjacent panel pads in a second direction intersecting the first direction.

Abstract: A display device is disclosed. Plural sub-pixels of display panel are electrically connected to a gate line set of corresponding row. Each data line is electrically connected to two adjacent sub-pixels of same pixel. The first gate line of each gate line set is electrically connected to one of odd-numbered and even-numbered ones of sub-pixels of pixels of same row. The second gate line of each gate line set is electrically connected to the other one of the odd-numbered and even-numbered ones of sub-pixels of pixels of same row. In one frame time, the data signal drives the two adjacent sub-pixels of same pixel through the nth and (n+1)th data lines using opposite polarities, and the data signal drives the column-direction adjacent two sub-pixels through the nth and (n+1)th data lines using opposite polarities.

Abstract: Provided are a shift register unit circuit and drive method, and a gate driver and a display device. The shift register unit circuit includes a first sub-unit circuit, a second sub-unit circuit, a third sub-unit circuit, and a fourth sub-unit circuit. Responsive to providing a corresponding input pulse and clock signal, the shift register unit circuit is configured output first, second, third, and fourth output signals. The shift register unit circuit is configured such that a fifth node is in conduction with a second node at least while the reset pulse is active.

Abstract: A pixel circuit, which may include a first pixel unit having a first display driving circuit (12), a first pixel electrode (P1), and a first control circuit (11), and a second pixel unit having a second display driving circuit (22), a second pixel electrode (P2), and a second control circuit (21). The first control circuit (11) may be configured to adjust and latch a voltage of a first positive phase node (Q1) and the first display driving circuit (12). The first display driving circuit (12) may be configured to provide a first display driving voltage to the first pixel electrode (P1). The second control circuit (21) may be configured to adjust and latch a voltage of a second positive phase node (Q2) and the second display driving circuit (22). The second display driving circuit (22) may be configured to provide a second display driving voltage to the second pixel electrode (P2).

Abstract: A pixel unit circuit includes a light emitting element, a first end thereof being coupled to a low level input end; a storage capacitor module, a first end thereof being coupled to a direct current voltage input end; a driving transistor, a gate electrode thereof being coupled to a second end of the storage capacitor module, and a first electrode thereof being coupled to a second end of the light emitting element; a first control module, coupled to a gate line, a data line and the gate electrode of the driving transistor, configured to control whether the gate electrode of the driving transistor is connected to the data line under the control of the gate line; and a potential control transistor, a gate electrode and a first electrode thereof being coupled to the first electrode of the driving transistor, the second electrode thereof being grounded.

Abstract: A display device includes a substrate including a display area having a plurality of pixel areas and a non-display area located at at least one side of the display area; a pixel in each of the pixel areas; and a plurality of fan-out lines in the non-display area to form a first conductive layer. The pixel includes a pixel circuit layer including at least one transistor and a first bridge line and a second bridge line; and a display element layer on the pixel circuit layer. Each of the first and second bridge lines is electrically connected to a corresponding fan-out line from among the fan-out lines.

Abstract: The present application discloses a shift-register unit. The shift-register unit includes a first sub-unit including a first input circuit coupled via a first node to a first output circuit. The first input circuit is configured to control a voltage level of the first node in response to a first input signal and the first output circuit is configured to output a shift-register signal and a first output signal in response to the voltage level of the first node. Additionally, the shift-register unit includes a second sub-unit including a second input circuit coupled via a second node to a second output circuit. The second input circuit is configured to control a voltage level of the second node in response to the first input signal and the second output circuit is configured to output a second output signal in response to the voltage level of the second node.

Abstract: A display device according to an embodiment of the disclosure includes a timing controller, a scan driver including a plurality of stages connected to a plurality of clock signal lines and generating a plurality of scan signals in response to the scan start signal, a data driver configured to generate a plurality of data signals based on the image data, and a pixel portion including a plurality of pixels. One stage in the scan driver transmits a carry signal to 2n-th next stage. The timing controller selects any one of a normal frequency and low frequencies lower than the normal frequency as a driving frequency based on the input image data, and adjusts a clock duty of the plurality of clock signals so that a time required to output all of the plurality of scan signals during one frame is constant irrespective of the driving frequency.

Abstract: A shift register unit, a gate drive circuit, a display device and a method of driving a gate drive circuit are provided. The shift register unit includes a shift register circuit and an output control circuit. The shift register circuit is configured to output a valid output level at a first output terminal according to a first input signal received by a first input terminal, and is configured to reset according to a first reset signal received by a first reset terminal. The output control circuit is configured to output an invalid output level at the second output terminal according to a second input signal received by the second input terminal, thereby controlling a level of the first output terminal to the invalid output level, and is configured to reset according to a second reset signal received by the second reset terminal.

Abstract: A liquid crystal layer as a member of a liquid crystal element is disposed between a first resin film substrate and a second resin film substrate. A first/second conductive film is attached to one side of the first/second resin film substrate. A blade is inserted into the liquid crystal layer. The blade is moved while being inserted in the liquid crystal layer, thus making an incision in the liquid crystal layer. Then, the incision location is widened in the first resin film substrate and in the second resin film substrate, forming an opening in the surface of the liquid crystal layer. This also forms a space inside the liquid crystal layer, allowing the opening to communicate with the space. Part of an electrode is then inserted into the space of the liquid crystal layer and the liquid crystal layer is bonded with part of the electrode.

Abstract: A multiplexer circuit includes a first switch unit and a second switch unit. The first switch unit is electrically connected to a first data line and a first pixel circuit, and configured to turn on according to a first signal in a first time duration. The second switch unit is electrically connected to the first data line and a second pixel circuit, and configured to turn on according to a second signal in a second time duration. The first time duration and the second time duration substantially start or end at a same time, so that the first time duration and the second time duration have overlap.