Integrated circuit layout utilizing separated active circuit and wiring regions
An LSI masterslice wiring technique, employing an array of elongated logic cells. A first level of metallization includes a first set of elongated, generally parallel conductors, orthogonal to the elongated logic cells and selectively contacting the cells. A second level of metal conductors, overlying and insulated from the first set, extends orthogonal to the first set, and thus parallel to the elongated logic cells. The second set includes both conductors passing over the areas of the logic cells and conductors lying between the logic cells. Conductors of the second set are selectively connected to conductors of the first set. This application has the same disclosure as that of Defensive Publication T100,501, published Apr. 7, 1981, but the abstracts are in conflict.
Type: Grant
Filed: May 5, 1980
Date of Patent: May 4, 1982
Inventors: John Balyoz (Hopewell Junction, NY), Algirdas J. Grwodis (Wappingers Falls, NY)
Application Number: 6/146,909
International Classification: H01L 2704;
