Patents by Inventor John Balyoz

John Balyoz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4737836
    Abstract: A very large scale multicell integrated circuit is provided with significantly improved circuit density. Both active and passive circuit elements are formed in a semiconductor substrate using ordinary diffusion techniques. Connectors, preferably made of polysilicon material, are then formed on the surface of the substrate. The connectors have bonding pad areas located along predetermined lines where metal connectors of later-formed metallization layers can be located. Some of the connectors have bonding pad areas connected to circuit elements while others are left unconnected. The subsequently formed metallization layers can then be used to connect together various ones of the circuit elements and multiple ones of the cells together in any desired circuit configuration using the polysilicon connectors.
    Type: Grant
    Filed: March 18, 1986
    Date of Patent: April 12, 1988
    Assignee: International Business Machines Corporation
    Inventors: Haluk O. Askin, Doyle E. Beaty, Jr., Joseph R. Cavaliere, Guy Rabbat, John Balyoz, Achilles A. Sarris
  • Patent number: 4295149
    Abstract: Disclosed are improved LSI semiconductor design structures termed "Master Image Chip Organization Techniques". Utilizing the technique provides increased density and optimized performance of semiconductor devices, circuits, and part number functions.In accordance with the disclosed Master Image Chip Organization Method the semiconductor chips are optimally structured to facilitate the maximum number of devices and circuits, and to facilitate fabrication of a wide variety of LSI part numbers. Essentially, none of the semiconductor surface is dedicated for signal and power wiring channels. A master image wiring structure is provided which resides over the semiconductor surface and beneath a power surface. In addition, the master image wiring structure provides a means for personalizing power and signal wiring for a multiple power surface structure.
    Type: Grant
    Filed: December 29, 1978
    Date of Patent: October 13, 1981
    Assignee: International Business Machines Corporation
    Inventors: John Balyoz, Chi S. Chang, Barry C. Fox, John A. Palmieri, Majid Ghafghaichi, Teh-Sen Jen, Donald B. Mooney
  • Patent number: 4249193
    Abstract: Disclosed is an improved masterslice design technique including structure, wiring, and method of fabricating, to provide improved Large Scale Integrated Devices.In accordance with the improved masterslice technique a plurality of semiconductor chips are provided wherein essentially the entire semiconductor surface area of each chip is utilized to provide cells selectable to be personalized (wired). None of the semiconductor surface area is dedicated for wiring channels. The individual cell area and cell configuration is optimally arrived at to facilitate wiring the maximum number, if not all of the cells contained on each chip, whereby circuit density is materially improved and a wide variety LSI device part numbers may be readily fabricated.
    Type: Grant
    Filed: May 25, 1978
    Date of Patent: February 3, 1981
    Assignee: International Business Machines Corporation
    Inventors: John Balyoz, Chi S. Chang, Barry C. Fox, John A. Palmieri, Majid Ghafghaichi, Teh-Sen Jen, Donald B. Mooney
  • Patent number: 4080720
    Abstract: An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less than that of prior layouts. Each circuit includes a first device including an elongated impurity region and a set of other impurity regions either in, or in contiguous relationship with, the elongated region; to form a set of diode junctions. The elongated region is capable of containing a predetermined maximum number of the other impurity regions. A second device is located adjacent the narrow side of said first device. A first set of first level conductors extends over the elongated region orthogonally with respect to the elongated direction and are interconnected to selected ones of the other impurity regions. Another conductor is a second level atop the substrate is connected to an impurity region of the second device and extends substantially parallel to the elongated direction.
    Type: Grant
    Filed: December 27, 1976
    Date of Patent: March 28, 1978
    Assignee: International Business Machines Corporation
    Inventors: John Balyoz, Algirdas Joseph Gruodis, Teh-Sen Jen, Wadie Faltas Mikhail
  • Patent number: 4032962
    Abstract: An integrated logic circuit having a novel layout in a semiconductor substrate. The area required for the circuits within the substrate is substantially less than that of prior layouts. Each circuit includes a first device including an elongated impurity region and a set of other impurity regions either in, or in contiguous relationship with, the elongated region to form a set of diode junctions. The elongated region is capable of containing a predetermined maximum number of the other impurity regions. A second device is located adjacent the narrow side of said first device. A first set of first level conductors extends over the elongated region orthogonally with respect to the elongated direction and are interconnected to selected ones of the other impurity regions. Another conductor in a second level atop the substrate is connected to an impurity region of the second device and extends substantially parallel to the elongated direction.
    Type: Grant
    Filed: December 29, 1975
    Date of Patent: June 28, 1977
    Assignee: IBM Corporation
    Inventors: John Balyoz, Algirdas Joseph Gruodis, Teh-Sen Jen, Wadie Faltas Mikhail
  • Patent number: T100501
    Abstract: In the method for fabricating a semiconductor substrate integrated circuit layout including: forming a plurality of spaced-apart circuit cells in columnar arrays within said substrate; forming a first insulating layer above said substrate, said layer having apertures therein to expose selected active regions of said selected cells; the improvement comprising: depositing first and second sets of elongated conductors in substantially parallel relationship atop said first insulating layer in said columnar direction; said first set being disposed directly atop said exposed cells to make selected contact with selected ones of said exposed active regions through said apertures in said first insulating layer; said second set being disposed in areas between said exposed cells; forming a second insulating layer above said first and second sets of conductors, said second insulating layer having apertures therein to expose selected ones of said first and second sets; and depositing a third set of substantially parallel,
    Type: Grant
    Filed: July 17, 1979
    Date of Patent: April 7, 1981
    Inventors: John Balyoz, Algirdas J. Gruodis
  • Patent number: T101804
    Abstract: An LSI masterslice wiring technique, employing an array of elongated logic cells. A first level of metallization includes a first set of elongated, generally parallel conductors, orthogonal to the elongated logic cells and selectively contacting the cells. A second level of metal conductors, overlying and insulated from the first set, extends orthogonal to the first set, and thus parallel to the elongated logic cells. The second set includes both conductors passing over the areas of the logic cells and conductors lying between the logic cells. Conductors of the second set are selectively connected to conductors of the first set. This application has the same disclosure as that of Defensive Publication T100,501, published Apr. 7, 1981, but the abstracts are in conflict.
    Type: Grant
    Filed: May 5, 1980
    Date of Patent: May 4, 1982
    Inventors: John Balyoz, Algirdas J. Grwodis
  • Patent number: T106201
    Abstract: A method for forming an improved integrated circuit chip structure having a surface from which regions of different conductivity type are arranged in a plurality of electrically isolated macro circuits, each macro circuit including interconnected components, a first X pattern of equally spaced parallel conductors overlying and electrically insulated from said chip structure surface, said first X pattern of conductors being selectively connected to at least certain ones of said plurality of macro circuits, a second Y pattern of equally spaced parallel conductors overlying and electrically insulated from said first pattern of parallel conductors, said second Y pattern of conductors being selectively connected to at least selected certain ones of said first pattern of electrical conductors, said spacing one from another of said first X pattern of conductors being equal to said spacing one from another of said second Y pattern of conductors, said first pattern of conductors being orthogonal of said second pattern
    Type: Grant
    Filed: January 13, 1983
    Date of Patent: March 4, 1986
    Inventors: John Balyoz, Chi S. Chang, Barry C. Fox, John A. Palmieri, Majid Ghafghaichi, Teh-Sen Jen, Donald B. Mooney