Abstract: In connection with remote feeder devices it is often necessary to take steps not to exceed limit values, for example the maximally permissible contact voltage. Customary voltage limiters evaluate the voltage at the output terminals of the remote feeder device. The remote feeder current can be distorted by the evaluation. With the invention, a dynamic resistor (V1, V2) is provided at the base point of the voltage limiter (BU), which can be set in such a way that the voltage drop at the remote feeder current regulator (RI) can be compensated. The range of the remote feeding or the distance between the intermediate current regenerators can be increased by means of the steps of the invention.

Abstract: A dual mode converter is provided that may be operated as a variable-frequency, naturally-commutated controller in a Zero-Voltage-Switching mode and as a fixed-off-time controller in a Fixed-Off-Time mode. The converter includes four functional elements. A reference and biases element generates voltage references and biases utilized to determine various signal states. A Timing element generates a fixed off time signal and a voltage ramp signal utilized to create the dual modes of operation. A Catastrophic-Event element detects events that cause the converter output be inhibited and the controller to be restarted. A Mode Detection and Pulse Width Modulation element determines the mode of operation for the converter based on signal inputs from the other functional elements and modulates the output accordingly. In a primary mode, the controller utilizes variable frequency operation to deliver primary power. In a standby mode, the controller utilizes fixed frequency operation to provide low power (less than 5W).

Abstract: A switch mode power converter circuit (20, 50) adapted to receive a driver voltage Vdiver includes a boot capacitor Cboot and a recharger for restoring the charge to the boot capacitor Cboot to a voltage substantially equal to the driver voltage Vdriver, where the recharger is internal to the circuit (20, 50). The recharger includes a synchronous rectifier S5 which restores the boot capacitor Cboot to a voltage equal to the driver voltage Vdriver less the voltage VS5 across the synchronous rectifier S5. Alternatively, the recharger may include a synchronous rectifier S5 and a first switch S4 of a charge pump circuit (22) that restore the charge to the boot capacitor Cboot in parallel to a voltage equal to the driver voltage Vdriver less the voltage VS5 across the synchronous rectifier S5 plus the voltage VS4 across the first switch S4. The circuit (20, 50) is particularly useful for applications such as DSPs and mixed signal or analog circuits.

Abstract: A circuit arrangement for delivering a supply current for an electronic circuit from a supply voltage source has a controllable current source arrangement which can be switched over so as to deliver a first and a second predetermined constant current. The second constant current is larger than the first constant current. An input of the controllable current source arrangement is connected to the supply voltage source and an output of the controllable current source arrangement is connected to an energy storage element and to the electronic circuit. The circuit arrangement further has a first reference voltage source for preparing a first and a second reference voltage. The second reference voltage is higher than the first reference voltage.

Abstract: A method and apparatus for mirroring currents in application specific integrated circuits provides higher current mirroring accuracy than previously obtainable with matched active devices by using small groups of resistors with local matching to create a summing node which represents the average voltage across the source resistors of the active output devices and by forming a reference resistor through the combination of resistors from the local resistor groups such that the reference resistor has properties which will largely cause cancellation of location gradients and initial value variation in the resistor groups. An error amplifier compares the voltage at the summing junction with the voltage across the reference resistor and adjusts its output voltage to drive the paralleled gates of each active mirror output device such that the summing junction and reference resistor voltages remain equal.

Abstract: A reusable miniaturized detector that utilizes magneto-optic elements to detect the occurrence of an electrostatic discharge during the manufacture or handling of electrostatic discharge sensitive electronic components and circuit boards. The device may also be used to determine the polarity and magnitude of the electrostatic discharge. The device may be manually or automatically read, either by removing the device from the environment being monitored or continuously monitoring in situ. The device can also be configured to provide protection to some electrostatic discharge events which could damage sensitive components being monitored.

Abstract: A high frequency wave measurement substrate comprising a dielectric substrate, a ground conductor being formed almost all over a bottom surface of the dielectric substrate, a microstrip line signal conductor and an radial stub-like equivalent ground conductor which is placed in proximity to an end of the microstrip line signal conductor being formed on a top surface of the dielectric substrate, a coplanar line structure wafer probe signal conductor and a ground conductor being electrically connected to both the signal conductor and the equivalent ground conductor, wherein the equivalent ground conductor is composed of a semi-circular or fan-shaped radial stub-like conductor pattern in which non-conductor areas are formed in its radial direction.

Abstract: A method and apparatus for determining the absolute position of a rotor in a permanent magnet synchronous machine (e.g. motor or generator) at standstill wherein short positive and negative voltage pulses are separately provided to each stator winding and the rate of current change with respect to time for each current is determined, the rates are used to determine general rotor position angle and thereafter are used to determine correction angle for correcting the general angle.

Abstract: A device is disclosed for measuring the position (location and orientation) in the six degrees of freedom of a receiving antenna with respect to a transmitting antenna utilizing multiple frequency AC magnetic signals. The transmitting component consists of two or more transmitting antenna of known location and orientation relative to one another. The transmitting antenna are driven simultaneously by an AC excitation, with each antenna occupying one or more unique positions in the frequency spectrum. The receiving antennas measure the transmitted AC magnetic field plus distortions caused by conductive metals. A computer then extracts the distortion component and removes it from the received signals providing the correct position and orientation output to a high degree of accuracy.

Abstract: A geartooth target providing a consistent magnetic signal for each feature type with unambiguously readable features has three unique 30° segments, each segment ending with a falling edge transition, the segments placed to have a unique pattern of segments every 90°.

Abstract: A detecting coil device mounted on part of a cable to evaluate the degree of corrosion of the cable, which is used, for example, on suspension or skew bridges. The detecting coil device is provided with a detecting coil and Hall elements. A magnetizer having a magnetizing coil is mounted as to enclose the cable and the detecting coil device. When current flows through the magnetizing coil, it magnetizes the cable. The magnetic field strength is detected by the Hall element, and the amount of magnetic flux passing through the cable is detected using the detecting coil. The cross-sectional area of the cable is also calculated on the basis of the magnetic field strength and the amount of magnetic flux which are detected and the permeability of the cable. The degree at which the cross-sectional area of the cable is decreased (the corrosion degree) is evaluated by comparing the calculated cross-sectional area of the cable with the cross-sectional area of a reference cable.

Abstract: According to the known method, a reference measurement is performed by measurement of magnetic resonance signals, without application of a magnetic gradient field to introduce phase encoding in the magnetic resonance signals. According to the invention, two measurements are performed with a read-out gradient of opposite polarity at substantially corresponding instants, relative to an instant at which the contributions to the phase error due to frequency deviations are zero. The advantage of the novel method resides in the fact that a higher insensitivity to field inhomogeneities and chemical shifts is achieved.

Abstract: The RF coil is an 8-shaped coil applied to a receiving coil, for example, of a so-called vertical field magnetic resonance imaging apparatus, and comprises a central conductor which is wide in a y-axis direction and a return path connected to the central conductor and provided to bypass the central conductor. The central conductor has an magnetic field sensitivity of interest in a y-axis direction orthogonal to a static magnetic field B0 direction (a z-axis direction). Since the return path has no magnetic field sensitivity of interest, the return path is provided to bypass the central conductor in order to prevent the magnetic field of the return path from interfering with the interest magnetic field of the central conductor.

Abstract: A flash phase analysis circuit provides parallel phase channels for simultaneously analyzing a detected signal in each of several phase windows and providing parallel outputs indicating whether a target falls in one of the phase windows. In one implementation, the parallel outputs each drive a segment of an output device to indicate the target type to the user. The flash phase analysis circuit divides a detected signal among the phase windows and then simultaneously compares the measured signal at each phase window with a reference signal. The circuit matches measured data with pre-selected phase characteristics corresponding to known targets in parallel and provides parallel output signals indicating target type.

Abstract: An apparatus for electronically testing or monitoring the condition of a storage battery is provided. The apparatus includes an inductance cancellation circuit for use in a Kelvin probe of an electronic battery tester. The induction cancellation circuit reduces inductive coupling between leads of the Kelvin probe. The apparatus also includes a DC coupled AC amplifier for amplifying an AC response signal of an electronic battery tester. Other aspects include a critically damped band-pass filter a response signal, a DC to DC convertor isolation circuit, operator editable test criteria, a battery temperature sensing element, an automatically adjustable gain stage and the use of an internal reference standard for a self calibration.

Abstract: A surface of the sample is scanned in intermittent contact mode with an the AFM. The probe tip is electrically conductive and is electrically connected to a capacitance sensing circuit. The oscillation of the AFM probe modulates capacitance between probe tip and sample surface. The modulated capacitance is demodulated to yield the capacitance properties of the sample.

Abstract: A circuit configuration for measuring resistance and/or leakage between two nodes, which includes a current source for feeding a test current into one of the two nodes and a circuit element that detects the voltage resulting between the two nodes. The output of a broadband signal generator is connected to a control input of the current source. The outputs of the circuit element and of the signal generator are connected to the inputs of the correlator for determining the correlation between their output signals.

Abstract: A new and improved system for testing tractor and trailer light systems interconnected by a cable wherein the trailer has a gladhand. The system includes a housing having a front control panel, a pair of battery terminals connected to said housing for connecting it to a battery and a cable connected to the housing having a connector which can be connected to an electrical receptacle of a trailer. Further, a plurality of switches are connected to the battery and the connector for testing various electrical circuits in the trailer. Additionally, a support rod is provided for engaging a convention glad hand thereby supporting the device in a hands free manner when in use.

Abstract: An electrical winding fault detection system wherein turn-to-turn and other winding faults in a polyphase alternating current machine are identified through processing of measured machine winding current flow changes, i.e., through identification of changes in electrical balance conditions in the machine. This disclosed processing includes scaling or normalization of measured operating currents using current measurements made while the machine is known to be in fault-free normal operating condition and altering the normalization by a relationship between average current flow in the fault-free condition and average current flow in the monitored changing load condition. Machine operation from a balanced energization source is preferred for successful use of the system; it is therefore especially suited to multiple phased machines operated from electronically derived alternating current energy. The invention is disclosed primarily in terms of a motor-operated machine; however, application to generator (i.e.

Abstract: Targeted portions of material layered structure is probed by microwave radiation focussed onto the targeted portion by adjustment of antenna position and orientation establishing a single oblique incidence path for reflection of antenna emitted probing radiation. Signal measurements of the radiation along the oblique incidence path is obtained to provide for evaluation and detection of defects in the targeted portion of the structure being probed.

Abstract: A device for measuring a crack in a workpiece or sample (3) comprises a resistive layer (1) arranged to be fixed to the workpiece so that the layer is fractured by the propagation of cracks in the workpiece or sample (3) to change the impedance of the layer (1). Two elongate electrodes (2) are provided on the resistive layer (1) and arranged to pass a current through it, and, measuring means are provided for measuring the impedance of the resistive layer (1), and for thereby determining the size of cracks in the workpiece or sample (3). Preferably another resistive layer (6), is provided adjacent the resistive layer (1), which is arranged not to be fractured by the propagation of cracks in the workpiece or sample (3). This enables environmental effects to be compensated for.

Abstract: Methods for the ready identification of dynamic defects using switching induced light emission from CMOS gates in complex integrated circuits such as microprocessors are described. The rapid increase in the complexity of logic circuits means that practical gate level identification of the sources of dynamic errors will require methods other than the gate by gate tracing of every possible path taken by a given set of instructions. The methods described here are based on the ability of picosecond imaging circuit analysis to detect the switching activity of every gate of a complex circuit in a single, passive measurement, and the ability of data processing today to compare large two- and three-dimensional files.

Abstract: A Schottky contact of a heterojunction field effect transistor is expressed by a set of regional elements each representative of a line or a region of said Schottky contact, and current components respectively passing through the regional elements are expressed as I ⁡ ( R1 , R2 , ⋯ . , R N ) = ∑ k = 1 N ⁢ J k ⁢ R k where I is a gate current current, Rk is a length of the line or an area of the region, N is equal to or greater than 3 and Jk is a current density of one of the current components so that an analyst checks the current components to see whether or not the Schottky contact has a trouble.

Abstract: A retainer for a circuit board test probe includes a unitary member in which the test probe is inserted. The retainer may then be plugged into a desired opening in a test fixture plate, with a circumferential bead on the retainer and a circumferential groove in the plate opening providing a snap-in feature. Inward compression of the retainer moves the bead out of the groove to allow the retainer to be removed from the plate opening.

Abstract: Bus coupler for transformer-free transmission onto a bus appertaining to building system technology, in particular the European Installation Bus Association, (“EIBA”) said bus carrying information, comprising active pulse and equalizing pulse, and energy. It is provided that the transmission valve of a transmission signal generator, in accordance with the function, is connected to at least one bus conductor via a capacitance, which is small relative to an imaginary capacitance acting as a short circuit for the active pulses of the information, it being the case that in a Miller circuit, in accordance with the function essentially further comprising a transistor, and a drive resistor, and two current amplifier circuits, this small capacitance is transformed into a sufficiently large capacitance in order to transmit active pulses in a sufficiently loss-free manner, and energy storage for the purpose of generating the equalizing pulse being effected in a further capacitance.

Abstract: An output buffer capable of reducing the noise and distortion of buffered output data while operating at high speed, and a buffering method performed in the output buffer are provided. An output buffer for buffering input data and outputting buffered input data as output data comprises first through M-th and (M+1)th through (M+N)th delay means for delaying the input data for (M+N) different delay times and outputting one by one delayed data in a predetermined order at time intervals of T M + N , where M and N are each integers equal to or greater than 2, and T corresponds to the time necessary for the level of the output data to change, and a data output means for outputting the output data in response to the outputs of the first through (M+N)th delay means.

Abstract: A signal transmitting circuit includes one or more circuit blocks having a driving circuit and an intra-block transmission line for transmitting a signal produced by the driving circuit, one or more circuit blocks having a receiving circuit and an intra-block transmission line for transmitting the signal to said receiving circuit, and a main interblock transmission line for propagating a signal between both of the driving and receiving circuit blocks. Inter-block transmission line is terminated at one or two ends by one or two resistors having substantially the same impedance as the interblock transmission line itself.

Abstract: A method of minimizing power use in programmable logic devices (PLD) using programmable connections and scrap logic to create a versatile power management scheme. Individual product terms in a PLD can be powered off, thereby saving power, without incurring the power-up and settling time delays seen in the prior art. Power management is not restricted to any one function block, nor must the entire device be powered down, unless so programmed. All conventional logic functionality present in the PLD is available to the power management elements, allowing, in one embodiment, a standard function block to be programmed to operate as the control function block. This logic functionality includes, but is not limited to, internal feedback, combinatorial functions, and register functions. Because scrap logic resources left over from user programming and small programmable connections are used, minimal additional chip surface area is needed.

Abstract: A method of operating a pin of an in-system programmable logic device (ISPLD) which includes the steps of (1) applying a predetermined voltage to the pin when the ISPLD is in a set-up mode, and (2) maintaining the last voltage applied to the pin when the ISPLD is in a normal operating mode. The ISPLD is in the set-up mode when the logic of the ISPLD has not yet been configured, or is being configured. The ISPLD is in the normal operating mode after the logic of the ISPLD has been configured. A particular ISPLD includes a pin and a logic gate having a first input terminal coupled to the pin, a second input terminal coupled to receive a control signal, and an output terminal coupled to the pin. When the ISPLD is in the set-up mode, the control signal causes the logic gate to apply a predetermined voltage to the pin. When the ISPLD is in the normal operating mode, the control signal causes the logic gate to maintain the last applied voltage on the pin.

Abstract: The present invention allows one portion of an FPGA to reconfigure another portion of the same FPGA. The invention makes use of input/output ports that can be connected on the input side to a frame register for loading configuration data into the FPGA. When a portion of the FPGA is to be reconfigured, data are loaded by a portion of the FPGA not being reconfigured into the frame register of the FPGA and addressed to the portion of the FPGA being reconfigured. Loading of the data is accomplished by forming a configuration data stream in the portion of the FPGA not being reconfigured, then applying the configuration data stream to an output buffer of the FPGA and forwarding that data to an input buffer that is connected to a frame register of the FPGA configuration structure.

Abstract: In order to achieve rapid reconfiguration of logic elements in a programmable logic device, a plurality of memory logic modules are arranged in a two-dimensional array. At least one logic element is provided in each of the plurality of memory logic modules. The logic element is provided with a configuration memory into which configuration data can be written to specify logic functions of the logic element. A memory element is provided in each of the plurality of memory logic modules. The memory element stores a plurality of configuration data with respect to the logic element, and one of the plurality of configuration data is written into the configuration memory of the logic element to configure or reconfigure the logic element.

Abstract: A digital CMOS predriver circuit pulls an output node up and down with accurately controlled rise and fall times in the threshold region. Resistors independently set rise and fall slew rates while additional CMOS devices initially charge and discharge the output node. The additional devices turn off before the output reaches the threshold region.

Abstract: A system and method for translating a non-logic-family signal level into a logic-family signal level, the system comprising: a source of a non-logic-family signal that can assume a first and a second non-logic-family state; and a translator for determining whether the signal is in the first non-logic-family state, and if so, providing a translated signal having a first-logic family level. The translator can take the form of a comparator controlling an output transistor tied to a pull-up resistor, or a programmed processor. Examples of the logic-families include transistor-transistor logic (TTL) and complimentary metal oxide semiconductor (CMOS) logic. Examples of sources of non-logic-family signals includes a light emitting diode, a buzzer and a beeping device.

Abstract: There is disclosed a data input buffer for buffering external input signals into signals suitable for internal signals in a semiconductor memory device. The data input buffer includes switching means controlled by first and second determination signals; and a buffering circuit which is operated as a SSTL buffer or a LVTTL buffer according to the operation of the switching means.

Abstract: A circuit includes a drive transistor or selectively coupling an output terminal to a power supply. The transistor has a control terminal coupled to an input terminal by a slew rate control device to control the slew rate of the drive transistor. In an embodiment, the slew rate control device includes two parallel pass gates which implement a variable resistance for switching between a normal and a slow slew mode. In one embodiment, a tri-state output buffer is disclosed including a pull-up device and a pull-down device, each with associated pass gates for implementing slew rate control. In a favorable embodiment, a control circuit controls the pass gates so that in the slow slew mode, the drive transistors turn off as quickly as in the normal slew mode.

Abstract: A semiconductor interface circuit connected between a first semiconductor device driven by a first level power voltage and a second semiconductor device driven by a second level power voltage which is higher than the first level power voltage. The semiconductor interface circuit includes an output buffer circuit being connected to the first semiconductor device; and at least a depletion type field effect transistor connected between the output buffer circuit and the second semiconductor device, wherein the at least depletion type field effect transistor has a driving capability substantially equal to or near a driving capability of the output buffer circuit.

Abstract: Signals inputted from nodes N2 and N4 to output circuit 100 are respectively transmitted to clocked inverters 31 and 32. Clocked inverter 31 is activated when node N4 is H level while clocked inverter 32 is activated when node N2 is L level. Output signal of clocked inverter 31 is supplied to gate electrode of PMOS 61 via node N5 while output signal of clocked inverter 32 is supplied to gate electrode of NMOS 62 via node N6. Voltage level of node N5 is pulled up when node N4 is L level while voltage level of node N6 is pulled down when node N2 is H level. With such a construction, it is possible to provide the output circuit capable of reducing feedthrough current without deteriorating high speed responsivity.

Abstract: A deskew circuit for synchronizing output signals from a fanout buffer. The circuit includes one capacitive element coupled to each of the buffer's output nodes. Each capacitive element is also coupled to a common floating bus. The capacitive element is preferably a capacitor and the common floating bus is electrically isolated from any power rails. The bus may be formed of polysilicon or metal.

Abstract: A domino logic circuit having output noise elimination is disclosed. A compound domino logic circuit includes at least two trees of logic devices arranged in parallel, with each tree having a precharge transistor connected to a power supply, and one or more input transistors coupled between the precharge transistor and ground. The precharge transistor receives a clock input while each of the one or more input transistors receives a signal input. The compound domino logic circuit also includes a logic gate coupled to the precharge transistor to produce a signal output. The logic gate includes at least two transistors connected in series. Further, an adjustment transistor is coupled to a node between the two transistors to ground.

Abstract: A decoder is provided for generating N output signals, the decoder comprising a precharged gate structure arranged to receive two or more input signals and to generate N intermediate signals. In a precharge phase, the precharged gate structure is arranged to output the N intermediate signals at a first logic value, and in an evaluate phase the precharged gate structure is arranged to maintain a first intermediate signal at the first logic value, and to cause all other intermediate signals to transition to a second logic value. Further, self-timed logic is provided for receiving the N intermediate signals, and for generating the N output signals, the self-timed logic being arranged, during the precharge phase, to generate the N output signals at the second logic value, and during the evaluate phase to cause a first output signal corresponding to the first intermediate signal to transition to the first logic value.

Abstract: A wordline decoder circuit and method of decoding a wordline input signal are provided. A first decoder receives multiple inputs to be evaluated. The first decoder includes a first precharge device for precharging a first node and a first discharge device to enable discharging the first node. A first clock signal enables the first discharge device. The first clock signal disables the precharge device. A clock delay circuit receives the first clock signal and generates a delayed clock signal. A second logic is coupled to the first decoder. The second logic provides a wordline output. The second logic wordline output is enabled responsive to the delayed clock signal and is disabled responsive to the first clock signal.

Abstract: The object of the present invention is to provide a semiconductor integrated circuit device wherein the input signal is made to have a low amplitude to shorten transition time of the input signal, said integrated circuit device operating at a low power consumption, without flowing of breakthrough current, despite entry of the input signal featuring low-amplitude operations, and said integrated circuit device comprising a gate circuit, memory and processor.

Abstract: A phase detector for measuring phase differences between K input signals is provided. The phase detector includes a counter, K first registers and a first subtractor. Each first register receives the counter signal of the counter and a respective input signal for updating a counter value in response to timing information on the input signal. The first subtractor receives the counter values to generate phase difference representing values. A frequency detector is also provided. The first subtractor is substituted by a second subtractor and K second registers are included. Each second register is connected to a respective first register. Each second register receives the counter value of its first register and the same input signal as that of its first register for backing-up the counter value as a back-up counter value in response to the timing information on the input signal.

Abstract: A gain control arrangement is suitable for controlling the gain of a variable gain amplifier in dependence on the difference between the actual magnitude and the desired magnitude of a read signal provided over an optical data carrier read channel. The amplitude of the read signal is sampled at periodic sampling points to determine an envelope value based on the sample value at a sampling point and an envelope value at a preceding sampling point, and a gain error value is derived from the difference between that envelope value and a desired envelope value.

Abstract: CMOS comparators are provided that have substantially improved operating frequency ranges. They include first and second differential pairs of transistors and first, second, third and fourth current mirrors. The first and second differential pairs both respond to an analog input signal but only the first differential pair is coupled to define an output port. The first and second current mirrors are cross coupled to the transistors of the first differential pair but each of the third and fourth current mirrors are cross coupled between a respective transistor of the second differential pair and a respective transistor of the first differential pair. The third and fourth current mirrors provide high-speed discharge paths for parasitic circuit capacitances. The comparator structure can be adjusted to control comparator slew rates and hysteresis.

Abstract: A hysteresis comparator circuit which has: a first differential input circuit that operates according to the difference between input voltage and reference voltage; an adder circuit that is composed of first and second addition input ends and differential output voltage of the first differential input circuit is input to the first and second addition input ends as first addition input; a quantizer that quantizes output voltage of the adder circuit and outputs the quantized value as output signal; an attenuator that attenuates output voltage of the quantizer; and a second differential input circuit that applies differential output obtained by differential-amplifying output voltage of the attenuator to the first and second addition ends as second addition input as well as forming a positive-feedback system.

Abstract: A semiconductor device has a DLL circuit or the like for adjusting the phase of an external clock and producing an internal clock that lags behind by a given phase. The semiconductor device further includes a clock frequency judging unit for judging the frequency of a first clock on the basis of an indication signal indicating a delay value of the first clock in the DLL circuit or the like to output a control signal; and a clock selecting unit for selecting either one of the first clock and the second clock, in response to the control signal.

Abstract: A method and an apparatus for reading a given digital pulse signal of variable length in the domain of a first clock frequency and creating a pulse output signal that is synchronized in the domain of a second clock. The number of cycles the input pulse signal is active, in terms of the first clock, is the same number of cycles as the resulting output signal is active, where for the output signal the number of cycles is measured by the second clock.

Abstract: A first latch circuit latches output data in response to a leading edge of a clock signal. A second latch circuit latches the output data in response to a trailing edge of the clock signal. When the first latch circuit latches a low level, an n-channel MOS transistor is turned to an on-state in order to supply the transmission path to the low level. When the first latch circuit latches a high level, a p-channel MOS transistor is turned to an on-state during a period during which the second latch circuit latches the low level. The transmission path is supplied to thq high level.

Abstract: The present invention provides a circuit to transfer data from a first clocked domain to a second clocked domain. The circuit includes a first latch clocked by a first clock signal and a second latch clocked by a second clock signal that is faster than the first clock signal. The circuit further includes a clock enabling circuit to receive the second clock signal and the signal indicating that a transition of the first clock has occurred and to provide the second clock signal to the second latch after the transition of the first clock signal. In another embodiment, the present invention provides a circuit to transfer data from a first clock domain to a second clock domain that is asynchronous with respect to the first clock domain. The circuit includes a first latch sequenced by a first clock signal that has a first frequency and the second latch sequenced by a second clock signal that has a second frequency substantially lower than the first frequency.