Abstract: A sense circuit for multi-level flash memory cell includes a control signal generator for generating a plurality of voltage control signals, a clock signal having constant period and a plurality of control pulses according to a sense amplifier enable signal; a control voltage generator for generating multi-steps voltage according to the clock signal and the plurality of voltage control signals, sequentially supplying the multi-steps voltage to a program gate of the memory cell, generating a reference voltage according to the sense amplifier enable signal and supplying the reference voltage to a program gate of a reference cell; and a sense amplifier for sequentially comparing a plurality of data stored in the memory cell and a data of the reference cell, storing the result according to the control pulse and converting it into binary data.

Abstract: A non-volatile semiconductor memory device is provided which is capable of shortening time required for determining a reading voltage in its reading circuit and of improving a data reading speed.

Abstract: A semiconductor memory device having a bit line which is precharged quickly is disclosed. According to the presenti invention, a semiconductor memory device includes a bit line which is connected to a memory cell, a first precharging circuit which precharges said bit line during a first time period, and a second precharging circuit which precharges said bit line during a second time period, wherein said first time period being longer than said second time period.

Abstract: A single-poly flash memory cell has a control device, a switch device, and an erase device, all of which share a common polysilicon floating gate which is designed to retain charge in the programmed memory cell. The memory cell is erased by applying an erase voltage to the tub of the erase device to cause tunneling across the oxide layer separating the floating gate from the rest of the erase device structure. Since a typical tub-to-source/drain breakdown voltage (e.g., 15 volts) is greater than a typical erase voltage (e.g., 10 volts), the memory cell can be safely erased without risking the junction breakdowns that are associated with other prior art single-poly memory cell designs for deep sub-micron technologies (e.g., 0.25-micron and lower).

Abstract: Circuit for controlling a sense amplifier, is disclosed, which restores a signal delayed by line loading for faster operation of the sense amplifier in a case every one or every group of a few of the sense amplifiers is provided with one sense amplifier drive for faster data sensing of the sense amplifier, including signal transmission means for compensating a signal /SP or SN for controlling a drive of a sense amplifier for a path basis transmission delay in addition to a sense amplifier pull-up driver and a sense amplifier pull-down driver for driving sense amplifiers connected to one pair of bit lines B/L, and /BL for a positive, and a negative signals, and a sense amplifier driver precharge circuit for precharging the sense amplifier drivers when the sense amplifier are not in operation.

Abstract: An integrated circuit includes primary circuit elements selectable by n address bits. A master storage device is programmable to indicate that at least one primary circuit element is being replaced. Redundant circuit elements each include a non-precharging matching circuit, which includes sub-match circuits. The sub-match circuits include two state storage devices corresponding to one of the possible binary values of at least one of the n address bits and activate a sub-match signal when the binary value of the at least one of the n address bits corresponds to one of the two state storage devices in a first state if the master storage device is programmed. A match circuit activates a match signal in response to all sub-match signals being active to disable a primary circuit element from being selected by a corresponding binary value of the n address bits and to enable the redundant circuit element to be selected by the corresponding binary value of the n address bits.

Abstract: There is provided a semiconductor memory which allows a redundant memory cell to be disposed at the center while maintaining the continuity of layout units of direct peripheral circuits and allows the total yield of the memory cell and the direct peripheral circuits to be improved. The inventive semiconductor memory is a 64 M-bits or 256 M-bits DRAM using a hierarchical word line structure or a multi-division bit line structure and comprises a main row decoder region, a main word driver region, a column decoder region, a peripheral circuit/bonding pad region, a memory cell array, a sense amplifier region, a sub-word driver region, intersection regions and the like formed on one semiconductor chip.

Abstract: A redundancy circuit is capable of repeatedly replacing a defective cell with redundant cells. The redundancy circuit is in a semiconductor memory device that includes memory cells and redundant cells in a memory array. The redundancy circuit includes first and second fuse blocks. The first fuse block has a first main fuse and generates a first redundancy signal according to whether the first main fuse is cut. The first redundancy signal indicates whether there is a defective memory cell for the redundancy circuit to replace. The second fuse block has a second main fuse and generates a second redundancy signal according to whether the second main fuse is cut. The second redundancy signal can stop the replacement of the defective cell with the redundant cell when the redundant cell is defective. When the replacement of the defective cell with the redundant cell is stopped, the defective cell is replaced by another redundant cell.

Abstract: A dynamic memory includes memory cells combined to form blocks and blocks combined to form at least one block group. The memory also includes bit lines and word lines connected to the memory cells for selecting the memory cells, redundant memory cells within the blocks, at least one redundant word line in at least one of the blocks, and a decoder unit connected to the word lines. The redundant word lines are connected to the redundant memory cells for selecting the redundant memory cells. A redundant word line, after redundancy programming has been carried out, selectively replaces a word line in any of the blocks. In a first mode of operation, no more than one of the word lines is selected simultaneously per block group. In a second mode of operation, more than one of the word lines is selected simultaneously per block group, and redundancy programming is deactivated.

Abstract: A memory device with redundancy arrays, including row word lines and column selective lines respectively selected by a plurality of row address signals and column address signals. A bank includes a first block and a second block separately driven by the different logic values of the first row address signal. In addition, a plurality of pairs of odd arrays and even arrays and a plurality of corresponding spare rows and spare columns are located in the first and second blocks, wherein the odd arrays and the even arrays are separately driven by the different logic values of the second row address signal, and the other row address signals are used to select the row word lines located in the odd arrays or even arrays. If the selected row word line is a defective row, it will be replaced by one of the spare rows, and if the column selective line selected by a plurality of column address signals is a defective column, it will be replaced by one of the spare columns.

Abstract: A semiconductor memory test circuit comprises a current mirror circuit including a reference side current path composed of a series connection of alternating p channel transistors and n channel transistors and an output side current path composed of a series connection of alternating p channel transistors and n channel transistors, an output signal for electrode of paired memory cells and a balance potential output signal for sense amplifier, required for a semiconductor memory test, being derived from the output side current path. The current mirror circuit includes a first output side current path and a second output side current path, the balance output for sense amplifier is derived from an output of the first output side current path and the output signal for electrode of paired memory cells is derived from an output of the second output side current path.

Abstract: A method and structure for a dynamic random access memory chip includes memory element arrays having bitlines, a sense amplifier shared by the arrays. The sense amplifier includes multiplexors connected to the bitlines, an equalizer circuit connected to the multiplexors and a timer circuit connecting first bitlines to the sense amplifier a time period after second bitlines are sensed by the sense amplifier, wherein the time period is less than the active phase of the row cycle.

Abstract: A current sensing amplifier for detecting a small current difference between a pair of variable resistance loads comprises a first amplifier and a second amplifier. The first amplifier comprises a voltage clamp including first and second outputs, the voltage clamp being coupled to the pair of variable resistance loads and substantially fixing a predetermined voltage across the variable resistance loads, the voltage clamp transferring the measured current difference to the first and second outputs. The first amplifier further includes a differential current source coupled to the first and second outputs. The second amplifier includes first and second inputs and an output, the first and second inputs being coupled to the first and second outputs, respectively, of the first amplifier.

Abstract: A semiconductor integrated circuit device has a memory array which includes amplifying MOSFETs of sense amplifiers which amplify small voltages read out of dynamic memory cells onto bit lines and column switch MOSFETs which select bit lines, a read/write section which includes main amplifiers for reading out stored data from memory cells selected by the column switch, and a logic circuit which implements the input/output operation of data with the read/write section. Two capacitors each having a first electrode which corresponds to a plate electrode with the same structure as that of storage capacitors of dynamic memory cells and a second electrode which is multiple commonly-connected storage nodes of the storage capacitors are arranged in serial connection, disposed contiguously to the read/write section, and connected between operation voltage lines of the read/write section.

Abstract: In a data rate converter, input data received in series synchronously with an input clock signal is converted into parallel data so as to be written into a memory, and the written parallel data is read from the memory and converted into serial data synchronously with an output clock signal so as to be outputted. Clock pulses of the input clock signal are counted to obtain an input count value. A ready signal is produced based on the input count value for allowing the start of reading the parallel data from the memory. The ready signal has a pulse width greater than two periods of the output clock signal. A trigger signal is produced upon detection of the second leading or trailing edge of the output clock signal within the pulse width of the ready signal. In response to the trigger signal, clock pulses of the output clock signal are counted to obtain an output count value. A read signal is produced based on the output count value for reading the parallel data from the memory.

Abstract: The first-in first-out storage device has a write counter for counting as a write address the number of data write operations of a write side circuit, a read counter for counting as a read address a number of data read operations of a read side circuit, a RAM which stores data input from the write side circuit into a storage region that corresponds to the write address when the write side circuit has performed the write operation and outputs the data stored in the storage region that corresponds to the read address to the read side circuit when the read side circuit has performed the read operation, a full-state detection unit which detects whether the write operation of the write side circuit needs to be restricted or not based on the write address and read address, a flip-flop which outputs a detection result obtained by the full-state detection unit to the write side circuit in synchronization with a write clock signal based on which the write side circuit operates, an empty-state detection unit which dete

Abstract: A first-in, first-out memory circuit includes first and second memory part respectively having first and second address locations each of which has a first word length, a write address counter outputting a write address signal and a memory part selection signal to the first and second memory parts in response to a word length selection signal, and a memory part enable circuit which is coupled between the write address counter and the first and second memory parts and receives the memory part selection signal. The memory circuit also includes a data bus which is applied with the input data and which includes a first data bus having the first word length and a second data bus having the first word length, and a data input part which is coupled between the data bus and the first and second memory parts.

Abstract: Improvement in an operating speed of a semiconductor device reduces power consumption. A current flowing through internal circuits 2A and 2B is supplied, via nodes N5 and N6, by transistors 13 through 20 forming two current mirror circuits as required. A voltage supplied to the internal circuits 2A and 2B is supplied from a transistor 10 via the nodes N5 and N6.

Abstract: A memory device includes a memory array and at least two sets of row decoders to drive row lines in the memory array. Select lines (such as row select lines) carry signals to select one or more decoders in one of the two sets of decoders. At least some of the select lines are shared between the two sets of row decoders to decrease the space needed to route signal lines in the memory array.

Abstract: The present invention provides a semiconductor memory device having a dynamic random access memory and a static random access memory for transmissions of data between the dynamic random access memory and the static random access memory, wherein there are provided a plurality of dynamic random access memory arrays, each of which comprises a pair of a dynamic random access memory cell array and a sense amplifier for data read/write operation to the dynamic random access memory cell array, and there is provided at least a static random access memory array, and the plurality of dynamic random access memory arrays and the at least a static random access memory array are connected through at least a data transmission bus.

Abstract: In a burst operation, a counter (18) receives one or more bits of a starting column address. The count signal (A[2:1]) generated by the counter is provided to an address adder (20). The address adder generates column address bits (B[2:1]) for a column to be selected in the burst operation. The Y-decoder circuitry (16.0,16.1) selects an even column and an odd column in parallel. The count address bits (A[2:1]) are used as address bits for the even column, and the address bits (B[2:1]) generated by the address adder are used as address bits for the odd column, or vice versa. The even and odd columns can be at non-consecutive column addresses, or they can be at consecutive column addresses starting at an odd column address boundary. Some embodiments are suitable for burst operations defined by standards for synchronous dynamic random access memories. Some embodiments are suitable for double data rate memories.

Abstract: A programmable logic device memory array circuit is provided that contains a pair of associated combinable single-port memory arrays. The memory array circuit may have a variable depth and width. The combinable single-port memory arrays may be operated independently if desired. Alternatively, a pair of the combinable single-port memory arrays can be combined to form a dual-port memory array. When the single-port memory arrays are combined to form a dual-port memory array, circuitry from a first of the combinable single-port memory arrays is used to perform writing operations and circuitry from a second of the combinable single-port memory arrays is used to perform reading operations. The availability of the dual-port memory array capability allows users to implement circuits such as first-in-first-out buffers and other circuits that require the ability to perform concurrent read and write operations.

Abstract: A semiconductor memory device using hierarchical word decoding for word selection includes memory-cell areas, each of which is provided for a corresponding one of column blocks. The semiconductor memory device further includes sub-word lines provided for each one of the column blocks and extending over a corresponding one of the memory-cell areas, and sub-word decoders provided on either side of a given one of the memory-cell areas to select one of the sub-word lines only with respect to the given one of the memory-cell areas.

Abstract: A word line driving circuit drives four word lines in response to a signal supplied from a main row decoder through a main word line and in response to a word line driving voltage supplied from a sub-row decoder. When the word line driving circuit is not selected by the main word line, a first reset circuit allows each word line to be short-circuited. When the word line driving circuit is selected by the main word line, second to fifth reset circuits allow the non-selected word line to bear a ground potential by using a signal of the selected word line.

Abstract: The present invention integrates a WWTM circuit with the write driver circuitry, which is an inherent part of any conventional SRAM design. Thus, a circuit for writing data into and weak write testing a memory cell is provided. In one embodiment, the circuit comprises a write driver that has an output for applying a write or a weak write output signal at the memory cell. The write driver has first and second selectable operating modes. In the first mode, the write driver is set to apply a weak write output signal from the output for performing a weak write test on the cell. In the second mode, the write driver is set to apply a normal write output signal that is sufficiently strong for writing a data value into the cell when it is healthy.

Abstract: A memory device includes a memory array, an external clock terminal, and control logic. The memory array is arranged in rows and columns. The external clock terminal is adapted to receive an external clock signal. The external clock signal has at least a first cycle and a second cycle. The first cycle includes a first edge and the second cycle includes a second edge. The control logic is coupled to the memory array and the external clock terminal and adapted to write to a first plurality of the columns in a specified row during the first and second cycles. The control logic is further adapted to suspend the external clock signal to suppress the second edge of the second cycle while writing to the first plurality of the columns. A method for accessing a memory device arranged in rows and columns is provided. The method includes receiving an external clock signal. The external clock signal has at least a first cycle and a second cycle.

Abstract: A semiconductor memory device includes a memory cell array, a plurality of word lines selectively activated by a row address signal from the outside, a plurality of bit lines selected by a column address signal from the outside, and sense amplifiers connected to the bit lines. The device further includes a row address latch circuit for latching the row address signal by using, as a trigger, a first edge of a clock signal from the outside, a sense amplifier activating circuit for activating the sense amplifier after a lapse of a given time from the first edge, a column address latch circuit for latching a column address signal by using, as a trigger, a second edge of the clock signal occurring after the first edge, and a precharge signal generating circuit for generating a precharge signal for precharging the bit lines after a lapse of a given time from the second edge.

Abstract: A clock pulse generator generates a plurality of clock pulses which has different phases during one cycle of a reference clock signal supplied from the exterior. A timing setting circuit sets a latency, which is a number of clock cycles from a start of a read operation to an output of read data, at a number which is divisible by one n-th (n=2, 3, 4 . . . ) of a cycle of the reference clock signal and outputs latency information according to the set latency. An output controlling pulse switching circuit respectively outputs each of the clock pulses as a predetermined output controlling pulse in accordance with the latency information. In other words, a plurality of the output controlling pulses are switched according to the latency information.

Abstract: A clock control signal and an output enable signal generating circuit of a semiconductor memory device includes a first control signal and clock control signal generating circuit, a second control signal generating circuit a write pass through signal generating circuit for generating a write pass through signal in the read command cycle in case write and read commands are sequentially input in a pipeline operation, a third control signal generating circuit for generating a third control signal for detecting a shift from a low impedance of low level to a high impedance of high level in an operation of double cycle deselect function, and for generating the third control signal in a deselect or write command cycle when read, deselect commands or read, write commands are sequentially input in an operation of single cycle deselect function; and an output enable signal generating circuit to generating an output enable signal in response to an output enable control signal in a flow through operation, for generating

Abstract: A transducer is constructed of a plurality of transducer elements which are arranged in multiple layers and columns forming as a whole a generally cylindrical shape. A scanning sonar employing the transducer thus constructed can be switched between horizontal scan mode in which a vertically focused beam having a narrow horizontal beam angle (high horizontal directivity) is steered around the transducer using all the transducer elements and vertical scan mode in which a horizontally focused beam having a narrow vertical beam angle (high vertical directivity) is steered in a vertical plane directed in a specified scan azimuth to find out the angle of incidence of a received signal. The horizontally focused beam is formed by using the transducer elements of specific columns centered on the specified scan azimuth. A vertical scan signal obtained in the vertical scan mode is multiplied by a chirp signal.

Abstract: A pager which can display base time in the base area of the pager along with displaying corrected local time in an area in which the pager is located is presented. The pager receives a country code and an area code transmitted by a paging system. A system information detection section judges whether or not the received country code and area code are the same as a country code and an area code corresponding to the base area of the pager. If the received country code and area code did not match, the CPU of the pager searches a time difference table for a piece of time difference information, based on the received country code and area code. The CPU judges whether or not the time difference information acquired by the search is the same as time difference information which has been stored in a time difference information memory section.

Abstract: In a method and device for reproducing record information from a magneto-optical recording medium, reproducing light and an alternating magnetic field signal are applied onto the magneto-optical recording medium in order to detect the record information therefrom. Two or more reference values and detected reproducing signal are compared with each other, and based on the comparison, a binary high or a binary low is outputted as a reproduced bit signal. Meanwhile, if the detected reproducing signal signifies an error, a binary signal of a level opposite to a magnetization direction of its applied alternating magnetic field signal is outputted as the reproduced bit signal.

Abstract: An information recording and reproducing method having a track identification function that is suitable for performing an accurate information record and reproduction for a recording medium including user information areas having any ones of land and groove tracks arranged alternately each other and identification areas having at least one pit stream arranged intersectionally each other at each side on the basis of the center line of the tracks and arranged alternately with the user information area. In the method, a first identification information signal for a pit stream recorded on one side and a second identification information signal for a pit stream recorded on the other side, on the basis of any one center line in tracks, are detected.

Abstract: An apparatus and method is provided for use on the pickup head of an optical disc drive for the purpose of adjusting the pickup head to the optimal focus point through a featured tree-structured search algorithm. The apparatus and method can perform the adjustment automatically so as to eliminate the need to use laborious work to make the adjustment in manufacture. The apparatus is activated each time the optical disc drive is started so as to offset the unbalanced condition in the focusing error signal, which allows the optical disc drive to perform the access operation more reliably. Moreover, the apparatus is realized in a digital manner that allows easy implementation and a low manufacturing cost.

Abstract: A gain controlling apparatus is provided with: an adjusting device (6, 7, 8) for adjusting a gain of a generation signal, which is generated on the basis of a light reception signal obtained by receiving a reflection light of a light beam from an information recording medium (1); and a detecting device (21, 14, 16) for detecting whether or not the generation signal is generated and outputting a detection signal when the generation signal is generated. The gain controlling apparatus is also provided with a controlling device (18) for controlling the adjusting device to increase the gain by a predetermined value set in advance when the detection signal is not outputted by the detecting device.

Abstract: A recording/reproducing method and apparatus for an optical recording medium that is adapted to accurately detect a wobbling signal from an optical recording medium having recording tracks defined by wobbled grooves independently of a driving condition of the optical recording medium. In the method, a wobbling signal is picked up from a wobbled part of the recording medium. A frequency of a wobbling signal being picked up from the wobbled part is detected, and a frequency band of filtering means for detecting the wobbling signal from the picked-up signal is controlled in accordance with the detected frequency.

Abstract: A disk reproducing apparatus is provided which can cope with the intermittent access due to track jump in the conventional CD reproducing system and which can reproduce data at N times the normal speed and produce the reproduced data at the normal speed. The disk reproducing apparatus includes a memory for storing the data and time information reproduced from the disk to match with each other, another external memory, a detection circuit detecting the time difference between the finally produced output data and the data which is being accessed, and a control circuit detecting the overflow/underflow of the external memory and controlling it to be written. The construction can absorb the time difference between the system operation speed and data output speed even during an intermittent access so that continuous data can be produced.

Abstract: A playback apparatus for reading a record carrier includes a drive unit for sending out audio sectors that were recorded on the record carrier, an ID extractor for extracting the ID codes of the audio sectors that were sent out by the drive unit, a retrieval controller for receiving the ID codes extracted by the ID extractor, and a sector data extractor for receiving data fields of the audio sectors that were sent out by the drive unit. The sector data extractor is controlled by the retrieval controller to extract the data fields of appropriate ones of the audio sectors when the ID codes thereof are recognized by the retrieval controller as belonging to a selected one of the audio programs.

Abstract: A recording/reproducing method and apparatus that is capable of driving a recording medium of land/groove recording system using a wobbling signal without a land/groove identification information. The method and apparatus detects the wobbling signal from a recording medium having wobbled land and groove tracks and then multiplies a frequency of the wobbling signal. In the method and apparatus, various control are performed on a basis of a period and a phase of the multiplied wobble signal, so that it becomes unnecessary to switch the polarity of the wobbling signal for the land/groove identification.

Abstract: In a data recovery apparatus and method for an optical disk reproduction system, a technique for digital recovery of data from an analog radio frequency (RF) signal is provided. An analog-to-digital converter (ADC) converts an analog radio frequency (RF) signal into a digital signal in response to a reference clock signal. A first adder combines an asymmetry error level to the digital RF signal. An adaptive digital equalizer digitally controls the level of the result added by the first adder, in response to a control signal. A digital level detector calculates the asymmetry error amount using the result added by the first adder, and outputs the control signal according to the output of the adaptive digital equalizer and predetermined coefficients. A viterbi decoder decodes the output of the adaptive digital equalizer into a bit train.

Abstract: The present invention includes a method and apparatus for reducing the width of a mark written in optical media. When forming a long mark, the prior art recording methods typically cause blooming at the edges of the mark, resulting in a wide mark pattern which may be sensed by the read focused spot reading an adjacent track causing increased adjacent track crosstalk (ATC). However, by removing every other pulse from the write pulse waveform, the cooling sequence of the writing process is sufficiently increased to allow for additional cooling between pulses. When forming marks with less pulses, the effects of blooming are substantially reduced. Thus, because of the reduction in the effect of blooming, the problems associated with ATC, whereby adjacent track information is recorded, is substantially reduced.

Abstract: A cluster and a cluster are linked by a link frame. The link area includes postamble, post guard, and a slice/PLL area, as well as a link data area. Substantially the same data as that recorded in clusters is recorded in the link data area. The capacity of a rewritable disc can thus be increased.

Abstract: This invention provides a disc player in which a disc can be taken out readily and without possibility for the disc to fall out when unloading the disc. A Transfer apparatus pushes back a disc located in a playing portion up to a position, at which the center hole of the disc at least partly projects from a disc insertion slot. An elastic holding mechanism elastically holds a portion of the disc, having been pushed back, on the outer side of a recording area from the opposite sides of the disc, thus preventing the falling-out of the disc.

Abstract: A semiconductor laser device includes a semiconductor laser element for emitting laser light onto a recording medium; beam dividing element provided in an optical path between the semiconductor laser element and the recording medium; a hologram optical element including a diffraction grating formed in a light-transmitting substrate, the hologram optical element located in an optical path between the beam dividing element and the semiconductor laser element; a servo-signal light-receiving element provided in an optical path of diffracted light transmitted through the diffraction grating for receiving the diffracted light; an information-signal light-receiving element for receiving light divided by the beam-dividing element, which is different from light divided by the beam-dividing element which is received by the diffraction grating; and a polarizing element provided in an optical path between the beam dividing element and the information-signal light-receiving element, wherein the semiconductor laser element

Abstract: An optical pickup apparatus for performing a reading or recording operation of information on one of different kinds of optical information recording medium, each having a transparent base board in different thickness. The optical pickup apparatus includes: a laser beam generator; a light converging optical system for converging luminous flux from the laser beam generator through the transparent base board onto an information recording surface of the optical information recording medium.

Abstract: A device is described for optically scanning a record carrier with a radiation beam having a high numerical aperture. The radiation beam is focused on the record carrier by means of an objective lens and a plano-convex lens. The plano-convex lens has a gap with the record carrier of several tens of micrometers. It focuses the radiation beam to a point at least 30 focal depths away from an aplanatic point of the plano-convex lens. As a consequence, the lens has a relatively large tolerance for sideways movements.

Abstract: An optical disc is read by being mounted on a turntable which rotates about a vertical axis, and moving an optical pick-up radially relative to the vertical axis. The optical pick-up is slidably mounted on a horizontal guide shaft and is threadedly mounted on a lead screw which is rotatable about a horizontal axis extending parallel to the guide shaft. A first end of the lead screw is connected to a motor, and the second end is mounted in a holder which is displaceable relative to the base to enable the second end to be displaced horizontally, in order to correct the horizontal orientation of the lead screw.

Abstract: In a phase change-type optical recording medium of absorption coefficient control structure used by land/groove recording system, difference in reproduction characteristics between the land and the groove is minimized while ensuring sufficient output of the tracking signal. In the optical recording medium of the present invention, light absorption coefficient at the wavelength of said recording/reproducing beam is such that: Ac/Aa≧0.8 when light absorption coefficient in crystalline region is Ac and light absorption coefficient in amorphous region is Aa; relation between groove width WG and land width WL is such that: 0.97≦2WG/(WL+WG)<1.

Abstract: A structure for protecting the reading area of a compact disc includes a transparent protective film and a two-side-adhesive ring. The protective film has an outer diameter equal to or slightly smaller than the outer diameter of the compact disc, and a center hole with a diameter greater than the protruded ring of the compact disc. The two-side-adhesive ring has an inner diameter equal to or slightly greater than the protruded ring of the compact disc, and an outer diameter greater than the inner diameter thereof by 2-5 mm. The structure is applied by an applicator to the compact disc such that the protective film is attached to the reading area of the compact disc by static attraction, and further that the inner annular portion of the protective film is held by the two-side-adhesive ring adhering to the annular portion surrounding the protruded ring of the compact disc.

Abstract: A medium access contention protocol that is highly beneficial in wireless networks and particularly in wireless networks that employ a fixed minimum burst size such as OFDM wireless networks. In one embodiment, a MAC protocol is a demand-assigned protocol that maximizes utilization of the bus medium (the allocated frequency spectrum.) Each data communication device (DCD) in the network communicates with a central access point (AP). Multiple DCDs may request access from the AP in the same request access (RA) burst. Each of the multiple DCDs transmits its access request to the AP within a frequency domain channel in the RA burst that is orthogonal to the frequency domain channels used by the other DCDs requesting access. Each DCD includes channel training information in the access request burst to allow the AP and/or DCD to adapt to rapid variations in channel characteristics.