Abstract: A device comprises a solid support and multiple immobilized agents for protein detection is described. The immobilized agents are mainly proteins, such as antibodies and recombinant proteins. The immobilized agents can be synthesized peptides or other small chemicals. Agents are individually deposited in a predetermined order, so that each of the agents can be identified by the specific position it occupies on the support. The immobilized agents on the solid support retain their protein binding capability and specificity. Methods employing the device are extremely powerful in screening protein expression patterns, protein posttranslational modifications and protein—protein interactions.

Abstract: A ferroelectric thin film includes: a bismuth oxide polycrystal thin film constituting a buffer layer, and a bismuth-based layered compound thin film represented by the formula: Bi2Am-1BmO3m+3 wherein A is an atom selected from the group consisting of Na, K, Pb, Ca, Sr, Ba and Bi; B is an atom selected from the group consisting of Fe, Ti, Nb, Ta, W and Mo; and m is an integer of 1 or more. The bismuth oxide polycrystal thin film and the bismuth-based layered compound thin film are formed into a single-phase.

Abstract: In a semiconductor manufacturing apparatus, a semiconductor substrate ion-implanted with an ion species is heated and thereby raised in temperature under vacuum. At this time, a partial pressure of a gas released from the semiconductor substrate is measured by a quadrupole mass spectrometer. Further, a change in partial pressure with time is observed and compared with a pre-measured release characteristic, whereby the temperature of the semiconductor substrate is corrected.

Abstract: A method to obtain the same effect as that of burning in at an operating frequency of a high-frequency transistor by burning in at a frequency lower than the operating frequency. Burn-in is carried out using a frequency lower than the operating frequency of the transistor and higher than the response frequency of impurities included in the transistor.

Abstract: Dispersion of a load may be kept within a predetermined allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane against a wafer by applying a pressure load to a plurality of places on a plane of the pressure members on the side opposite the wafer in a probe test step, burn-in test step which represent typical semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit at the same time.

Abstract: A system and method of controlling multi-process, multi-product semiconductor fabrication tools. Individual, grouped, or composite controllers are designated to control various tool operations. First control parameters for a fabrication tool process are generated, where the first control parameters are based on first tool operation attributes. Second control parameters for the process are generated based on second tool operation attributes. The fabrication tool is then controlled by generating cooperative control parameters which are a function of the first and second control parameters. Disturbance information can be shared between controllers for use in generating the first and second control parameters while taking into account disturbance information already discovered and quantified.

Abstract: A method and device for testing and manufacturing integrated circuits such as microprocessors, memories, ASICs, programmable logic, and other types of integrated circuits. A test system is designed to test the relevant integrated circuit. A device under test emulator responds to the test system. If modifications are needed, the test system can be modified, and used to test actual devices.

Abstract: The depth of a denuded layer with respect to a relatively defective bulk region of a monocrystalline semiconductor wafer is estimated in a nondestructive way. The depth is determined by measuring the lifetime or diffusion length of injected excess minority charge carriers on a surface of the wafer having such a denuded layer and on a different portion of the surface of the wafer from where the denuded layer has been previously stripped-off by lapping and/or etching. The depth is calculated through a best-fit procedure or through numerical processing of the measurement results on the basis of the diffusion equations of excess minority carriers.

Abstract: A method of fabricating a field emission array to facilitate optimization of the size of grid openings. The method also minimizes the occurrence of electrical shorts between the cathode and anode grid of the field emission array. In the method of the present invention, a first layer of dielectric material is disposed over a substrate and emitter tips of the field emission array. A second layer is disposed over the first layer and subsequently planarized to expose regions of the first layer that are located above the emitter tips. Dielectric material of the first layer may be removed through openings of the second layer to expose a top portion of each of the emitter tips. The second layer is then substantially removed from the first layer. Planarization and removal of the second layer may reduce any conductive defects that extend through the first layer. A third layer, which comprises dielectric material, is disposed over the first layer.

Abstract: A mask for forming a selective grating and selective area growth and a method for fabricating an electro-absorption modulated laser device by utilizing the mask are disclosed. The mask for forming the selective grating and the selective area growth comprises a + shaped island type pattern and a stripe type pattern to allow, during the formation of the selective grating, the selective grating to be formed only in a laser diode region, and to allow, during the selective area epitaxial growth, the selective area growth to be carried out only with the stripe pattern in the diode laser region after the island pattern being removed.

Abstract: Semiconductor layers forming a light emitting layer and including an n-type layer and p-type layer are formed onto a substrate, then the n-type layer is exposed by removing a part of the laminated semiconductor layers. p-side electrode and n-side electrode are then respectively formed on the p-type layer on the surface of the laminated semiconductor layers and the exposed n-type layer, respectively in an electrically connected manner, followed by dicing of the substrate from the exposed n-type layer to the substrate at portions at which breaking of the substrate is performed. Then a protection film is provided on the entire surface of the laminated semiconductor layers as to expose the p-side and n-side electrodes, and breaking of the substrate is performed at dicing portions into individual chips. Consequently, semiconductor light emitting devices can be obtained by breaking the wafer into individual chips without etching the protection film and without damaging the protection film at the time of breaking.

Abstract: A method and system for making small gaps in a MEMS device is disclosed. The MEMS device is first made with a sacrificial layer where the gap is to reside. The device can then be assembled, including forming a protective coat surrounding the device. Once the protective coat is formed, small holes in the protective coat can be made to expose the sacrificial layer to an external environment. The holes can be formed using laser ablation. After the small holes have been made, an etchant can then be applied through the holes to remove the sacrificial layer.

Abstract: The present invention provides a method for producing a solar cell comprising the step of immersing a silicon substrate in an etching solution which includes an aqueous sodium carbonate (Na2CO3) solution, optionally an aqueous sodium hydroxide (NaOH) solution and/or an aqueous sodium bicarbonate (NaHCO3) solution to form minute concave and convex patterns on the surface of the silicon substrate. This method allows quite uniform textures to be formed on the crystal faces while avoiding the problem of disposal of isopropyl.

Abstract: In a semiconductor chip mounting apparatus including a mounting section for mounting a semiconductor chip on a substrate, a loader which supplies the substrate to the mounting section, an unloader which contains the substrate having the semiconductor chip mounted thereon into a magazine, the substrate having the semiconductor chip is heated by a heater to be kept at high temperature after the mounting process and until a sealing process for sealing the substrate having the mounted semiconductor chip with a resin.

Abstract: The present invention discloses a method for forming a wafer level package by first providing a silicon wafer that has a multiplicity of IC dies formed on a top surface, each of the IC dies has at least one peripheral I/O pad formed in an insulating layer, then forming at least one via plug of a conductive metal with a top surface exposed on the at least one peripheral I/O pad, then coating a layer of an insulating material that has sufficient elasticity on the surface of the wafer prior to the deposition and forming of a metal trace on the elastic material layer, at least one area array I/O pad is then formed at an opposite end of the metal trace with a solder bump formed on the I/O pad before they are reflowed into a solder ball. The elastic material layer deposited under the metal traces acts as a stress-buffing layer such that an IC circuit of high reliability can be produced on a wafer level for the low cost fabrication of IC assembly.

Abstract: A new method is provided for packaging high-density IC semiconductor devices. A metal substrate is provided, a layer of dielectric is deposited over the first surface of the metal panel. One or more interconnect layers are then created on top of the dielectric layer, the interconnect layers, which can be thin film interconnect layers, are patterned using maskless exposure equipment. One or more cavities are created in the second surface of the metal panel; openings through the layer of dielectric are created where the layer of dielectric is exposed in the openings in the metal substrate thereby providing points of electrical contact to the second surface of the interconnect substrate. Holes are created in the first surface of the interconnect substrate thereby providing points of electrical contact to the first surface of the interconnect substrate. Bare semiconductor devices and/or packaged semiconductor devices can be attached on one or both sides of the interconnect substrate.

Abstract: A lead frame for manufacturing semiconductor device packages has inner leads, tie bars and a die pad that are formed with irregular dimples on their respective upper and lower surfaces. This improves the bonding strength between the lead frame and the molding compound as well as between the die pad and a semiconductor device. The dimples are formed during the manufacture of the lead frame which allows the lead frame to be economically and easily manufactured.

Abstract: An object of the present invention is to provide a method of fabricating a semiconductor device having a relatively small package structure and hence a relatively small mounting area. An insulating board with a plurality of device carrier areas thereon is prepared, and semiconductor chips are mounted on the respective device carrier areas and then covered with a common resin layer. The resin layer and said insulating board are separated along dicing lines into segments including the device carrier areas thereby to produce individual semiconductor devices. External electrodes connected to electrodes of the semiconductor chips are mounted on the back of the insulating board. The external electrodes are positioned symmetrically with respect to central lines of the packaged semiconductor device for preventing various problems which would otherwise be caused when such a small package is mounted.

Abstract: In a semiconductor device including a substrate which has a primary surface, a conduction wire formed on the primary surface, a semiconductor element which has a secondary surface, a projective electrode formed on the secondary surface, an insulative resin for adhesion which is applied between the primary surface and the secondary surface and which shrinks by hardening thereof, the substrate and the semiconductor element are adhered to each other by the hardening of the insulative resin with the projective electrode and the conduction wire corresponding with each other, so that an electrical connection between the projective electrode and the conduction wire is achieved and that a residual stress is generated in the insulative resin. The residual stress has a maximum value thereof around the projective electrode.

Abstract: A temporary self-adherence of the individual components in a stack of semiconductor components is accomplished by the use of adhesive bodies either separate from the solder preforms used in the stack or included within the solder in the form of a tacky paste. The adhesive bodies may comprise relatively high-purity water, and adhesion of the adjoining parts is achieved by the surface tension of the water. During a single heating step, preferably performed in a protective, non-oxidizing atmosphere, the water is completely evaporated while the solder preforms are heated to form the desired solder joints.

Abstract: A structure and methods for reinforcing a semiconductor device to prevent cracking is provided. The device may take the form of a semiconductor chip or a semiconductor chip package. When a semiconductor chip is provided, an adhesion layer is applied over its top surface, followed by the application of a reinforcing layer over the adhesion layer. When a semiconductor chip package is provided, the package first undergoes a cleaning process, followed by the application of an adhesion layer over its top surface and, lastly, the application of a reinforcing layer over the adhesion layer.

Abstract: A system and method for forming a memory having at least 16 megabits (224 bits) and only a single deposition layer of highly conductive interconnects. The resulting semiconductor die or chip fits within existing industry-standard packages with little or no speed loss over previous double metal deposition layered DRAM physical architectures. This is accomplished using a die orientation that allows for a fast single metal speed path. The architecture can be easily replicated to provide larger size memory devices. In addition, a method is described for reducing parasitic resistance in an n-sense amplifier.

Abstract: An integrated circuit includes a substrate with doped regions, a patterned polysilicon layer defining contacts and local interconnects, a submetal dielectric, a two-metal layer metal interconnect structure with an intermetal dielectric layer, and a passivation layer. Like the dielectric layers, the passivation layer is optically transparent, thick, and planarized. Because of this, laser energy can be directed through the passivation layer to fuse two conductors of the top metal layer without delaminating the passivation layer. In addition, laser energy is directed through the passivation layer and the intermetal dielectric to fuse pairs of conductors in the lower metal layer. Thus, the present invention provides for reliable convenient circuit modification without disturbing dielectric and exposing metal features to moisture and other contaminants.

Abstract: The present invention provides a structure of a metal-insulator-semiconductor (MIS)-like multiple-negative-differential-resistance (MNDR) device and the fabrication method thereof. The device of the present invention has the characteristics of dual-route and MNDR at low temperatures. These characteristics result from the successive barrier-lowering and potential-redistribution effect when conducting carriers fall into a quantum well. MNDR devices have excellent potential in multiple-value logic circuitry applications and are capable of reducing circuitry complexity.

Abstract: A method for crystallizing an amorphous silicon thin-film is provided, in which amorphous silicon thin-films on a large-area glass substrate for use in a TFT-LCD (TFT-Liquid Crystal Display) are crystallized uniformly and quickly by a scanning method using a linear lamp to prevent deforming of the glass substrate. The crystallization method includes the steps of forming an amorphous silicon thin-film on a glass substrate, and illuminating a linear light beam on the amorphous silicon thin-film from the upper portion of the glass substrate according to a scanning method. The crystallization method is applied to a polycrystalline silicon thin-film transistor manufacturing method including the steps of forming an amorphous silicon thin-film on a glass substrate, and crystallizing the amorphous silicon of the thin-film transistor according to a scanning method using a linear light beam.

Abstract: This invention is related to a method for controlling a threshold voltage of a bottom gate type thin film transistor as follows. Gate electrodes and a gate insulating film are formed on a glass substrate. An amorphous silicon film is formed thereon and then crystallized into a crystalline silicon film. After a buffer layer is formed thereon, an impurity element (selected from Group 13 or Group 15 elements) for a threshold voltage control is added to the crystalline silicon film by ion implantation or ion doping.

Abstract: A method of fabricating a thin film transistor having a vertical offset layer which prevents the damage on an active layer due to the etching plasma by preserving the vertical offset layer during an etching process for separating an ohmic contact layer.

Abstract: A TFT having stable characteristics is obtained by using a crystal silicon film obtained by crystallizing an amorphous silicon film by using nickel. Phosphorus ions are implanted to regions 111 and 112 by using a mask 109. Then, a heat treatment is performed to getter nickel existing in a region 113 to the regions 111 and 112. Then, the mask 109 is side-etched to obtain a pattern 115. Then, the regions 111 and 112 are removed by utilizing the pattern 115 and to pattern the region 113. Thus, a region 116 from which nickel element has been removed is obtained. The TFT is fabricated by using the region 116 as an active layer.

Abstract: A MOS device comprises a p-channel semiconductor device and n-channel semiconductor device, which are formed on top of an SOI substrate consisting of a supporting substrate, an insulation film, and a semiconductor layer patterned in a plurality of islands. In the peripheral region of respective islands of the semiconductor layer, boundary films, thicker than respective gate oxide films, are formed, and a boundary film formed on the semiconductor layer for the n-channel semiconductor device is thinner than another boundary film formed on the semiconductor layer for the p-channel semiconductor device. A field doped layer 11 may be preferably provided in the peripheral region of the semiconductor layer of the n-channel semiconductor device 41. In the MOS device fabricated as above, leakage current that occurs in a parasitic MOS region in an environment under exposure to radiation is reduced, ensuring stable operation.

Abstract: A method for use in the fabrication of integrated circuits includes providing a substrate assembly having a surface. A diffusion barrier layer is formed over at least a portion of the surface. The diffusion barrier layer is formed of RuSix, where x is in the range of about 0.01 to about 10. The barrier layer may be formed by depositing RuSix, by chemical vapor deposition or the barrier layer may be formed by forming a layer of ruthenium relative to a silicon containing region and performing an anneal to form RuSix from the layer of ruthenium and the silicon containing region. Capacitor electrodes, interconnects or other structures may be formed with such a diffusion barrier layer.

Abstract: A semiconductor fabrication method is provided for the fabrication of a polysilicon-based load circuit (called poly-load) for SRAM (static random-access memory). In accordance with this method, a lightly doped polysilicon layer is formed. This lightly doped polysilicon layer is doped with an impurity element to a predetermined concentration corresponding to the desired resistive characteristic of the poly-load. Further, this lightly-doped polysilicon layer is partitioned into two parts: a first part to be formed into the desired poly-load and a second part to be formed into a conductive interconnecting line that is electrically connected to the poly-load. After this, a metal silicide layer is formed over the second part of the lightly doped polysilicon layer to serve as the conductive interconnecting line. Next, an ILD (Inter Layer Dielectric) layer is formed over the poly-load and the conductive interconnecting line, and then the ILD layer is subjected to a densification process.

Abstract: A method of fabricating a narrow bit line structure is disclosed. The fabrication includes the steps as follows. At first, the interpoly dielectric layer is formed over the MOSFET. Then the landing pad is formed in the interpoly dielectric layer. Afterwards, the first polysilicon layer, the tungsten silicide layer, the silicon-oxy-nitride layer, and the second polysilicon layer is continuously formed over the interpoly dielectric layer. The defined photoresist layer is formed on the second polysilicon layer. A portion of the second polysilicon layer is etched, using the defined photoresist layer as a mask. Afterwards, the defined photoresist layer is removed. The polysilicon spacer is formed in the second polysilicon layer sidewall. The silicon oxide layer is deposited over the second polysilicon layer. Next, the silicon oxide layer is etched back to expose the second polysilicon layer.

Abstract: In a fabricating method of a semiconductor storage device, a ferroelectric film is formed on a lower electrode, and crystallized. Thereafter, a heat treatment is performed in an atmosphere of hydrogen or a mixture of hydrogen and an inert gas to vanish a defect at the interface between the gate insulating film of a MOS transistor and a silicon substrate. Next, an upper electrode is formed on the ferroelectric film.

Abstract: This invention relates to integrated circuit product and processes. More particularly, the invention relates to high performance Dynamic Random Access Memory (DRAM) chips and processes for making such chips. An IC fabrication is provided, according to an aspect of the invention, including a silicon wafer, a DRAM array fabrication disposed on said silicon wafer having a first multitude of gate sidewall oxides, and a logic support device fabrication disposed on said wafer adjacent said DRAM array fabrication and having a second multitude of gate sidewall oxides, said first multitude of gate sidewall oxides being substantially thicker than said second multitude of gate sidewall oxides. Methods of making IC fabrications according to the invention are also provided.

Abstract: A method for producing a memory configuration that comprises a multiplicity of memory cells, and has storage capacitors whose first electrodes are configured in plate form in a parallel manner one above the other. These electrodes are in electrical contact with selection transistors of the memory cell through contact plugs having different lengths. The first electrodes preferably extend beyond the cell area of one memory cell.

Abstract: Thin film metal-insulator-metal capacitors having enhanced surface area are formed by a substituting metal for silicon in a preformed electrode geometry. The resulting metal structures are advantageous for high-density DRAM applications since they have good conductivity, enhanced surface area and are compatible with capacitor dielectric materials having high dielectric constant.

Abstract: Improved dimensional accuracy of the gate electrode structure in the peripheral circuitry region of a semiconductor device is achieved by avoiding ARC loss during photoresist stripping associated with plural maskings in the core memory cell region during patterning and ion implantations. Processing is simplified by employing the same mask in the memory cell region for patterning the stacked gate electrode structure and for ion implanting the shallow source/drain extensions. Embodiments include initially etching to form the gate electrode structure in the peripheral circuitry region. Subsequently, processing in the core memory cell region is conducted by etching the stacked gate electrode structure and ion implanting to form the source/drains with attendant stripping of photoresist layers.

Abstract: An electrically erasable programmable read-only memory device comprises a substrate having an active region, a field isolation region for isolating the active region, and extension areas integrally extended and interconnected at portions of the active region in the neighborhood of a tunnel region to enlarge an overlap margin between the active region and tunnel region. A tunnel ion implanted region is formed in a portion of the active region including the tunnel region and a tunnel dielectric film is formed on a portion of the active region corresponding to the tunnel region. A gate dielectric film is formed on the remaining portion of the active region except for the portion corresponding to the tunnel region. A floating gate is formed in common on the tunnel region and active region and a control gate is formed on the floating gate via an insulating film. A selection gate is formed on the gate dielectric film at a predetermined distance from the control gate.

Abstract: A method for fabricating a non-volatile memory cell for a substrate includes the following steps: forming an isolation structure to define an active region on the substrate; forming a channel oxide layer on the active region; forming a conducting layer and a silicon nitride layer over the substrate; defining the polysilicon layer and the silicon nitride layer to form a floating gate on the active region and to form an opening exposing a portion of the isolation structure; conformally forming an etching protection layer which extends from the isolation structure inside the opening up to the silicon nitride layer; forming an oxide layer over the substrate; planarizing the oxide layer to the surface of the silicon nitride layer so that the remainder of the oxide layer is left within the opening; removing the silicon nitride layer; forming conducting spacers on the sidewalls of the remainder of the oxide layer; removing the remainder of the TEOS oxide layer; conformally forming an ONO layer; forming a controlling

Abstract: A method of providing oxide layers at the surface of the semiconductor substrate suitable for use with the formation of programmable logic devices. The method comprises the steps of: depositing a layer of nitride on the surface of the semiconductor substrate; etching a first and second portions of the nitride layer; forming a first and second regions of a first oxide layer on the substrate in the first and second etched portions of the nitride layer; etching a the first region of the oxide; forming a second oxide layer on the substrate having a first portion in the first etched portion of the nitride and a second portion overlying the first portion of the second region of the first oxide layer; removing the nitride layer; and forming a third layer of oxide having a first portion on the surface of the substrate, a second and third portions on the first and second portions of the second oxide layer.

Abstract: An improved method for fabricating a NOR flash memory device having a cell array region and a periphery region near the cell array region is disclosed. The bit line contact regions of the cell array region are formed independently, using a different mask, from the word line contact regions of the cell array region, and the active contact region and the gate contact region of the periphery region, thereby allowing stable formation of all contact regions without etching damage. Also, plug ions are implanted into the bit line contact region of the cell array region, and a metal plug is formed in the bit line contact region and the word line contact region of the cell array region, and the active contact region and the gate contact region of the periphery region.

Abstract: A method of manufacturing a semiconductor component includes providing a semiconductor substrate (200) having top and bottom surfaces, forming a drain electrode (160) at the bottom surface of the semiconductor substrate (200), and simultaneously forming source and gate electrodes (251, 254, 255, 253) at the first surface of the semiconductor substrate (200).

Abstract: A process for fabricating a vertical MOSFET device for use in integrated circuits is disclosed. In the process, at least three layers of material are formed sequentially on a semiconductor substrate. The three layers are arranged such that the second layer is interposed between the first and third layers. The second layer is sacrificial, that is, the layer is completely removed during subsequent processing. The thickness of the second layer defines the physical gate length of the vertical MOSFET. In the process the first and third layers have etch rates that are significantly lower than the etch rate of the second layer in an etchant selected to remove the second layer. The top layer, which is either the third or subsequent layer, is a stop layer for a subsequently performed mechanical polishing step that is used to remove materials formed over the at least three layers. After the at least three layers of material are formed on the substrate, a window or trench is formed in the layers.

Abstract: A method for manufacturing a gate terminal comprising the steps of providing a substrate, then forming and patterning an oxide layer to form a gate region. Next, a gate oxide layer and a crystalline silicon layer are formed in the gate region. This is followed by depositing a tungsten layer in the gate region, and then polishing the tungsten layer to form a final tungsten layer functioning as the gate electrode. Finally, the oxide layer is removed. The method of this invention is able to control the dimensions of the gate terminal produced. Moreover, the formation of a thin crystalline silicon layer over the gate oxide layer helps to increase the bonding strength with the metallic layer, and that the gate electrode can be formed at a lower processing temperature. Therefore, the gate so formed has a higher quality and the processing of the semiconductor is much easier. Furthermore, the silicon nitride layer can serve as an etching stop layer during the etching operation of the oxide layer.

Abstract: The level converting circuit includes a first current cutting circuit, a second current cutting circuit, a level shift circuit and an inverter. The first current cutting circuit includes two PMOS transistors connected to a node having a boosted potential Vpp. The second current cutting circuit includes two NMOS transistor connected to a ground node. The level shift circuits include two PMOS transistors and two NMOS transistors. Before a through current flows between the node having the boosted potential Vpp and the ground node, any of the transistor included in the first current cutting circuit and any of the transistors included in the second current cutting circuits are turned off. Therefore, through current between the node having the boosted potential Vbb and the ground node can be prevented.

Abstract: In an integrated circuit, a pair of IGFET devices can be formed with reduced dimensions without requiring the use of higher resolution optical masks. A gate electrode is formed with a layer of silicon nitride and a photoresist layer formed thereon. The dimensions of the photoresist layer are reduced by a trim etch and the dimension of the nitride layer reduced by a nitride etch. After removing the photoresist layer, a silicon oxide layer is grown over the exposed gate electrode and substrate. The nitride layer is removed leaving a pattern in the silicon oxide layer. An anisotropic etch guided by the pattern in the silicon oxide layer divides the gate electrode into two portions with an aperture therebetween. By proper doping, a IGFET structure can be formed that has two IGFET devices having a shared source/drain region and occupying the same area on the surface of the substrate as a single IGFET device previously occupied.

Abstract: An IGFET with elevated source and drain regions in close proximity to a gate with sloped sidewalls is disclosed. A method of making the IGFET includes forming a lower gate level over a semiconductor substrate, wherein the lower gate level includes a top surface, a bottom surface and sloped opposing sidewalls, and the top surface has a substantially greater length than the bottom surface, and depositing a semiconducting layer on the lower gate level and on underlying source and drain regions of the semiconductor substrate to form an upper gate level on the lower gate level, an elevated source region on the underlying source region, and an elevated drain region on the underlying drain region. The elevated source and drain regions are separated from the lower gate level due to a retrograde slope of the sidewalls of the lower gate level, and the elevated source and drain regions are separated from the upper gate level due to a lack of step coverage in the semiconducting layer.

Abstract: A method of manufacturing a semiconductor device with a silicide electrode is provided which can form a good contact even at a scaled-down pattern. The method includes the steps of: forming an insulated gate structure with side wall spacer on a p-type region of a silicon (Si) substrate; implanting arsenic ions in source/drain regions at a dose less than 5×1015 cm−2; forming a laminated layer of a Co film and a TiN film on the surface of the substrate; heating the substrate to let the Co film react with an underlying Si region for silicidation; and removing the TiN film.

Abstract: A semiconductor process in which a low temperature oxidation of a semiconductor substrate upper surface followed by an in situ deposition of polysilicon are used to create a thin oxide MOS structure. Preliminarily, the upper surface of a semiconductor substrate is cleaned, preferably with a standard RCA clean procedure. A gate dielectric layer is then formed on the upper surface of the substrate. A first polysilicon layer is then in situ deposited on the gate dielectric layer. An upper portion of the first polysilicon layer is then oxidized and the oxidized portion is thereafter removed from the upper surface of the first polysilicon layer. A second polysilicon layer is subsequently deposited upon the first polysilicon layer. Preferably, the formation of the gate dielectric on the semiconductor substrate upper surface comprises annealing the semiconductor substrate in an ambient comprising an inert species and O2.

Abstract: A gate electrode is formed in an element region of a semiconductor substrate. By ion implantation using the gate electrode as the mask, a low density doping (LDD) region is formed. By ion implantation after forming a side wall insulating film on the side wall of the gate electrode, source and drain regions are formed. Afterwards, by varying the thickness of the side wall insulating film of the side wall of the gate electrode, that is, by reducing the thickness of the side wall insulating film, a sufficient silicide region is formed on the source and drain regions. A silicide layer is formed on the gate electrode and source and drain regions by thermal reaction between a refractory metal and silicon in the gate electrode or in the semi-conductor substrate.