Abstract: A quantum well infrared photodetector includes a direct connection between the charge well and detector that induces a nonlinear dynamic bias. This dynamic bias advantageously corrects for nonuniformity in the conductance of the detector. In another feature, the charge well is fabricated on the detector element by adding an extra contact layer and a dielectric layer to a standard quantum well. Very dense focal plane arrays can be produced by making the charge well a part of the infrared detector.

Abstract: Apparatus for inspecting a container having an open mouth and a closed bottom spaced from the container mouth, while the container is hot from its manufacture, includes a light sensor disposed with respect to the container to view the container bottom through the container mouth. Infrared light energy emitted from the container bottom that travels through the container mouth is directed onto the light sensor, and the inside diameter of the container mouth is measured as a function of the light energy directed onto the sensor. The light sensor preferably comprises an area array sensor for developing a two-dimensional image of the container mouth, and the infrared light energy is directed onto the sensor by a telecentric lens arrangement. The area array sensor is disposed within a camera that has an entrance pupil and the telecentric lens arrangement has one focus at infinity directed toward the container bottom and a second focus at the entrance pupil of the camera.

Abstract: A nuclear level sensing gauge for measuring the level of product in a bin utilizes a bundle of scintillating fibers. A source of nuclear radiation positioned adjacent the bin, and a bundle of one or more scintillating fibers is positioned adjacent the bin opposite the source of nuclear radiation such that nuclear radiation passing through the bin impinges upon the bundle. Circuitry detects scintillating photons generated in the fibers, which are indicative of radiation passing through the bin. The number of photons generated in the fibers is representative of the level of radiation-absorbing product in the bin.

Abstract: A technique for correcting for random coincidences in a gamma camera system is provided. The system includes a pair of scintillation detectors coupled to a processing system and is configured to detect radiation coincidences. Each detector generates trigger pulses in response to scintillation events to generate a plurality of event-based trigger pulses. Each detector includes a pulse generator, which generates a plurality of artificial trigger pulses. When an artificial trigger pulse in one detector occurs in coincidence with an event-based trigger pulse in the other detector, data is registered by the corresponding detectors, and the artificial trigger pulse is associated with a predetermined energy level. The data processing system examines the data to identify singles events that were registered as a result of artificial trigger pulses and prevents such singles events from contributing to the coincidence images. Instead, such singles events are used to generate a singles image for each detector.

Abstract: An ionization gauge including a source of electrons; an open anode defining an anode volume, where the source of electrons is disposed outside the anode volume; a plurality of ion collector electrodes disposed within the anode volume; a plurality of axially extending anode support posts for supporting the open anode, the anode support posts being electrically connected to the open anode; and the plurality of ion collector electrodes being respectively located sufficiently close to the plurality of axially extending anode support posts so as to substantially repel the electrons from the anode support posts.

Abstract: A flexible container is provided for the storage and mixing together of diluents and medicaments. The container incorporates multiple compartments, separated by peelable seals, in which the diluents and medicaments are stored. The container is constructed of thermoplastic materials having high oxygen and moisture barrier properties which allows the container to be stored for extended periods of time without degrading the contents. The seals are ruptured by manipulation of the container to thereby mix the contents together for delivery through standard IV arrangement to a patient. The seals are constructed to provide a non-linear resistance characteristic to hydraulic pressure, which causes the seal to peel open completely along its length. The container also includes a locking tab and retaining slot to secure the bag in a folded-over condition.

Abstract: Systems, devices and methods are provided for viewing a pattern of fluorophors capable of fluorescing when exposed to visible light, e.g., fluorescently stained DNA, protein or other biological material. The system includes a light source emitting light in the visible spectrum, such as a fluorescent lamp used in domestic lighting, a first optical filter capable of transmitting light from the source at wavelengths capable of exciting the fluorophors and of absorbing light of other wavelengths, and a second optical filter capable of blocking substantially all the light from the source not blocked by the first filter, so that the only light reaching the viewer is light produced by fluorescence of the fluorophors.

Abstract: A dosimeter device that is fabricated from a flat member separated into panels along fold lines. In an illustrated embodiment, a first panel has two attenuators thereon, a first attenuator formed of a first material and a second attenuator formed of a second material. The first panel also has a window or opening formed thereon. A second panel also has two attenuators thereon, a third attenuator formed of the same material as the first attenuator on the first panel and a fourth attenuator formed of the same material as the second attenuator on the first panel. The second panel is separated from the first panel by a fold line, and the second panel also has a window or opening formed thereon. A third panel is separated from the second panel by a second fold line, and has a radiation sensitive member thereon.

Abstract: There is provided an apparatus used for forming a pattern on a substrate by photolithography with electron beams, the apparatus including (a) an aperture formed with at least one opening through which electron beams are to pass, and (b) a holder for fixedly supporting the aperture therewith by means an adhesive, at least one of surfaces of the aperture and the holder at which the aperture is adhesively fixed to the holder, being formed with at least one groove for excessive portion of the adhesive to flow in. When an aperture is fixed onto a holder with an adhesive, an adhesive may be excessively applied on a surface of the aperture or holder. However, in accordance with the above-mentioned apparatus, since excessive adhesive is pooled in the groove, it is possible to avoid the excessive adhesive from being forced out to the opening of the aperture, and thus, it is possible to avoid forming an incorrect pattern on a photoresist film.

Abstract: This invention describes a method by which microparticles, typically in the size range from 0.3 &mgr;m to 100 &mgr;m, which are carried in a fluid suspension, may be rapidly detected and characterized. The method primarily relates to the measurement of atmospheric particles such as those in clouds or environmental aerosols, but it may be used to measure other forms of particulate suspension wherever the flow of suspension through a defined measurement space can be achieved. The method is based upon a rapid analysis of the spatial laser scattering profile (i.e., the complex manner in which individual particles scatter laser light) recorded from individual particles as they are carried in suspension through a measurement space. Using this method it is possible to differentiate various types of particles based on particle shape and structure, as manifest in characteristics of their individual spatial light scattering patterns.

Abstract: A system is provided for scanning an object, the system comprising: a drive shaft having a proximal portion and a longitudinal axis; a motor including a motor shaft having a rotational axis, the motor serving to rotate the motor shaft about the rotational axis; a flexible joint coupling the drive shaft to the motor shaft by the proximal portion of the drive shaft, the flexible joint having a range of motion which allows the longitudinal axis of the drive shaft to move relative to the rotational axis of the motor shaft; and an object attached to the drive shaft which is movable along the longitudinal axis of the drive shaft in response to the drive shaft being rotated by the motor. This system may be used in a drum scanner system and may be used to read storage layer radiation screens.

Abstract: The present invention provides a III-V compound semiconductor having a laminated superlattice structure in which a first monoatomic layer and a second monoatomic layer are regularly laminated, the first monoatomic layer being formed by laminating 1 atomic layer of a group III atom selected from Al, Ga and In and 1 atomic layer of a group V atom selected from P, As and Sb, the second monoatomic layer being formed by laminating 1 atomic layer of the group III atom and 1 atomic layer of a nitrogen atom, and a semiconductor device using the same.

Abstract: A transistor operated by changing the electrostatic potential of an island disposed between two tunnel junctions. The transistor has an island of material which has a band gap (e.g. semiconductor material). Source and drain contacts are provided. The transistor has a first tunnel junction barrier disposed between island and source, and a second tunnel junction barrier disposed between island and drain. The island is Ohmically isolated from other parts of the transistor as well as a substrate. A gate electrode is capacitively coupled to the island so that a voltage applied to the gate can change the potential of the island. The transistor has n- and p-type embodiments. In operation, applying a gate voltage lowers (e.g., for positive gate bias) or raises (e.g., for negative gate bias) the conduction band and valence band of the island. When the conduction band or valence band aligns with the Fermi energy of the source and drain, tunneling current can pass between the source, island and drain.

Abstract: A field-effect transistor and a method for its fabrication are described. The transistor includes a monocrystalline channel region extending from a monocrystalline body region of a semiconductor substrate. First and second source/drain regions laterally adjoin opposite sides of the channel region and are electrically isolated from the body region by an underlying first dielectric layer. The source/drain regions include both polycrystalline and monocrystalline semiconductor regions. A conductive gate electrode is formed over a second dielectric layer overlying the channel region. The transistor is formed by selectively oxidizing portions of a monocrystalline semiconductor substrate and then removing portions of the oxidized substrate. The resulting structure includes a body region of the substrate having overlying first and second oxide regions, with a protruding channel region extending from the body region between the oxide regions.

Abstract: The boundary between the P type silicon base and N+ buffer layer of an IGBT is intentionally damaged, as by a germanium implant, to create well defined and located damage sites for reducing lifetime in the silicon.

Abstract: A method for fabricating a periodic table group III-IV metal semiconductor metal field-effect enhancement mode complementary transistor pair device is described, a device typically made of gallium arsenide materials. The disclosed fabrication uses initially undoped semiconductor materials, single metallization for ohmic and Schottky barrier contacts, employs a non-alloyed ohmic contact semiconductor layer and includes an inorganic dielectric material layer providing non photosensitive masking at plural points in the fabrication sequence. The invention uses selective ion implantations, and a combined optical and electron beam lithographic process, the latter in small dimension gate areas. These attributes are combined to provide a field-effect transistor complementary pair of reduced fabrication cost, low electrical energy operating requirements increased dimensional accuracy and current state of the art electrical performance. Fabricated device characteristics are also disclosed.

Abstract: A transistor formed in a master slice manner is disclosed for use in radio frequency range, the transistor includes a main transistor cell operating as a smallest transistor in scale among a product group of transistors, and sub-transistor cells are arranged at symmetrical positions with the main transistor cell as the center. The sub-transistor cells are connected in common or not to the main transistor in a master slice manner in accordance with the required characteristics.

Abstract: A distributed photodiode structure is shown having a plurality of diffusions formed in a uniform pattern on a first surface of a semiconductor substrate and interconnected by a plurality of connective traces. The diffusions are minimum geometry dots for a standard semiconductor fabrication process that are spaced apart from one another by an interval that is less than an average distance travelled by photo-generated carriers in the substrate before recombination. A conductive backplane is formed on a second surface of the semiconductor substrate to produce an inverted induced signal for noise cancelling.

Abstract: A ferroelectric element is provided that can be highly densely integrated having a high Pr and a small Ec by using a ferroelectric thin film of the perovskite structure. A large distortion is imparted to the crystalline lattices of a ferroelectric thin film of the perovskite structure by using in combination elements having dissimilar ionic radii for the A-site that constitutes crystalline lattices, for the B-site and for the C-site that produces polarization, in order to obtain a ferroelectric element of a structure in which the ferroelectric thin film exhibiting a high spontaneous polarization and a small coersive electric field is sandwiched by the electrodes.

Abstract: A ferroelectric thin film device comprises: a Si substrate; a TiN thin film epitaxially grown on the Si substrate in which Ti is partially substituted by Al; a metal thin film epitaxially grown on the TiN thin film; and a ferroelectric thin film grown and oriented on the metal thin film and composed of an oxide having a perovskite structure. The amount of Al substituted at Ti sites in the TiN thin film is about 1 to 30% in terms of Al atoms, and the oxygen content of the TiN thin film is about 5% or less in terms of oxygen atoms.

Abstract: A DRAM cell structure, and a fabrication process to create the DRAM cell structure, has been developed. The area consumed by the DRAM cell structure is reduced by vertically aligning a polysilicon word line structure, to an underlying bit line structure, and to an overlying capacitor structure. The process features creating a narrow hole in a polysilicon word line structure, and in overlying and underlying insulator layers. The narrow hole, when filled with single crystalline silicon, connects the polysilicon word line structure to an underlying bit line structure, as well as connecting to an overlying capacitor structure.

Abstract: A semiconductor memory includes a semiconductor substrate, a memory cell portion formed on the substrate and including stacked capacitors formed on the substrate, each having a storage electrode formed on a bottom surface of a recess in an insulating layer, a capacitor insulating film formed on the storage electrode, and a plate electrode formed on the capacitor insulating film and lower than an upper edge of the recess, and a first multilayered interconnecting layer having an interconnecting layer including a plate interconnection connected to the plate electrode, and a peripheral circuit portion formed adjacent to the memory cell portion on the substrate and comprising a second multilayered interconnecting layer.

Abstract: An integrated circuit (IC) capacitor offers reduced sensitivity to parasitic capacitance, reduced-size, and increased noise immunity, such as for use in digital-to-analog converters (DACs), analog-to-digital converters (ADCs), switched-capacitor filters, and other IC circuits. The capacitor includes a first polysilicon layer, a superjacent second polysilicon layer separated from the first polysilicon layer by an insulator, and an overlying metal layer separated from the second polysilicon layer by an insulator. The metal layer provides a shield that is connected to a known voltage, or to the first polysilicon layer. When connected to the first polysilicon layer, the overlying metal layer also provides additional parallel capacitance, thereby reducing the integrated circuit area of the capacitor. In one example, the overlying metal layer is a second metal layer that is also used, together with a first metal layer, for interconnecting IC components.

Abstract: A method of forming a dielectric layer includes, a) chemical vapor depositing a dielectric layer of Ta2O5 atop a substrate; and b) providing a predominately amorphous diffusion barrier layer over the Ta2O5 dielectric layer. A method of forming a capacitor includes, a) providing a node to which electrical connection to a capacitor is to be made; b) providing a first electrically conductive capacitor plate over the node; c) chemical vapor depositing a capacitor dielectric layer of Ta2O5 over the first electrically conductive capacitor plate; and d) providing a predominately amorphous diffusion barrier layer over the Ta2O5 dielectric layer. A capacitor construction is also disclosed. The preferred amorphous diffusion barrier layer is electrically conductive and constitutes a metal organic chemical vapor deposited TiCxNy Dz, where “x” is in the range of from 0.01 to 0.5, and “y” is in the range of from 0.99 to 0.5, and “z” is in the range of from 0 to 0.

Abstract: The present invention relates to a nonvolatile semiconductor device using a vertical channel semiconductor device and a method of fabricating the same. The method starts with forming an insulator for device isolating having a depth D in a semiconductor substrate. The semiconductor substrate is etched with an etch depth d so that elevated portions are formed. A first conductive film is formed covering the elevated portions. After selectively and isotropically etched, the first conductive film is anisotropically etched so as to form floating gates on the side surfaces of the elevated portions. Sequently, a device insulating may be performed by selective oxidation technology. Further, a second conductive film is formed and anisotropically etched so that control gates are fabricated on the side surfaces of the elevated portions. In this case, forming a mask on predetermined regions of the elevated portions, the second conductive film may be etched to form gates of planar transistors or wirings.

Abstract: A high voltage semiconductor device is provided with a p layer which forms a main pn-junction, a plurality of p layers which surround the p layer in a ring form, a ring-like n+ layer which further surrounds those p layers, forward field plates extending in the peripheral direction and reverse field plates extending in the inside direction, the field plates being in contact at a low resistance with the p and n+ layers and reaching the surface of an n− layer through an insulating film, the area of the field plates being not less than one half of the n− surface. This arrangement is particularly effective in stabilizing the blocking voltage of a high voltage semiconductor device which is used in a severe environment, and is very effective in improving the reliability of a high voltage control unit.

Abstract: A trench MOS-gated device comprises a doped monocrystalline semiconductor substrate that includes an upper layer and is of a first conduction type. An extended trench in the upper layer of the substrate has a bottom portion filled with a dielectric material that forms a thick layer in the bottom of the trench. The upper portion of the trench is lined with a dielectric material and substantially filled with a conductive material, the filled upper portion of the trench forming a gate region. An extended doped zone of a second opposite conduction type extends from the upper surface into the upper layer on one side of the trench, and a doped well region of the second conduction type overlying a drain zone of the first conduction type is disposed in the upper layer on the opposite side of the trench. The drain zone is substantially insulated from the extended zone by the thick dielectric layer in the bottom portion of the trench.

Abstract: In a case where an impurity for suppressing the short channel effect of MISFETs is introduced into a semiconductor substrate obliquely to the principal surface thereof, gate electrodes adjacent to each other are arranged so that the impurity to be introduced in directions crossing the gate electrodes may not be introduced into the part of the semiconductor substrate lying between the gate electrodes, and the source region of the MISFETs is arranged in the part between the gate electrodes.

Abstract: At a portion below a gate electrode of a vertical type MOS transistor having a gate electrode and source electrodes formed over the surface of a semiconductor substrate and a drain electrode formed over the back thereof, a P type impurity diffusion layer spaced away from P well diffusion layers which surround sources, is formed in the semiconductor substrate which serves as a drain region.

Abstract: An ON-state voltage is reduced. A line of gate trenches 8 is formed on an n-type silicon layer (a SOI layer) 3 so as to divide a p-type base layer 4 and an n-type emitter layer 5. The gate trench 8 extends from the n-type emitter layer 5 toward a collector electrode 21. A gate electrode 10 is buried in the gate trench 8 with a gate insulation film 9 interposed therebetween. The gate electrode 10 is provided opposite to a vertical section of the p-type base layer 4. Therefore, a channel width can be kept great. Furthermore, a wide region of the n-type silicon layer 3 which is provided opposite to the gate trench 8 functions as an accumulation layer of a hole. As a result, the ON-state voltage can be reduced.

Abstract: A high voltage metal oxide semiconductor device. The high voltage device comprises a high voltage NMOS, a high voltage PMOS, or a high voltage CMOS. A field oxide layer is used to isolate the gate from the source region, while a diffusion region is formed under the field oxide layer. A channel region around the source drain extends across a first doped well and a second doped well having different dopant concentration. The channel region further comprises two grading regions with different dopant concentrations around the drain region.

Abstract: In a process for producing a thin-film device, a conducting layer composed of an anodically oxidizable metal is formed on a substrate and is etched to form gate bus lines and gate electrode having upper surfaces parallel to the substrate and inclined side surfaces. The gate bus lines and the gate electrodes are anodically oxidized, so that they include inner conducting portions and outer insulating oxide films covering the inner conducting portions. The outer insulating films prevent the bus lines from short circuiting, and the inclined side surfaces of the bus lines makes it possible to fabricate a dense wiring arrangement.

Abstract: Using thin film transistors (TFTs), an active matrix circuit, a driver circuit for driving the active matrix circuit or the like are formed on one substrate. Circuits such as a central processing unit (CPU) and a memory, necessary to drive an electric device, are formed using single crystalline semiconductor integrated circuit chips. After the semiconductor integrated circuit chips are adhered to the substrate, the chips are connected with wirings formed on the substrate by a chip on glass (COG) method, a wire bonding method or the like, to manufacture the electric device having a liquid crystal display (LCD) on one substrate.

Abstract: According to a semiconductor device of the present invention, a field oxide film is formed so as to cover the main surface of an SOI layer and to reach the main surface of a buried oxide film. As a result, a pMOS active region of the SOI and an nMOS active region of the SOI can be electrically isolated completely. Therefore, latchup can be prevented completely. As a result, it is possible to provide a semiconductor device using an SOI substrate which can implement high integration by eliminating reduction of the breakdown voltage between source and drain, which was a problem of a conventional SOI field effect transistor, as well as by efficiently disposing a body contact region, which hampers high integration, and a method of manufacturing the same.

Abstract: A semiconductor device having an ESD protection element with an improved ESD resistance is obtainable even if it is formed on the same substrate together with an internal circuit. An SiGe—P well region (3) mainly composed of SiGe having a smaller breakdown field than Si, is formed in the upper portion of a P type Si substrate (1). A drain region (4) and a source region (5) are selectively formed in the surface of the SiGe—P well region (3), and therefore, the boundary between the SiGe—P well region (3) and the drain and source regions (4), (5) defines a PN junction. This results in a MOS transistor for protection comprising the SiGe—P well region (3), the drain region (4), the source region (5), a gate oxide film (6), and a gate polysilicon layer (7).

Abstract: A semiconductor package contains a CMOS core integrated circuit chip, a support chip, and leads for external contact. The support chip has lead-buffer circuits such as ESD protection circuits, decoupling capacitors, drivers, and receivers, for electrical connection to the core integrated circuit chip and to the leads. By removing these lead-buffer circuits from the core chip and providing them on a separate support chip, core integrated circuit chip yield and performance are improved. Typically, the support chip is elongate and has a line of circuits, one for each pad of the core chip. Since the process technology used to build the buffer circuits is decoupled from the process technology used to build the core integrated circuit chip, a high degree of ESD protection can be provided for silicon-on-insulator chips, chips using shallow trench isolation, and for chips using very small minimum dimension lines.

Abstract: A memory cell is formed in which N channel transistors A and P channel transistors B having respectively different conduction types are alternately fitted. The channel section of the N channel transistor A and the P-type drain 7a of the P channel transistor B are commonly used in a shared manner, and the channel section of the P channel transistor B and the N-type source 5b of the N channel transistor A are commonly used in a shared manner; thus, it is possible to achieve high integrity. Moreover, the junction between the adjacent P-type drain 7a and N-type source 5b is always maintained in a reverse bias state so that the P-type drain 7a and the N-type source 5b are separated. With this arrangement, the separation area between the respective transistor elements is minimized so that it is possible to provide a semiconductor device which can achieve miniaturization and high integrity.

Abstract: A threshold voltage or a channel potential of a MIS device can be set in an analogue fashion. A MIS device includes a multi-layer structure having a gate insulating film in which an oxide film, a nitride film and an oxide film are laminated in that order. The threshold voltage or channel potential of the MIS device can be controlled by an amount of electric charges injected into the nitride film.

Abstract: A p− epitaxial layer is formed on the main surface of a p+ silicon substrate. A p-type impurity region is formed extending from the main surface into epitaxial layer. P-type impurity region has a first region having a relatively large thickness and a second region having a relatively small thickness. A p-well is formed on first region and an n-well is formed on second region. A p MOS transistor is formed on n-well and an n MOS transistor is formed on p-well.

Abstract: In a semiconductor device including high-voltage, middle-voltage, and low voltage transistors having operating voltages different from one another, a gate length and a thickness of a gate oxide film are increased as the operating voltage is increased. Accordingly, in the high-voltage transistor, an electric field produced at a channel is relaxed. In the low-voltage transistor, a structure is made finer. A concentration of a well and an impurity amount implanted into a surface portion of a substrate are set to be identical with each other in all the transistors. Accordingly, the semiconductor device can be speedily manufactured at a high yield.

Abstract: Dot-pattern-like impurity regions are artificially and locally formed in a channel forming region. The impurity regions restrain the expansion of a drain side depletion layer toward the channel forming region to prevent the short channel effect. The impurity regions allow a channel width W to be substantially fined, and the resultant narrow channel effect releases the lowering of a threshold value voltage which is caused by the short channel effect.

Abstract: A novel MOS transistor having minimal junction capacitance in this method of fabrication. According to the present invention, a gate dielectric layer is formed on a first surface of the semiconductor substrate. A gate electrode is then formed on the gate dielectric layer. Next, a pair of recesses are formed in the semiconductor substrate on opposite sides of the gate electrode. A dielectric layer is then formed on the surface of each of the recesses. A Semiconductor material is then deposited into the recesses to form a pair of source/drain regions.

Abstract: Highly refractory titanium silicide structure comprises a titanium silicide film formed on a silicon crystal surface and a thermal oxide film formed on this titanium silicide film. A manufacturing method of the highly refractory titanium silicide is as follows. Initially, titanium is deposited on surfaces including a silicon crystal surface to form a titanium film (12) of a predetermined thickness. This titanium film (12) is then heat-treated in vacuum or in a certain atmosphere which does not cause any oxidation, to form a titanium silicide film (13). Subsequently, further heat treatment at temperatures between 600° C. and 1,000° C. in oxygen atmosphere is done for a predetermined time to oxidize the surface of the titanium silicide film (13). This oxidization of the surface of the titanium silicide film (13) restrains agglomeration in the titanium silicide which might occur in the subsequent annealing, so that the resistance value increase can be prevented.

Abstract: A method of fabricating an integrated circuit on a wafer includes forming a gate electrode stack over a gate dielectric and forming nitride spacers along sidewalls of the gate electrode stack other than along lowermost portions of the sidewalls. Subsequently, a reoxidation process is performed with respect to the gate dielectric. By providing the nitride spacers along exposed surfaces of conductive barrier and metal layers of the word line stack, those surfaces can be passivated, thereby preventing or reducing the conversion of those layers to non-conductive compounds during the reoxidation process. At the same time, the nitride spacers can be formed so that they do not interfere with the subsequent reoxidation of the gate dielectric. An integrated circuit having a gate electrode stack with nitride spacers extending along sidewalls of the gate electrode stack other than along lowermost portions of the sidewalls is also disclosed.

Abstract: The integrated microactuator has a stator and a rotor having a circular extension with radial arms which support electrodes extending in a substantially circumferential direction and interleaved with one another. For the manufacture, first a sacrificial region is formed on a silicon substrate; an epitaxial layer is then grown; the circuitry electronic components and the biasing conductive regions are formed; subsequently a portion of substrate beneath the sacrificial region is removed, forming an aperture extending through the entire substrate; the epitaxial layer is excavated to define and separate from one another the rotor and the stator, and finally the sacrificial region is removed to release the mobile structures from the remainder of the chip.

Abstract: A photo detective unit includes a photo detective semiconductor chip including a photo detective element formed under a first manufacturing condition and a buffer circuit for shaping output waveform of the photo detective element, and a signal processing semiconductor chip formed under a second manufacturing condition and responsive to voltage from the photo detective semiconductor chip for generating digital data, and the photo detective semiconductor chip and the signal processing semiconductor chip are together accommodated in a single package.

Abstract: A photosensitive element may be formed by an upper layer which is sensitive to visible light and a lower layer which is sensitive to infrared radiation. By making the upper device infrared transparent, the upper device can detect visible light while the lower device detects infrared radiation in one single detector. In some embodiments a plurality of pixels may be provided, only some of which contain both the first and second layers.

Abstract: A photodiode is provided comprising a substrate, a well with a first electric type within the substrate, a heavily doped region with a second electric type within the well, and a insulating layer on the substrate. The insulating layer in the position on the heavily doped region is thinner than in other positions. A junction is thus formed between the heavily doped region and the well.

Abstract: A semiconductor device is comprised of: an element isolating film formed on one major surface of a semiconductor substrate; an element forming region formed on the major surface and surrounded by the element isolating film; a gate electrode formed via a gate insulating film on the element forming region and extended over the element isolating film; first and second impurity regions formed in the element forming region, whose portions exposed from a surface of the semiconductor substrate are made in contact with the element isolating film and are located opposite to each other under the gate electrode; a first insulating film formed near the gate electrode on the first impurity region, and extended over the gate electrode and near an extended portion of the gate electrode within the element isolating film; and a second insulating film formed near the gate electrode on the second impurity region.

Abstract: A quick, deep, clean two step trench process for an SOI/bonded wafer substrate 100 is disclosed. A first isotropic plasma etch using SF6 is made through an opening 40 in the photoresist layer on device layer 16. A second anisotropic plasma etch using SF6 and C12 stops on the isolation/bond oxide layer 14. The bottom of the trench 60 is overetched to form cavities 50 on the isolation/bond oxide layer 14 without removing a substantial portion of that layer.