Abstract: A control circuit, system for, and method of, testing a device under test (DUT) coupled to a load having a controllable load current level. The DUT is capable of operating in a regulated range and an unregulated range. In one embodiment, the control circuit includes: (1) minimum and maximum current control stages that set minimum and maximum load current values, respectively, for the control circuit and (2) an integrator, coupled to the DUT. In a constant current mode, the integrator selects one of the minimum and maximum load current values to control the load current level and test the DUT while the DUT is operating in the regulated range. In a constant voltage mode, the integrator produces an intermediate load current value based on a relationship between a voltage of an output of the DUT and a reference voltage to control the load current level and test the DUT while the DUT is operating in the unregulated range.

Abstract: An electronic device includes an Erasable Programmable Read-Only Memory (EPROM), a programmable logic device connected to the EPROM, and a single package enclosing the EPROM and the programmable logic device. The electronic device provides combined functionality that allows the EPROM to store configuration data for a programmable logic device, a Static Random Access Memory (SRAM), or an external programmable logic device, while the programmable logic device is configured to implement another function, such as a Joint Test Access Group interface function, an address decoder function, or a state machine function.

Abstract: A logic cell for a programmable logic device that features a random access memory adapted to selectively function as additional logic functions for the logic cell or one of a several different types of random access memory. For example, the random access memory may be configured to provide AND-OR logic functions or as a 32×1 single input port random access memory, two 16×1 single input port random access memories or a 32×1 dual input port memory.

Abstract: A product-term array that may allow for the implementation of product terms requiring less silicon area than conventional designs. The product terms may also have a shorter propagation delay when compared with conventional designs. A multiplexer, which may be programmed with a configuration bit or signal, may select the polarity of an input signal to the product-term array. Duplicating a number of the initial inputs to the array may accommodate particular design constraints that may require both polarities (i.e., both positive and negative) of a given signal or set of signals. Even with the duplication of certain inputs, the total number of product-term inputs to the array will generally be reduced when compared with conventional designs, that duplicate the polarity of every input internally to the array.

Abstract: A CMOS wave shaping buffer circuit comprises two CMOS inverter stages connected as a non-inverting buffer. In addition, the two stages are further coupled by way of their supply connections to produce a positive feedback from the second stage to the first whenever both stages are driven to a linear state, that is both transistors of each stage are “ON”. The positive feedback prevents the output stage from remaining in a logically ambiguous state, but forces crisp transitions from one state to another even for slowly changing input signals.

Abstract: An output driver circuit for driving a signal onto a signal line. The output driver circuit comprises at least one driver circuit and a passive network. The passive network is configured to limit the variation in the output impedance of the output driver circuit. The output driver circuit thus provides an output impedance that closely matches the loaded impedance of the signal line at all times so as to minimize secondary reflections on the signal line.

Abstract: A buffer circuit for providing dynamic threshold control. The buffer circuit includes a pair of input inverters designed with different skewed threshold potential characteristics. The outputs of the skewed inverters are directed to a logic circuit designed to select either the faster or the slower signal received from the two inverters for transmission to passgate devices coupled to the respective inverters. Only one of the passgate devices is enabled to ensure that only one of the output signals from the two inverters is propagated through the buffer. A latch is preferably connected between the logic circuit and the two passgate devices to maintain the states of the inverters and the logic circuit. The circuit can be designed to define the threshold potential at which switching will occur so as to reduce propagation delay or increase it as desired. It is therefore possible using the circuit to increase transmission rates with minimal affect on signal noise.

Abstract: An integrated circuit device having emitter follower outputs with adjustable output currents includes a variable bias generator that produces a bias voltage. The bias voltage is connected to the bases of current source transistors in order to program the output currents. The variable bias generator is connected to an electrical connection area of the integrated circuit device. An external programming circuit can be connected to the electrical connection area in order to set the bias voltage, to thereby program the desired amount of current in the output current sources. The external programming circuit typically can be a resistance or an external voltage source. The variable bias generator can be any of a number of circuits that produce a bias voltage that is dependent upon the external programming circuit connected to the electrical connection area.

Abstract: A circuit arrangement for monitoring a load operated with a clock signal is provided. The circuit arrangement may be applied to the field of automotive engineering. The circuit arrangement includes a comparator having at least two inputs and one output. The circuit arrangement further includes a D-flip-flop having one clock input, one signal input, and one output. At least a first input of the comparator is coupled to the load signal. The output of the comparator is coupled to the signal input of the D-flip-flop. The clock input of the D-flip-flop is coupled to the clock signal. The output of the D-flip-flop delivers a monitoring signal.

Abstract: A current sorter for sorting a plurality of currents is disclosed. The current sorter comprises an input circuit unit for receiving a plurality of input currents to be sorted, a winner-take-all (WTA) circuit unit for finding the maximum current, a feedback control and voltage output circuit unit for generating feedback control signals and output voltages indicating the maximum current, and an output circuit unit for outputting sorted currents. A plurality of input currents are simultaneously input to the input circuit unit and the sorted results are output in a time-shared manner on the output circuit unit.

Abstract: A circuit and a method for comparing an input voltage to an internally generated reference voltage utilize a bias network to make the voltage comparison. The bias network is preferably configured to generate a proportional-to-absolute-temperature (PTAT) reference voltage, which is used for the voltage comparison. Although the circuit can be implemented to operate in a number of applications, the circuit is particularly useful in a current sensing application. The circuit includes the bias network, a comparison current path and an output terminal. The comparison current path is configured to partially duplicate a current path of the bias network on which the reference voltage is generated. The comparison current path includes a current control element and an active transistor. Depending on the input voltage applied to the active transistor of the comparison current path, the output terminal is driven to generate either a high or a low comparison signal.

Abstract: An infinite sample-and-hold circuit which employs a DAC and an ADC coupled with a mode control circuit. In acquisition mode, the mode control circuit connects the analog input signal to the ADC. The ADC drives the DAC and when the DAC output equals the analog input, the mode control circuit disconnects the analog input and the DAC drives the output in hold mode. The mode control circuit preferably includes a comparator/buffer circuit including switching circuitry. The ADC is preferably of the successive approximation type. The comparator/buffer is used in two modes: (1) open loop, as a comparator, and (2) closed loop, as a buffer. During acquisition, the comparator mode is used, while in hold mode the buffer mode is used. The utilization of the same amplifier to provide both functions allows cancellation of offset errors otherwise introduced by the comparator and buffer, at least to a first order.

Abstract: A sample and hold circuit (200) accepts an input (202). During a first half of the clock (204) (either an active high portion or an active low portion) the devices (216, 220, and 222) drive the node (218) to a voltage representative of the voltage present on input (202). At a rising edge of the clock (204), the switch (222) is disabled and the voltage on the node (218) is forced to a higher hold voltage by a capacitor (224). While sample circuit (208) is holding the high voltage on node (218), a hold circuit (210) is settling to a hold voltage representative of the voltage on node (218) in a master-slave fashion. This manner of clocking and controlling the circuit (200) allows circuit (200) to be used in low power, high speed telecommunications systems.

Abstract: A current detection circuit having a voltage conversion section for converting current flowing to a load to a voltage; an amplifier section having an operational amplifier for amplifying the voltage converted by the voltage conversion section; a constant current circuit section having a constant current circuit connected to an input of the operational amplifier; and a current detection section for detecting a load current from a voltage amplified by the amplifier section. The constant current circuit section shifts the input offset voltage to the operational amplifier of the amplifier section. As a result, a dead zone in which a load current cannot be detected due to the input offset voltage of the operational amplifier can be eliminated.

Abstract: An improved off-chip driver circuit is disclosed which will properly transition from an active mode to a high impedance mode. The circuit includes first and second input nodes for receiving a first and second input signal respectively. An input composite transmission gate including a p-channel transistor in parallel with an n-channel transistor to receive the first input signal is provided in the circuit. A push-pull circuit is also included which includes the pull-up transistor disposed between a voltage supply and an output node and a first pull-down transistor disposed between ground and the output node. The pull-up transistor has a gate electrode for receiving the first input signal provided by the input composite transmission gate. The first pull-down transistor has a gate electrode for receiving the second input signal. A control transistor is included and is coupled between the gate electrode of the pull-up transistor and the output node.

Abstract: An N times frequency multiplication circuit uses duty cycle control buffers in combination with edge detectors to provide both multiplication and 50% duty cycle adjustment. Parallel branches of duty cycle control buffers are preset for respective duty cycles of 1/N, 2/N,...,N−1/N. The buffers each receive a common edge detected input signal and simultaneously output their respective duty cycle adjusted clock signals. A rising and falling edge detector generates a pulse train at double the frequency of the 1/N buffer output, while falling edge detectors generate time spaced pulse trains from the outputs of their respective 2/N,...,N−1/N buffers. These pulse trains are combined in an OR gate to provide an output pulse train at a frequency N times the input clock frequency fin. A final stage duty cycle control buffer adjusts the N times fin output signal to a 50% duty cycle.

Abstract: An apparatus is used to control a reset function of an electronic device. The apparatus includes a circuit adapted to monitor a system voltage level and deliver a control signal in response to the system voltage level falling below a first preselected value. A duration controller receives the control signal and delivers a first reset signal for a preselected duration of time after receiving the control signal. A voltage level controller receives the first reset signal, and delivers a second reset signal that persists until the system voltage rises above a second preselected magnitude.

Abstract: The invention provides a power-on circuit which assures a high impedance state of a terminal of an IC until the IC starts its operation after a point of time immediately after a power supply voltage is made available to the IC. The power-on circuit is built in a synchronous IC memory and includes a ring counter, an output controlling circuit, and a pulse signal interruption circuit. The ring counter successively generates a pulse signal after a power supply voltage begins to be supplied to the synchronous IC memory. The output controlling circuit controls an output terminal of the synchronous IC memory to a high impedance state while the pulse signal generated by the ring counter is inputted to the output controlling circuit. The pulse signal interruption circuit interrupts the pulse signal from being inputted to the output controlling circuit after a clock signal is inputted to the pulse signal interruption circuit.

Abstract: A charge pump and filter for a phase-lock loop circuit are provided with common-mode voltage control for differential outputs to be used by a voltage-controlled oscillator. The common-mode voltage controller preferably initializes capacitors in the filter to an optimum common-mode voltage in response to a reset signal. Common-mode voltage is controlled using currents that are small compared to currents generated by the charge pump (less than 20 &mgr;A).

Abstract: A device for the generation of a drive signal phase-shifted with respect to an external synchronization signal includes a first digital phase-locked loop to give a reference signal, servo-linked to the external synchronization signal by a current phase among N phases of a high frequency signal. The device includes a second digital phase-locked loop including a measuring circuit to measure the position of an active edge of the drive signal or a derived signal that is delayed with respect to an active edge of the reference signal. The second phase-locked loop also includes a circuit to compute the phase shift to be made and a phase-shift circuit. The measurement circuit includes a circuit for the rough measurement of the position, controlled by a fixed phase of the high frequency signal independent of the present phase of locking in the first loop. The digital computation circuit accounts for this shift between the fixed phase and the present phase.

Abstract: A duty ratio can be corrected to 1:1 without affecting the operation of a PLL or DLL circuit. A rising-edge control circuit (1a) generates a signal (S10) by inverting a signal (S6), and varies a time required for a high to low transition of the signal (S10). A comparator (A1) causes a transition of a signal (S2) when the signal (S10) becomes less than a reference value (Vref), so the duty ratio of the signal (S2) varies according to the length of its fall time. A duty-ratio detecting circuit (2) is a charge pump for drawing or passing a constant amount of current according to a voltage of the signal (S2). A duty-ratio correction filter (3) converts a signal (S8) obtained from the duty-ratio detecting circuit (2) into a smooth voltage signal (S9). This signal (S9) becomes a feedback signal to the rising-edge control circuit (1a) for correcting the duty ratio of the signal (S2) to 1:1.

Abstract: A flip-flop having one or more stages (e.g., a master stage and a slave stage in a master-slave flip-flop, or a single stage as in a latch), at least one stage having a driver coupled at its input and output to a feedback path with a gated inverter having embedded preset and/or clear logic. By embedding the preset/clear logic in the feedback path, the driver can be implemented using a simple inverter. Moreover, the preset and/or clear functionality can be added without adversely affecting either the setup time or the clock-to-Q propagation time of the flip-flop.

Abstract: Techniques for providing improved memory flip-flops and other logic circuits are described. A flip-flop uses only one p-channel transistor to drive the output node strongly to achieve fast results. To reduce diffusion area, parallel logic is substantially eliminated and only series branches are used, in critical areas. This allows all pull-up transistors and/or all pull-down transistors to be formed from contiguous active areas. The D-to-Q path is reduced, and the clock is used to control the output. The clock becomes the dominant controller of the output when it is located closest to the output. Placing the clock devices closest to the clocked nodes reduces clock skew. The rising D response time and falling D response time are caused to be as close as possible to reduce the overall cycle time. To reduce parasitics in the circuit, complex-gates are used which are asymmetric. Even multiples of series branches per gate are used to share contacts and eliminate breaks in the layout diffusion.

Abstract: An active digital voltage regulator circuit is a two terminal device that is connected in shunt to first and second power supply input lines. The active digital voltage regulator circuit stores energy during times when the local power supply voltage is greater than a predefined voltage, e.g., during times when the parasitic inductances supplement the local power supply voltage. A control circuit within the regulator circuit is a combination of two self-biasing and off-set nulling power supply monitor circuits. Each power supply monitor circuit further includes a differencing, non-overlapped, dual-output amplifier connected to the first and second power supply input lines. The differencing, non-overlapped, dual-output amplifier includes a predriver stage and an output stage, both of which are connected to the first and second power supply input lines.

Abstract: A delay time compensation circuit for a clock buffer includes first and second toggle flip-flops multiplying an input clock signal and a delay clock signal which is delayed by an input buffer, respectively, a time interval extraction chain extracting a time interval between a rising edge of the input clock signal and a rising edge of the delay clock signal in accordance with clock signals multiplied in the first and second toggle flip-flops, and a variable delay chain delaying the input clock signal by a time interval extracted from the time interval extraction chain. The circuit employs a ½ multiplied clock signal and operates without regard to a duty cycle of an input clock signal, thereby compensating for all the delay time within the cycle of the input clock signal.

Abstract: ON-OFF operations of the pull-up and pull-down transistors are independently controlled so as to generate a start edge of a pulse signal in synchronizing with any one of a rising edge and a falling edge of a first cycle of the clock signal, and then generate an end edge of the pulse signal in synchronizing with any one of a rising edge and a falling edge of a later cycle than the first cycle, thereby avoiding concurrent ON-states of the pull-up and pull-down transistors, whereby the pulse generator is capable of generating the pulse signal completely depending upon a clock signal externally supplied but being independent from internal factors of the circuits thereby allowing a high speed and constant width pulse generation.

Abstract: The circuit configuration produces complementary signals. An input signal is routed from an input terminal via a first path, through a pass element, and to a first output terminal. The input signal is also routed on a second path, connected in parallel with the first path, via an inverter, and to a second output terminal. The first and the second output terminal are connected to a first and a second output node, respectively, via a compensation device. The compensation device compensates for the different time delays in the signals on the first and on the second path.

Abstract: A circuit and associated method for determining the offset bias of a comparator by first shorting together the inputs of the comparator to apply the same voltage signal at each of the inputs of the comparator. The voltage signal at one of the inputs is then offset a select amount by applying varying selected resistances from a variable resistor to the comparator. The variable resistor is controlled by a programmable controller that is responsive to an input clock signal. At each selected amount of offset applied to the input, the output is monitored to determine if the output of the comparator has flipped, or changed state. When the output flips, the corresponding resistance setting is used to compensate for the corresponding offset bias of the comparator.

Abstract: Inverters are provided which adapt their output impedance to the driven load and thereby enhance inverter performance (e.g., current drive, switching speed and common-mode rejection). An inverter embodiment includes a complementary common-source stage arranged to drive an output port in response to signals at a first side of a differential input port and a complementary common-drain stage arranged to drive the output port in response to signals at a second side of the differential input port.

Abstract: A voltage level converter circuit includes a first node, a second node having a voltage according to an input voltage, a P channel MOS transistor connected between the second node and the first node, turned on when the input voltage attains an L level, a third node to which a first voltage is supplied, a first N channel MOS transistor connected between the third node and a fourth node, turned on when the input voltage attains an H level, a second N channel MOS transistor connected between the first node and the fourth node, and having a gate to which an alleviate signal is supplied, a third N channel MOS transistor, and a level determination circuit for providing an alleviate signal according to the level of the first voltage.

Abstract: A frequency doubler includes a first Gilbert cell, a second Gilbert cell coupled to the first Gilbert cell, a frequency generator configured to apply a first sinusoidal wave to the first Gilbert cell, and a phase shifter applying a sinusoidal wave shifted from the first sinusoidal wave to the second Gilbert cell. A method of doubling frequency without using a feedback loop includes providing a first Gilbert cell, providing a second Gilbert cell coupled to the first Gilbert cell, applying a first sinusoidal wave to the first Gilbert cell, and applying a sinusoidal wave shifted from the first sinusoidal wave to the second Gilbert cell.

Abstract: A bipolar analog multiplier with a greatly reduced output sensitivity to temperature. The multiplier uses the difference between the multiplier input voltages and the reference voltages to generate currents. Voltages which are logarithmically dependent on the generated currents are developed and applied to inputs of bipolar variable transconductance stages. Circuits are used to reduce ringing at the output of the multiplier.

Abstract: In a CMOS noise eliminating circuit, a plurality of PMOS transistors or NMOS transistors are connected in series so as to cause of switching speeds or switching timings of the PMOS transistors or the NMOS transistors, which are connected in series, to differ from each other, thereby improving the noise-resistant performance of a semiconductor integrated circuit.

Abstract: A circuit and method to drive an H-bridge circuit are disclosed. The H-bridge circuit uses NMOS transistors for both the upper and lower sets of transistors. An inductive head is coupled between the terminals of the transistors. When a logic signal is received, one of the upper transistors is driven. The upper transistor selected to be driven is responsive to the logic signal. A corresponding lower transistor is also driven, forcing current through the inductive head in a first direction. The driving circuit for the lower transistors includes a programmable circuit structured to capacitively couple the output of the driving circuit to a pull-up voltage, thereby allowing the amount of current forced through the inductive head to be maximized for optimum data transfer. Within the programmable voltage boost circuit are several logic gates, each coupled to a capacitor of differing value.

Abstract: A threshold element enabling a logical operation with fewer transistors and easy design and setting of an element weight and a threshold value is provided. In a threshold element of the present invention, MIS (Metal Insulator Semiconductor) transistors each passing a drain current upon excitation corresponding to weight &ohgr;i of input Xi obtained from a logical expression Y=Sign(&Sgr;&ohgr;iXi−1) derived from Y=F(Xi) thereof are connected in parallel. A terminal for transmitting an input signal Xi corresponding to each of the transistors is connected to the gate electrode thereof. By this input signal, excitation of each of the transistors is controlled. An output voltage based on a sum of the drain currents from the transistors is compared with a threshold value by a comparing inverter, and a comparison result is output.

Abstract: A semiconductor device for outputting a reference voltage, the value of which changes depending on the ambient temperature, and a crystal oscillator device comprising the semiconductor device. The semiconductor device comprises at least one depletion MOS transistor having an overall conductivity coefficient KDO and at least one enhancement MOS transistor having an overall conductivity coefficient KEO, wherein KDO does not equal KEO and the transistors are connected in series. Thus, the semiconductor device provides an output reference voltage having a predetermined temperature characteristic which can be effectively controlled in accordance with the ambient temperature. The semiconductor device is employed in a two-level housing or in a one-level housing package so that the crystal oscillator device can have a small size and is produced easily. Also disclosed is a method of producing the crystal oscillator device.

Abstract: A method for providing a fuse apparatus for a semiconductor device includes providing at least one fuse portion of the fuse apparatus with at least two fuses connected in series. A circuit, such as a redundancy decoder, is adapted to utilize a fuse apparatus including at least one fuse portion having a plurality of fuses connected in series. The fuse apparatus is preferably provided with polysilicon fuses which are cut using a laser beam cutting device. The fuse apparatus provides an increased probability of accurately cutting a fuse portion of a fuse means necessary to effect a proper repair of the circuit and to improve the semiconductor circuit operational reliability.

Abstract: A switched capacitor current reference circuit with improved tolerance. Additional optional devices maintain an output in the absence or loss of an input frequency.

Abstract: In this invention a booster circuit is driven with two complimentary boost signals. The two boost signals produce two complimentary boosted signals that are connected to a pump circuit output by means of two pass gate circuits. The transistors in each pass gate are controlled such that one pass gate circuit conducts in a first half of a clock cycle and the second pass gate circuit conducts in a second half of a clock period. Each pass gate is driven such that the full boosted signal is transferred to the output of the pump circuit and is not diminished by a threshold voltage of the pass gate circuit. The efficiency of this design keeps the output capacitor charged to a value close to the average value of boosted signal.

Abstract: A circuit is provided for biasing a semiconductor substrate. The circuit comprises a driving signal generating circuit and a charge pump circuit. The driving signal generating circuit produces first to fourth charge pump driving signals in response to an oscillation signal. Each of the first and fourth charge pump driving signals has a high voltage level that is higher than a power supply voltage. Accordingly, even though the power supply voltage is lowered, a loss of a pump efficiency is prevented because a PMOS transistor in the charge pump circuit is driven by the charge pump driving signal having the voltage higher than the power supply voltage.

Abstract: In a charge pump circuit, the issues of increase in loss due to the backgating effect, increase in cost, risks of latch-up and charge leak and the like, which would be involved in achieving voltage reduction, are resolved with a simple circuit structure. A pump cell 31 has nMOS transistors M1-M3 and capacitors C1, C2. An auxiliary capacitor C is connected to an input node IN, and further p-well portions of the nMOS transistors M1-M3 are connected to this auxiliary capacitor C, the nMOS transistor M3 is interposed between each p-well portion and output node OUT, and the input node IN is connected to the gate of the nMOS transistor M3. Thus, with a simple circuit structure which involves only the use of the auxiliary capacitor C, voltage difference of the push-down of the p-well voltage is increased so that the deterioration of pump efficiency due to the backgating effect in the voltage reduction of power supply voltage is eliminated and that latch-up and charge leak are prevented.

Abstract: The current mirror circuit in accordance with the present invention includes a first current mirror circuit composed of first and second MOS transistors being cascade connected to a second current mirror circuit composed of third and fourth MOS transistors. Further, an NPN transistor is interposed between the gate and the drain of the third MOS transistor to which an input current is supplied. Thus, the third MOS transistor can operate normally even with a higher input voltage than in a case where the drain is connected to the gate by as much as the base-emitter voltage of the NPN transistor. In addition, even if the input current is in an off state, electric charge always flows out via the gates of the first and second MOS transistors as the base current of the NPN transistor. Thus, a current mirror circuit can be offered with high precision in output current and a short rise-time when changed from an on state to an off state, while maintaining a wide input voltage range.

Abstract: A back bias voltage level sensing circuit includes a constant current generation unit for generating a constant current regardless of a variation in a power supply voltage; a switch for transferring or disconnecting the constant current generated from the constant current generation unit under the control of a switch control signal; a current distribution unit for distributing the constant current transferred by the switch by using a current mirror under the control of a first control signal; a switching current removal unit for flowing the switching current generated when the switch is turned on and turned off to the ground according to a second control signal; a back bias voltage level sensing unit for sensing a level of a back bias voltage and outputting an output signal according to the current distributed by the current distribution unit; and a switching controlling unit for receiving an oscillating signal and the output signal from the back bias voltage level sensing unit and outputting a switch control

Abstract: A polyphase filter passes a desired frequency and attenuates an image frequency in many communication systems. The invention is an error correction circuit that compensates the polyphase filter for low open loop gain operational amplifiers. When multiple polyphase filters are used in communication circuits on a single integrated circuit (IC), the open loop gain of the operational amplifiers is limited by the IC's ability to dissipate power. The error correction circuit reduces the dependency of the polyphase filter performance on the low open loop gain of its operational amplifiers and hence, on temperature and IC process parameters.

Abstract: A multi-tone signal amplifier topology and an amplifying method in which a first amplifier outputs a first signal having at least one fundamental frequency signal and a first distortion signal. A second amplifier outputs a second signal that has a fundamental frequency signal corresponding to each fundamental frequency signal of the first signal and a second distortion signal. Each fundamental frequency signal of the second signal is substantially in-phase with the corresponding fundamental frequency signal of the first signal, while the second distortion signal is substantially 180° out-of-phase with the first distortion signal. An output coupler combines the first and second signals to form a third signal having the corresponding fundamental frequency signals of the first and second signals constructively combined and a third distortion signal that is a difference between the first distortion signal and the second distortion signal.

Abstract: The present invention, generally speaking, provides an RF amplifier circuit architecture that enables high efficiency to be achieved while avoiding complicated matching networks and load networks. The active device may be of the bipolar transistor type or the FET (field effect transistor) type. A simple driving circuit is provided for each type of active device. In accordance with one embodiment of the invention, a single-ended switch mode RF amplifier includes an RF input signal; an active device having a control terminal; and a non-resonant driving circuit for receiving the RF input signal and controlling a signal applied to the control terminal so as to operate the active device in switch mode.

Abstract: A differential circuit (200) provides for reverse isolation between input and output ports (202, 204). The differential circuit has amplification circuitry that includes active transistors (221, 222) and reverse isolation circuitry that employ transistors (223,224) having similar manufacturing and processing characteristics to couple the input and output ports (202, 204).

Abstract: A variable gain amplifier has a large variable range of a gain with respect to an analog signal having a level changing at a high-speed. The variable gain amplifier is provided with a digital-setting-type signal attenuator having a resistor string including a plurality of resistors connected in series. A maximum attenuation-factor limiting resistor is connected between the resistor string and a ground. Each of the analog switches is connected to respective points of the resistor string. A decoder generates a control signal for selecting at least one of the analog switches, the control signal being generated based on setting data provided from an external device. A voltage across the resistor string is divided by the resistors included in the resistor string, and the divided voltage is output to an amplifier from at least one of the analog switches selected by the control signal generated by the decoder.

Abstract: A signal amplifying circuit (24) includes level shifting input circuits (D1-D4) permitting input common-mode voltages (VIN1 and VIN2) of an amplifier and fault detection circuit (50) to vary between preset limits. The sense amplifier circuit (24) includes a DC offset buffer circuit (52) operable to receive an analog DC offset compensation signal and provide this signal to an input of the amplifier and fault detection circuit (50). The buffered DC offset compensation signal provided to the amplifier and fault detection circuit (50) is operable to reduce an aggregate DC offset voltage attributable to signal amplifying circuit (24) to a desired DC offset level. The amplifier and fault detection circuit (50) also includes a fault detection function whereby an output (VSENSE) of the amplifier circuit (50) is forced to a predetermined output state if either, or both, of the inputs (VIN1 and VIN2) of the sense amplifier circuit (24) are unconnected; i.e., floating.

Abstract: In a power amplifier comprising a plurality of cascaded field effect transistors (FETs), a power sensing circuit for sensing the output power of the power amplifier comprising a FET device operative in a first linear mode and second saturated mode of operation, the FET having source, gate and drain electrodes; and a low value resistor connected between the source electrode and a reference potential for generating a voltage drop between the source and the reference potential such that when the FET operates in the saturation mode, the voltage drop is indicative of the output power of the power amplifier.