Abstract: For providing a semiconductor package with improved moisture resistance and high reliability and a production method thereof, a solder resist is also provided in an appropriate thickness between electrodes of conductor circuits on a surface of a substrate. The resist in these portions is obtained by patterning the solder resist while leaving the solder resist between the conductor circuits by removing the unnecessary solder resist under irradiation of a laser.

Abstract: A method for attaching bumped semiconductor dice to substrates, such as printed circuit boards and multi chip modules, is provided. The method includes the steps of: providing an instant curing adhesive formulated to cure within 0.25 to 60 seconds, and dispensing a volume of the adhesive onto the substrate. The method also includes the steps of heating the die, and aligning the contact bumps on the die to the contacts on the substrate. Following these steps the die can be brought into contact with the substrate to form an adhesive layer therebetween. Heat from the die cures the adhesive layer. In addition, the cured adhesive layer tensions the die against the substrate, and compresses the contact bumps and contacts to form low resistance electrical connections. A system for performing the method includes a lead-on-chip die attacher configured to heat the die, to dispense the adhesive, to align the die and substrate, and then to press the die against the substrate with a desired pressure.

Abstract: A circuit board mounted with a semiconductor device is fabricated by forming on a silicon substrate at least one first metal layer, overlaying a second metal layer to completely cover the first metal layer, covering the whole surface of the second metal layer with an insulating material, etching the insulating material to open a window at a prescribed region of the surface of the second metal layer, selectively imparting adhesiveness to the portion at the window, adhering solder powder to the adhesive portion, melting the solder powder by heating to form a solder bump, selectively imparting adhesiveness to at least one electrode portion of a wiring board, adhering solder powder to the adhesive portion, melting the adhered solder powder by heating to form a solder bump on the electrode portion, and contacting and fusing the solder bump of the silicon substrate and the solder bump of the wiring board so as to form and maintain a prescribed gap between the silicon substrate and the wiring board.

Abstract: A new method is provided for mounting high-density flip chip BGA devices. A dielectric layer is first deposited over the first surface of a metal panel. One or more thin film interconnect layers are created on top of the dielectric layer. The interconnect layers are patterned in succession to create metal interconnect pattern. The BUM technology allows for the creation of a succession of layers over the thin film layers. The BUM layers can be used for power or ground distribution and for signal or fan-out interconnect. A cavity is etched on the second surface of the metal panel. A laser is used to create openings for flip chip pad contacts. The panel is subdivided into individual substrates. The method of the invention can also be applied to Land Grid Array and Pin Grid Array devices.

Abstract: A method of making a circuitized substrate which may be utilized as a chip carrier structure. The method involves the steps of providing a dielectric member and routing out a preselected portion of the base member to form an aperture. Metallization of the dielectric member and the walls of the aperture then occurs, followed by circuitization of the surfaces of the dielectric member. Direct metallization of the aperture walls eliminates many manufacturing steps previously required to metallize the aperture walls.

Abstract: An LOC die assembly includes a die dielectrically adhered to the underside of a lead frame. The active surface of the die underlying the attached lead frame is coated with a polymeric material such as polyimide. The underside of the lead frame overlying the die is coated with a layer of soft material, such as silver, which has a lower hardness than the coating on the active surface for absorbing point stresses. Penetration of stacked filler particles into the soft material reduces point stresses on the active die surface and disadhesion stresses on the lead frame components.

Abstract: A process comprises the following operations: forming a structure of metal elements with functions of support and electrical connection, these metal elements having a high degree of surface finish; fixing a chip of semiconductor material, containing active parts and contact pads, to an area of a metal element of the structure acting as a support; electrically connecting the contact pads of the chip to predetermined metal elements of the structure acting as terminal conductors; and incorporating in plastic the chip of semiconductor material and part of the structure of metal elements. To improve the adhesion between the structure and the plastic, at least part of the surface of the metal elements is roughened by irradiation with a laser light beam.

Abstract: A chip scale package mainly comprises two elastomer pads respectively interposed between a substrate and a semiconductor chip. Each of the elastomer pads is respectively situated on the flank of a slot centrally defined in the substrate, and keeps a predetermined distance from the slot. The semiconductor chip is attached onto the upper surface of the substrate through the two elastomer pads wherein bonding pads formed on the semiconductor chip are exposed from the slot of the substrate. The upper surface of the substrate is provided with a plurality of solder pads and leads. Each of the leads has one end electrically connected to a corresponding solder pad, and the other end electrically connected to a corresponding bonding pad of the semiconductor chip. The substrate has a plurality of through-holes formed corresponding to the solder pads such that each solder pad has a portion exposed within the through-hole for mounting a solder ball.

Abstract: A method of fabricating high density mask-type read only memory (ROM) devices that utilize a thick gate oxide to form non-programable cells and that can be easily integrated into standard CMOS manufacturing. The method includes forming a thick oxide over a semiconductor substrate, removing portions of the thick oxide layer, ion implanting dopants to form buried bit lines, patterning to form coding openings, forming a gate oxide within the coding openings, and forming a plurality of polysilicon gate electrodes constituting word lines of the mask ROM.

Abstract: An infrared optical field effect transistor has been developed using a thin film of Lead Titanate (PbTiO3) deposited on a n/p+ Si substrate by RF magnetron sputtering. This transistor possesses excellent pyroelectric properties and can, therefore, be operated even at room temperature. The infrared optical field effect transistor has the following features associated with rapid bulk channel structure and higher mobility: 1. Can be operated at room temperature, unlike quantum type IR sensors which can only operate at very low temperature (−100° C.˜−200° C.), which results in higher costs. 2. High speed response with only 2.3 &mgr;s of rise time. This is much faster than other types of thermal infrared optical field effect transistors. 3. Easy to fabricate an integrated sensor device.

Abstract: A surface portion of a p type base region is made amorphous as an amorphous layer by implanting nitrogen ions which serve as impurities and ions which do not serve as impurities. After that, the amorphous layer is crystallized to have a specific crystal structure through solid-phase growth while disposing the impurities at lattice positions of the crystal structure. As a result, a surface channel layer is formed with a high activation rate of the impurities.

Abstract: An insulated gate field effect transistor is constructed by first forming a non-single crystalline semiconductor layer or island on an insulating surface of a substrate. A gate insulating layer is then formed on the semiconductor layer. A gate electrode is formed on the gate insulating layer. An impurity is added to a portion of the semiconductor layer to form source and drain regions, and the semiconductor layer is irradiated with light through the gate insulating layer. In preferred embodiments, the substrate is maintained at a temperature less than 400° C. and the light have a wavelength of 250-600 nm.

Abstract: The present invention relates to a method of fabricating a thin film transistor in which a metal silicide line generated from Metal Induced Lateral Crystallization is located at the outside of a channel region. The present invention includes the steps of forming a semiconductor layer on a substrate wherein the semiconductor layer has a first region, a channel region and a second region in order, forming a gate insulating layer/a gate electrode on the channel region, doping the first and the second region heavily with impurity, forming a metal film pattern making the first region a metal-offset, and crystallizing the semiconductor layer by means of applying thermal treatment to the semiconductor layer having the metal film.

Abstract: The invention relates to an ion implantation method for adjusting the threshold voltage of MOS transistors. The MOS transistor is employed in a DRAM (dynamic random access memory) memory cell in a semiconductor wafer and comprises a substrate, a gate insulating layer positioned on the substrate, and a gate conducting layer with a rectangular-shaped cross section positioned on the gate insulating layer. The method comprises performing an ion implantation process at a predetermined dosage and ion energy to implant dopants through the gate conducting layer and gate insulating layer and deposit the dopants into the superficial portion of the substrate below the gate insulating layer.

Abstract: Semiconductor devices are fabricated by providing a substrate; forming isolation regions in the substrate; forming a first insulating layer on the isolation regions and the substrate; forming a conductive-forming layer on the first insulating layer; forming a second insulating layer on the conductive layer; forming a resist layer on the second insulating layer; forming an opening through the resist down to the second insulating layer located vertically between the isolation region; removing the second insulating layer beneath the opening down to the conductive-forming layer; depositing a conductive material through the opening over the conductive layer; planarizing the second insulating layer and the conductive material; removing the second insulating layer, the conductive-forming layer and the first insulating layer except beneath the conductive material; and forming source/drain regions in the substrate; or by providing a substrate; forming isolation regions in the substrate; forming a first insulating laye

Abstract: A method of fabricating a semiconductor device wherein there is provided a semiconductor substrate, preferably of silicon, having a gate insulator thereover, preferably of silicon dioxide, forming a junction, preferably a silicon/silicon dioxide interface, and a gate electrode, preferably of doped polysilicon, over the partially fabricated device. Deuterium is implanted into the structure and the deuterium is caused to diffuse through the deivce. The device fabrication is then completed.

Abstract: MOS semiconductor devices of different conductivity types are formed on a semiconductor substrate using a minimal number of critical masks. Embodiments include forming conductive gates on the main surface of the semiconductor substrate, and disposable aluminum sidewall spacers on the side surfaces of the gates. A photoresist mask is then formed on gates and portions of the main surface intended to be implanted with impurities of a first conductivity type. Moderate or heavy source/drain implants of a second impurity type are then formed in the substrate, the aluminum sidewall spacers on the unmasked gates are then removed, and lightly or moderately doped source/drain extension implants of the second impurity type are formed in the substrate. The first mask is then removed and a second photoresist mask is formed on the previously uncovered gates and implanted portions of the main surface.

Abstract: A method for fabricating a transistor having a variable threshold voltage is disclosed. Energy levels of a transistor can be represented by a valance band, a conduction band, and a Fermi level. In order to fabricate a transistor with a variable threshold voltage, a region of the transistor is initially doped with a first dopant having a first energy level below the Fermi level. The region of the transistor is subsequently doped with a second dopant having a second energy level above the Fermi level. Alternatively, the region of the transistor can be initially doped with a first dopant having a first energy level above the Fermi level, and then the region of the transistor can be subsequently doped with a second dopant having a second energy level below the Fermi level.

Abstract: The invention encompasses integrated circuitry which includes a semiconductive material substrate and a first field effect transistor supported by the substrate. The first field effect transistor comprises a first transistor gate assembly which includes a first layer of conductively doped semiconductive material and only one layer of conductive nitride. The integrated circuitry further comprises a second field effect transistor supported by the substrate. The second field effect transistor comprises a second transistor gate assembly which includes a second layer of conductively doped semiconductor material and at least two layers of conductive nitride. The invention also encompasses a field effect transistor assembly which includes a channel region and an insulative material along the channel region. The transistor assembly further includes a gate stack proximate the channel region. The gate stack includes a first conductive nitride layer separated from the channel region by the insulative material.

Abstract: A method of fabricating an integrated circuit having an n-channel and a p-channel transistor is provided. The method includes forming LDD regions for the n-channel transistors self-aligned to the gate electrodes. A first oxide is then formed over the structure and the n-type silicon regions are implanting with a p+ type dopant through the first oxide to form the source and drain regions of the p-channel transistor. A second oxide is formed over structure. The two oxide layers are then etched to provide sidewall spacers, having an inner portion formed from the first oxide and an outer portion formed from the second oxide. The p-type silicon regions are implanted with an n+ type dopant to form the low resistivity regions of the n-channel transistor. The p+ implants in the source and drain of the p-channel transistor typically outdiffuse toward the gates during further thermal processing of the device.

Abstract: A method of fabricating a capacitor on a semiconductor substrate. A barrier layer is formed over the substrate to serve as a bottom electrode of the capacitor. A dielectric layer is formed on the barrier layer. An upper electrode is formed on the dielectric layer. In addition, the method can be used in a dynamic random access memory.

Abstract: Methods of electrically contacting to conductive plugs, methods of forming contact openings, and methods of forming dynamic random access memory circuitry are described. In one embodiment, a pair of conductive contact plugs are formed to project outwardly relative to a semiconductor wafer. The plugs have respective tops, one of which being covered with different first and second insulating materials. An opening is etched through one of the first and second insulating materials to expose only one of the tops of the pair of plugs. Electrically conductive material is formed within the opening and in electrical connection with the one plug. In a preferred embodiment, two-spaced apart conductive lines are formed over a substrate and conductive plugs are formed between, and on each side of the conductive lines. The conductive plug formed between the conductive lines provides a bit line contact plug having an at least partially exposed top portion.

Abstract: A method for fabricating a gate structure. The method involves providing a substrate, followed by forming a nitride region on a surface of the substrate. With a Tantalum (Ta)-based organic compound and a Titanium (Ti)-based organic compound serving as precursors, an organic metal chemical vapor deposition (OMCVD) is performed, so that a Ta2−xTixO5 dielectric layer is formed on the substrate. A barrier layer, a conducting layer, and an anti-reflection (AR) layer are then formed in sequence on the Ta2−xTixO5 dielectric layer. Subsequently, the AR layer, the conducting layer, the barrier layer, and the Ta2−xTixO5 dielectric layer are defined to form a gate structure on the substrate of the nitride region. The Ta-based organic compound in this case may include a Ta-alkoxide compound, whereas the Ti-based organic compound may include a Ti-alkoxide compound or a Ti-amide compound.

Abstract: A method for forming bit-line and charge-node contact holes that eliminates effects of misalignment when contact etching these holes. A liner is deposited that arrests the etch from burning through the deposited polysilicon and damage the word-line and passgate transistor of a DRAM structure should misalignment occur in the formation of these structures and their surrounding contact plugs. This liner at the same time relaxes restrictions of tolerance for the process of the creation of such holes.

Abstract: A method of forming a contact hole in a semiconductor device is provided wherein an oxide spacer is formed over a contact hole. The oxide contact hole spacer prevents an already-formed gate protecting spacer comprised of silicon nitride from being etched during a subsequent step of removing the already-formed silicon nitride etching stopper. After forming a gate stack having the protecting spacer, the silicon nitride etching stopper is formed. An interlayer insulating layer is formed thereon and a selected portion of the interlayer insulating layer is etched to form a contact hole. The oxide spacer is formed on both sidewalls of the contact hole and then the etching stopper silicon nitride layer is removed.

Abstract: A technique for forming an integrated circuit device having a self-aligned gate layer. The method includes a variety of steps such as providing a substrate, which is commonly a silicon wafer. Field isolation regions including a first isolation region and a second isolation region are defined in the semiconductor substrate. A recessed region is defined between the first and second trench isolation regions. The isolation regions are made using a reactive ion etching technique. A thickness of material such as polysilicon is deposited overlying or on the first isolation region, the second isolation region, and the active region. A step of selectively removing portions of the thickness of material overlying portions of the first isolation region and the second isolation region is performed, where the removing step forms a substantially planar material region in the recessed region. The substantially planar material region is self-aligned into the recessed region using the removing step.

Abstract: There is disclosed a method of manufacturing a flash memory cell comprising the steps of forming a first ploysilicon layer pattern then forms a cell source; patterning a second polysilicon layer so that a gate electrode can be formed while the portion of the first polysilicon pattern where the cell drain will be formed is opened; forming a transistor at peripheral circuit area by performing ion injection process and a thermal process; forming a floating gate and a control gate by performing a self aligned etching process; and forming a cell source line and a cell drain by injecting cell source/drain ions. The flash memory cell formed thus has an increased coupling ratio since the control gate is formed to surround the floating gate, and also has an improved hot carrier reliability characteristic both at the peripheral circuit and the cell area upon operation of the device since the cell drain is formed after the thermal process for forming the peripheral circuit source and drain.

Abstract: Process for manufacturing of an integrated structure including at least one circuitry transistor and at least one non-volatile EEPROM memory cell with relative selection transistor, including at least a first stage of growth and definition of a gate oxide layer on a silicon substrate, a second stage of definition of a tunnel oxide region in said gate oxide layer, a third stage of deposition and definition of a first polysilicon layer on said gate oxide layer and on said tunnel oxide region, a fourth stage of growth and definition of an intermediate dielectric layer on said first polysilicon layer, a fifth stage of selective etching and removal of said dielectric intermediate layer in a region for said circuitry transistor, a sixth stage of ionic implantation of a dopant with a first type of conductivity in order to introduce said dopant into a channel region for said circuitry transistor in order to adjust its threshold voltage, a seventh stage of deposition and definition of a second polysilicon layer on sai

Abstract: A method of fabricating a flash memory is provided. The flash memory structure is formed with buried bit lines that are lower in resistance, are shallower in buried depth into the substrate, and have a larger punchthrough margin than the prior art. The flash memory structure is constructed on a semiconductor substrate. A tunneling oxide layer is formed over the substrate. A plurality of floating gates is formed at predefined locations over the tunneling oxide layer. A plurality of sidewall spacers is formed on the sidewalls of the floating gates. A plurality of selective polysilicon blocks is formed over the substrate, each being formed between one neighboring pair of the floating gates. An ion-implantation process is performed to dope an impurity element through these selective polysilicon blocks into the substrate to thereby form a plurality of impurity-doped regions in the substrate to serve as a plurality of buried bit line for the flash memory device.

Abstract: Process for the manufacturing of a DMOS-technology transistor, providing for forming, over a semiconductor material layer of a first conductivity type, an insulated gate electrode, introducing in said semiconductor material layer a first dopant of a second conductivity type for forming at least one body region of a second conductivity type extending under the insulated gate electrode, and introducing in said at least one body region a second dopant of the first conductivity type for forming, inside said body region, at least one source region of the first conductivity type, said body region and said source region defining, under the insulated gate electrode, a channel region for the DMOS transistor, wherein said first dopant is aluminum. After the introduction of said first dopant and said second dopant, a single thermal diffusion process for simultaneously diffusing the first dopant and the second dopant is provided.

Abstract: Laminated layers including semiconductor or metal thin layers and insulative thin layers are formed on a substrate and after the laminated layers are patterned, the laminated layers are oxidized from their side to form an oxidized area. This way, a 0-dimensional quantum box or one-dimensional quantum line having fine tunnel junctions surrounded by the oxidized area and a 0-dimension quantum box or a one-dimensional quantum line made of semiconductor or metal area interposed between the oxidized area and the insulative thin layers are formed in the laminated layers.

Abstract: It is an object to compatibly realize a decrease in an on-state voltage and an increase in a current capable of turn-off. An N layer (43) having an impurity concentration higher than that of an N− layer (42) is formed between the N− layer (42) and a P base layer (44). In the exposed surface of the P base layer (44) connected to an emitter electrode (51), a P+ layer (91) having an impurity concentration higher than that of the P base layer (44) is formed. The formation of the N layer (43) allows the carrier distribution in the N− layer (42) to be close to the carrier distribution of a diode, so that the on-state voltage is decreased while maintaining high the current value capable of turn-off. Furthermore, the P+ layer (91) allows holes to easily go through form the P base layer (44) to the emitter electrode (51), which increases the current value capable of turn-off.

Abstract: A method of fabricating a mask ROM that includes forming a plurality of buried bitlines in an upper surface of a semiconductor substrate at fixed intervals and a plurality of wordlines on the semiconductor substrate perpendicular to the buried bitlines; forming an interlayer insulating film having a bitline contact hole on an entire first surface of the semiconductor substrate inclusive of the wordlines; forming a metal pattern in contact with the buried bitlines through the contact hole; forming a ROM code mask on the metal pattern; forming a plurality of ROM code ion implantation regions by selectively etching the interlayer insulating film with the ROM code mask; and forming a protection film on an entire second surface of the semiconductor substrate by implanting ROM code ions in the ROM code ion implantation regions.

Abstract: A method of setting a plurality of different threshold voltage levels to a plurality of cell regions for a mask programmable semiconductor device by carrying out a second impurity first-code selective ion-implantation, into at least a first-selected one of said plurality of cell regions doped with a first impurity to have a first threshold voltage level so that the at least the first-selected one of said cell regions has a second threshold voltage level which is different from the first threshold voltage level, the second impurity of the first-code selective ion-implantation being heavier than said first impurity so as to suppress any excess thermal diffusion to avoid variations in threshold voltage level of the cell regions.

Abstract: An integrated circuit and method of fabrication is provided for an integrated circuit having punch-through suppression. Unlike conventional methods of punch-through suppression wherein a dopant implant is fabricated in the device, the present invention utilizes an inert ion implantation process whereby inert ions are implanted through a fabricated gate structure on the semiconductor substrate to form a region of inert ion implant between source and drain regions of a device on the integrated circuit. This accumulation region prevents punch-through between source and drain regions of the device. In a second embodiment, the inert ion implantation is used in conjunction with the conventional punch-through dopant implant. In this second embodiment, diffusion of the implant during subsequent thermal annealing is suppressed by the inert ion accumulation in the subsurface region of the device.

Abstract: A method of fabricating a silicide layer on a gate electrode is described. A gate oxide layer is formed on a substrate. A gate electrode is formed on a portion of the gate oxide layer. A spacer is formed on a sidewall of the gate electrode to cover the other portion of the gate oxide layer. The spacer is removed to expose a portion of the gate oxide layer. A metallic layer is formed over the substrate to cover the gate electrode and the gate oxide layer. An annealing step is performed to transform the metallic layer in contact with the gate electrode and the source/drain region into a silicide layer. The remaining metallic layer is removed.

Abstract: Silicon device structures designed to allow measurement of important doping process parameters immediately after the doping step has occurred. The test structures are processed through contact formation using standard semiconductor fabrication techniques. After the contacts have been formed, the structures are covered by an oxide layer and an aluminum layer. The aluminum layer is then patterned to expose the contact pads and selected regions of the silicon to be doped. Doping is then performed, and the whole structure is annealed with a pulsed excimer laser. But laser annealing, unlike standard annealing techniques, does not effect the aluminum contacts because the laser light is reflected by the aluminum. Once the annealing process is complete, the structures can be probed, using standard techniques, to ascertain data about the doping step.

Abstract: A new method of fabricating an inductor utilizing air as an underlying barrier in the manufacturing of integrated circuits is described. A field oxide region is formed in and on a semiconductor substrate and then removed whereby a well is left in the semiconductor substrate. A polish stop layer is deposited over the substrate and within the well. The polish stop layer is covered and the well filled with a spin-on-glass layer. The spin-on-glass layer is polished back to the polish stop layer. The said polish stop layer is removed. A first oxide layer is deposited overlying the spin-on-glass layer and the semiconductor substrate and is patterned using an inductor reticle whereby a plurality of openings are made through the first oxide layer to the spin-on-glass layer. All of the spin-on-glass layer within the well is removed through the plurality of openings.

Abstract: In a method for manufacturing a semiconductor device having a mixture of a MOSFET and a low-resistance resistive element, after etching a tungsten silicide film which will serve as the resistive element to achieve a prescribed shape, thermal processing is performed for the purpose of activating a diffusion layer of the MOSFET, thereby achieving a low-resistance tungsten silicide film.

Abstract: A method of jointly forming stacked capacitors and antifuses includes, a) providing a common layer of electrically conductive material to form both a capacitor storage node and an inner antifuse plate; b) providing a common layer of dielectric material over the capacitor storage node and the inner antifuse plate, the common layer of dielectric material comprising both an intervening capacitor dielectric element and an intervening antifuse dielectric element, the common layer of dielectric material having a first breakdown voltage per unit length value for a given current per unit area; c) providing a common layer of electrically conductive material over the common layer of dielectric material to form both a capacitor cell layer and an outer antifuse plate; d) providing a lateral edge of the outer antifuse plate and a lateral edge of the intervening antifuse dielectric element; and e) depositing an antifuse breakdown layer of dielectric material over the lateral edges of the outer antifuse plate and the interv

Abstract: A fabrication method of a semiconductor device is provided, which makes it possible to introduce suitably a dopant into surface grains of a semiconductor layer at a comparatively low temperature. In the first step, a first semiconductor layer is formed over a semiconductor substrate through a first dielectric. In the second step, the first semiconductor layer is heat-treated to form semiconductor grains on a surface of the first semiconductor layer, thereby roughening the surface of the first semiconductor layer. The grains are made of a same material as that of the first semiconductor layer. In the third step, the first semiconductor layer with the semiconductor grains is heat-treated at a temperature of approximately 700° C. to 780° C. for a specific time in an atmosphere containing a gaseous dopant, thereby introducing the dopant into the semiconductor grains of the first semiconductor layer from the atmosphere.

Abstract: A process is disclosed for fabricating buried diffusion junction that can be combined with the shallow-trench isolation for the memory device cell unit transistor wherein both the junction and the isolation can be formed in the same layout. The buried diffusion is free from being inadvertently cut apart to cause open-circuiting. A bird's beak oxide layer is formed protecting the buried diffusion junction region from undesirable etching, thereby preventing from damaging consumption by etching. The buried diffusion junctions formed may serve as the source/drain region for the transistor.

Abstract: A method of producing a semiconductor device comprising the steps of: (a) forming partially an SOI structure portion comprising an insulation layer and a semiconductor layer on a semiconductor substrate; (b) forming selectively a first oxidation-resistant film on a region other than device isolation region-forming portions of the SOI structure portion and of an exposed portion of the semiconductor substrate; (c) forming an oxide film in the device isolation region-forming portions of the semiconductor substrate and of the SOI structure portion under such condition that the semiconductor layer of the SOI structure portion is oxidized up to the bottom of the semiconductor layer; (d) depositing a second oxidation-resistant film over the entire surface of the resultant obtained by the above steps (a) to (c); (e) etching away selectively the second oxidation-resistant film on the exposed portion of the semiconductor substrate using a resist mask so patterned as to cover the SOI structure portion; (f1) implanting a

Abstract: A method of minimizing mechanical stress generated during the trench-forming/trench-filling process steps in a standard shallow trench isolation (STI) process is provided. This is achieved by forming trenches with a more sloped and smoother profile, and/or limiting the trench depth to be less than 0.4 &mgr;m, and/or reducing or increasing the trench densification temperature, and/or performing the densification step after the chemical-mechanical polishing step. In addition, a furnace TEOS oxide film is used as the trench-filling material.

Abstract: A method of reducing a chemical mechanical polishing (CMP) dishing effect. A plurality of trenches are formed in the substrate, while a first insulating layer, such as silicon oxide layer is formed on the substrate to fill those trenches. A chemical reaction, such as nitridation reaction, is performed on the surface of the insulating layer to form a second insulating layer, which is harder than the first insulating layer. CMP is then performed.

Abstract: The stress dislocations formed in a substrate by semiconductor processing are significantly reduced, if not eliminated, by subjecting the substrate to a high temperature post sacrificial oxide anneal that causes viscous flow of the oxide over the substrate. In one example embodiment, a method of forming a semiconductor structure includes forming a first oxide layer over a substrate and forming a first dielectric material layer over the first oxide layer. An opening is then etched in the oxide and dielectric layers thereby exposing the substrate. A trench is formed with a desired depth in the substrate in the opening provided, followed by a deposition of an insulator material in the trench. The first dielectric layer and a portion of the insulator material is then removed leaving a portion of the insulator material within the trench. Applications include logic circuits having embedded-DRAM and circuits directed to stand-alone logic or stand-alone DRAM.

Abstract: A method for fabricating a shallow trench isolation structure is described, in which a pad oxide layer, a silicon oxy-nitride layer and the silicon nitride layer are sequentially formed on the substrate. Photolithography and etching are further conducted to form a trench in the substrate. A liner oxide layer is then formed on the exposed substrate surface in the trench, followed by removing portions of the silicon nitride layer and the silicon oxy-nitride layer by wet etching. After this, the trench is filled with an oxide material d the excessive oxide material is removed by using the silicon nitride layer as barrier layer. The remaining silicon nitride layer and the silicon oxy-nitride layer are further removed to complete the fabrication of a shallow trench isolation structure.

Abstract: A method of making a semiconductor device such as a diode or MOSFET provided in a thin semiconductor film on a thin buried oxide is disclosed, in which the lateral semiconductor device structure includes at least two semiconductor regions separated by a lateral drift region. A top oxide insulating layer is provided over the thin semiconductor film and a conductive field plate is provided on the top oxide insulating layer. In order to provide enhanced device performance, a portion of the top oxide layer increases in thickness in a substantially continuous manner, while a portion of the lateral drift region beneath the top oxide layer decreases in thickness in a substantially continuous manner, both over a distance which is at least about a factor of five greater than the maximum thickness of the thin semiconductor film.

Abstract: There are provided a method of producing an SOI wafer of high quality with excellent controllability, productivity and economy and a wafer produced by such a method. In the method of producing a substrate utilizing wafer bonding, a first substrate member and a second substrate member are mutually bonded, and then the second substrate member is separated from the first substrate member at the interface of a first layer and a second layer formed on the main surface of the first substrate member, whereby the second layer is transferred onto the second substrate member. In the separation, the separation position at the interface of the first and the second layers is ensured by varying the porosity of a porous Si layer, forming an easily separable plane by the coagulation of pores in porous Si, effecting ion implantation to the interface or utilizing a heteroepitaxial interface.

Abstract: In accordance with the present invention, a preferred method for bonding a single crystal membrane to a supporting structure having a curved surface includes the steps of segmenting a unitary wafer of a single crystal, for example semiconductor material, into a plurality of semi-attached wafer segments and then aligning a supporting structure with each of the wafer segments. The wafer segments are then detached from each other and are individually bonded to one of the supporting structures. In the case of silicon, lattice strain each of the segments is relieved by depositing a layer of germanium onto the surface of the silicon membrane and then thermally processing the assembly so that germanium atoms are either nucleate on the surface to form quantum wires or diffused into the lattice to relieve the lattice strain.