Abstract: An integrated circuit package includes a semiconductor chip, a plurality of wired pins, and at least one non-wired pin. The size of the non-wired pin is minimized, or the non-wired pin is eliminated, in order to increase the lead pin spacing. The increase in lead pin spacing prevents electrostatic discharge failure in an integrated circuit package due to electrostatic stressing of the non-wired pin.

Abstract: A process is provided for the fabrication of a plastic molded type semiconductor device in which a die pad is formed to have a smaller area than a semiconductor chip to be mounted on a principal surface of the die pad and the semiconductor chip and die pad are sealed with a plastic mold.

Abstract: A semiconductor wafer processing system including a multi-chamber module having vertically-stacked semiconductor wafer process chambers and a loadlock chamber dedicated to each semiconductor wafer process chamber. Each process chamber includes a chuck for holding a wafer during wafer processing. The multi-chamber modules may be oriented in a linear array. The system further includes an apparatus having a dual-wafer single-axis transfer arm including a monolithic arm pivotally mounted within said loadlock chamber about a single pivot axis. The apparatus is adapted to carry two wafers, one unprocessed and one processed, simultaneously between the loadlock chamber and the process chamber. A method utilizing the disclosed system is also provided.

Abstract: The present invention provides an electronic package assembly in which a ball grid array (BGA) is surface mounted to a printed wiring board using solder balls. Tubing is placed along the perimeter of the BGA housing to prevent subsequently applied sealant from contacting the solder balls or filling the gap between the BGA housing and the printed wiring board. This results in a seal that prevents electrical disconnection in the solder joint during operation of the electronic package assembly.

Abstract: A method for producing a color CMOS image sensor including a matrix of pixels (e.g., CMOS APS cells) that are fabricated on a semiconductor substrate. A silicon-nitride layer is deposited on the upper surface of the pixels, and is etched using a reactive ion etching (RIE) process to form microlenses. A protective layer including a lower color transparent layer formed from a polymeric material, a color filter layer and an upper color transparent layer are then formed over the microlenses. Standard packaging techniques are then used to secure the upper color transparent layer to a glass substrate.

Abstract: A thin film transistor is provided that includes a substrate, a gate electrode formed on the substrate, and a gate insulating layer formed all over the substrate including the gate electrode. A first semiconductor layer is formed on the gate insulating layer, and a second semiconductor layer is formed on the first semiconductor layer. Source and drain electrodes are separately etched together to expose a prescribed portion surface of the second semiconductor layer over the gate electrode. The source and drain electrodes adjacent to the prescribed portion of the second semiconductor layer are non-linearly inclined at their edges. A method of fabricating a thin film transistor includes forming a gate electrode on a substrate; forming a gate insulating layer on the gate electrode and the substrate, forming a first semiconductor layer on the gate insulating layer and forming a second semiconductor layer on the first semiconductor layer.

Abstract: The invention discloses a method of forming an ESD protection device without adding the extra mask layers into the traditional CMOS process. At first, P-wells, N-wells, and isolations are formed in a semiconductor substrate. Next, an NMOS transistor with a gate dielectric layer, a gate electrode, source/drain regions, lightly doped source/drain regions, and insulator spacers is formed on the substrate. Particularly, N-wells are also formed in a part of the source/drain regions of the NMOS transistor. Thereafter, ESD protection regions are formed under the source/drain regions by performing P+ ESD protection implantation. Such ESD protection device has a low junction breakdown voltage, quick response speed, and a small junction capacitance.

Abstract: A method for fabricating an improved metal-insulator-metal or metal-insulator-polysilicon capacitor having high capacitance density and low noise is achieved. An insulating layer is provided overlying a semiconductor substrate. A capacitor bottom plate electrode is formed overlying the insulating layer. A thin capacitor dielectric layer is deposited overlying the capacitor bottom plate electrode. An etch stop layer is deposited overlying the capacitor dielectric layer. A thick oxide layer is deposited overlying the etch stop layer. The oxide layer over the capacitor bottom plate electrode is etched away stopping at the etch stop layer whereby a recess is formed in the oxide layer overlying the bottom plate electrode wherein sidewalls of the oxide layer overlie the edges of the bottom plate electrode.

Abstract: A method for manufacturing a semiconductor device for use in a memory cell including the steps of preparing an active matrix provided with at least one transistor, a plurality of conductive plugs electrically connected to the transistors and an insulating layer formed around the conductive plugs; patterning the insulating layer into a first predetermined configuration to form contact holes; forming a diffusion barrier layer on an entire surface including the contact holes; forming a seed layer on top of the diffusion barrier layer; forming a first conductive layer and a conductive plug on top of the seed layer; carrying out a thermal treatment for changing grains of the conductive plug into a granular type; removing the first conductive layer, the diffusion barrier layer, and the seed layer until a top surface of the insulating layer is exposed; forming a second conductive layer on the conductive plug and the diffusion barrier layer; patterning the second conductive layer into a second predetermined configura

Abstract: An integrated circuit and fabrication method includes a vertical transistor for a memory cell in a dynamic random access memory (DRAM) or other integrated circuit Vertically oriented access transistors are formed on semiconductor pillars on buried bit lines. Buried gates and body contacts are provided for each access transistor on opposing sides of the pillars. Buried word lines extend in first alternating trenches orthogonal to the bit lines. The buried word lines interconnect ones of the gates. Buried body lines extend in second alternating trenches orthogonal to the bit lines. The buried body lines interconnect body regions of adjacent access transistors. Unitary and split-conductor gate and body lines are provided for shared or independent signals to access transistors on either side of the trenches. In one embodiment, the memory cell has a surface area that is approximately 4 F2, where F is a minimum feature size. Bulk-semiconductor and semiconductor-on-insulator (SOI) embodiments are provided.

Abstract: A method for fabricating a conducting structure for a semiconductor device is described. A first dielectric layer is formed on a substrate. The first dielectric layer is etched by using a first photoresist layer, to form original contact holes for exposing surface of the substrate. The first dielectric layer is etched by using a second photoresist layer which is aligned with desired contact holes selected from the original contact holes, to broaden top region of part of the desired contact holes as offset landing regions. A conductive layer is deposited in the desired contact holes, which includes the offset landing region, original contact holes, and on the first dielectric layer. Surface of the conductive layer is planarized to expose the first dielectric layer. In this planarization, original contact structures and desired contact structures having landing plugs are formed, which landing plugs are defined by the first and second photoresist layer.

Abstract: A method of fabricating a semiconductor capacitor is disclosed. An impurity layer is formed on a semiconductor substrate. An interlayer insulating film is disposed on an upper surface of the impurity layer and the semiconductor substrate. A contact hole is selectively etched through the interlayer insulating film to the impurity layer. A conductive plug is formed in the contact hole. A metal film pattern having an irregular surface area is disposed on the conductive plug. A dielectric substance film is located directly on the irregular surface of the metal film pattern. A metal electrode is formed on the dielectric substance film.

Abstract: The present invention provides a novel integrated circuit device, which has a flash memory cell. The flash memory cell (100) has a tunnel dielectric layer (113) overlying a surface of a semiconductor substrate. A floating gate layer (107) is defined overlying the tunnel dielectric layer. The gate layer has an edge defined thereon, where a sidewall spacer (108) extends along and on the edge. The sidewall spacer includes a first portion defined adjacent to the edge and a second portion extending from the first portion to a region substantially outside the edge. The combination of the sidewall spacer and the gate layer provide a novel surface for increasing gate coupling ratio.

Abstract: A method of forming contact holes of a semiconductor device wherein process yield is improved and manufacturing processes can be simplified. First, a plurality of gate electrodes provided with a plurality of spacers are formed on an active region of a semiconductor substrate that is separated into the active region and a field region by a field oxide layer. Then, the outermost spacers are removed from the plurality of spacers, to ensure a space for a first contact hole on the semiconductor substrate. Next, an etch stopping layer and an interlayer dielectric are subsequently formed on the semiconductor substrate.

Abstract: A method of fabricating a field effect transistor, wherein a substrate with a gate is provided. A liner oxide layer and a first spacer are formed adjacent to the sides of the gate. An epitaxial silicon layer is formed at both sides of the gate in the substrate, while a shallow source/drain (S/D) extension junction is formed in the substrate below the epitaxial silicon layer. An oxide layer and a second spacer are formed to be closely connected to the first spacer and form the S/D region below the epitaxial silicon layer. A part of the epitaxial silicon layer is then transformed into a metal silicide layer, so as to complete the process of the field effect transistor.

Abstract: A bipolar transistor is described whose I-V curve is such that it operates in two regions, one having low gain and low power consumption and another having higher gain and better current driving ability. Said transistor has a base region made up of two sub regions, the region closest to the emitter having a resistivity about an order a magnitude lower than the second region (which interfaces with the collector). A key feature of the invention is that the region closest to the collector is very uniformly doped, i.e. there is no gradient or built-in field present. In order to produce such a region, epitaxial growth along with boron doping is used rather than more conventional techniques such as ion implantation and/or diffusion.

Abstract: A method of dissipating charge from a substrate of an SOI device is provided wherein a charge dissipation path is formed in the device so that it abuts the various layers thereof. Exemplary charge dissipation paths include high conductive materials, resistive means, and field emission or arc discharge means. SOI structures having said charge dissipation path formed therein are also provided. SOI ESD circuits between SOI substrate and chip ground Vss are provided herein.

Abstract: A method for fabricating a bottom electrode structure for a semiconductor capacitor. The method according to the present invention includes providing an interlayer insulating layer having a conductive plug formed therein. A first bottom electrode layer is formed on the interlayer insulating layer. An oxygen diffusion barrier layer is formed on the first bottom electrode layer. A second bottom electrode layer is formed on the first oxygen diffusion barrier layer. Thereafter, portions of the second bottom electrode layer, first oxygen diffusion barrier layer, and first bottom electrode layer are selectively removed to form a bottom electrode pattern. A third bottom electrode is formed on side walls of the bottom electrode pattern.

Abstract: The present invention provides a method of manufacturing a semiconductor device, comprising the steps of forming a gate insulating film, on a semiconductor substrate, forming a gate electrode containing a refractory metal layer on the gate insulation film, and heat-processing the semiconductor substrate in an atmosphere containing water vapor and hydrogen, to lessen a damage caused to a portion of the semiconductor substrate, which is located close to an end portion of the gate electrode. The heat-processing step is carried out while controlling a vapor pressure of a refractory metal oxo-acid generated on a surface of the high-melting metal layer.

Abstract: A method for suppressing boron penetrating the gate dielectric layer by pulsed nitrogen plasma doping. A pulsed nitrogen plasma doping process is utilized to dope nitrogen ions into the surface layer in the channel region of the semiconductor substrate. A thermal oxidation step is then performed to form a gate dielectric layer commixed with oxide and oxynitride over the channel region of the semiconductor substrate to avoid boron penetration effect accruing while a boron doped polysilicon layer is subsequently formed on the gate dielectric layer.

Abstract: A semiconductor processing method of making electrical connection between an electrically conductive line and a node location includes, a) forming an electrically conductive line over a substrate, the substrate having an outwardly exposed silicon containing node location to which electrical connection is to be made, the line having an outer portion and an inner portion, the inner portion laterally extending outward from the outer portion and having an outwardly exposed portion, the inner portion having a terminus adjacent the node location, and b) electrically connecting the extending inner portion with the node location. An integrated circuit is also described. The integrated circuit includes a semiconductor substrate, a node location on the substrate, and a conductive line over the substrate which is in electrical communication with the node location. The conductive line includes an outer portion and an inner portion.

Abstract: Methods of forming contact openings, making electrical interconnections, and related integrated circuitry are described. Integrated circuitry formed through one or more of the inventive methodologies is also described. In one implementation, a conductive runner or line having a contact pad with which electrical communication is desired is formed over a substrate outer surface. A conductive plug is formed laterally proximate the contact pad and together therewith defines an effectively widened contact pad. Conductive material is formed within a contact opening which is received within insulative material over the effectively widened contact pad. In a preferred implementation, a pair of conductive plugs are formed on either side of the contact pad laterally proximate thereof. The conductive plug(s) can extend away from the substrate outer surface a distance which is greater or less than a conductive line height of a conductive line adjacent which the plug is formed.

Abstract: A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry, and forming a via in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In another specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.

Abstract: Silicide interfaces for integrated circuits, thin film devices, and backend integrated circuit testing devices are formed using a barrier layer, such as titanium nitride, disposed over a porous, thin dielectric layer which is disposed between a silicon-containing substrate and a silicidable material which is deposited to form the silicide interfaces for such devices. The barrier layer prevents the formation of a silicide material within imperfections or voids which form passages through the thin dielectric layer when the device is subjected to a high temperature anneal to form the silicide contact from the reaction of the silicidable material and the silicon-containing substrate.

Abstract: Methods, apparatuses and substrate assembly structures for mechanical and chemical-mechanical planarizing processes used in the manufacturing microelectronic-device substrate assemblies. One aspect of the invention is directed toward a method for planarizing a microelectronic-device substrate assembly by removing material from a surface of the substrate assembly, detecting a first change in drag force between the substrate assembly and a polishing pad indicating that the substrate surface is planar, and identifying a second change in drag force between the substrate assembly and the polishing pad indicating that the planar substrate surface is at the endpoint elevation. After the second change in drag force is identified, the planarization process is stopped.

Abstract: Provided is a method for producing regularly ordered narrow pores excellent in linearity, and a structure with such narrow pores. A method for producing a narrow pore comprises a step of radiating a particle beam onto a workpiece, and a step of carrying out anodic oxidation of the workpiece having been irradiated with the particle beam, to form a narrow pore in the workpiece.

Abstract: After forming a processed film onto the underlying film formed on the substrate, the processed film is dry etched using a mask pattern so as to form an etched pattern. After the reaction product deposited on a wall of the etched pattern is removed by using the first cleaning solution having relatively low power to etch the processed film and the second cleaning solution having relatively high power to etch the processed film in that order, the etched pattern or its vicinity is rinsed with water.

Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.

Abstract: A method and system for providing a semiconductor device is disclosed. The method and system include depositing an antireflective coating (ARC) layer having antireflective properties. The method and system also include depositing a capping layer on the ARC layer. The capping layer reduces a susceptibility of the ARC layer to removal while allowing the ARC layer to substantially retain the antireflective properties.

Abstract: An electrical connection box has upper and lower casings capable of being combined with each other, a wiring board located between the casings and having a plurality of independent electric circuits, and an insulating plate located between the upper casing and the wiring board. The upper casing is formed with a connector housing to be fitted with an external connector, and external connecting terminals coupled to the electric circuits and electrically connecting the electric circuits and the external connector or an L-shaped rib formed on the wiring board and capable of preventing the external connector from being fitted in the connector housing projects into the connector housing.

Abstract: An electrical connector, comprising: a housing; and a plurality of modules received in said housing. Each module comprises: a printed circuit board assembly; and a plurality of contact secured to ends of traces located on outer surfaces of the printed circuit board assembly. The printed circuit board assembly also includes at least one shield layer located between the outer surfaces. A first group of the contacts engage a mating electrical component, and a second group of the contacts engage a circuit board to which the electrical connector mounts.

Abstract: An electrical connector, comprising: a housing; a plurality of signal contacts extending from said housing; and a plurality of ground contacts. Each ground contact has: an L-shaped section located within the housing that shields at least one signal contact from the other signal contacts; and a mating section extending from said housing. The header could have a differential pair arrangement of pairs of columns of signal contacts extending from the housing; and columns of ground contacts flanking the pairs of columns of signal contacts. Two columns of ground contacts preferably flank each side of two columns of signal contacts.

Abstract: A socket for receiving a semiconductor component (10) having an electric terminal (12) comprises a contact (31), to which the electric terminal is connected, and a driving mechanism for moving the contact (31) toward the electric terminal (12) when the semiconductor component is inserted into an insertion position in the socket. The driving mechanism has a movable separation member (40) for keeping the contact (31) away from the insertion position of the semiconductor component (10) when the semiconductor component is not inserted in the socket. The socket also has a spring (50) which is compressed as the semiconductor component (10) is inserted, and pushes back the movable separation member (40) toward the semiconductor component.

Abstract: A locking connector is provided for electrically interconnecting first and second electrical conductors. The connector includes an enclosure that accommodates an electrical contact component electrically interengaged with the first conductor. At least two spring locking clips are mounted in the enclosure and serially arranged to face away from the inlet such that the clips are sequentially and resiliently opened by introducing the second conductor into the enclosure through the inlet. The clips are spring biased to grip the second conductor at a plurality of locations and hold the second conductor in electrical interengagement with the contact component. This enables the second conductor to resist disengagement from the contact component.

Abstract: In a wire module (1), a terminal (4, 5) is pressed to be clamped to each of opposite end portions of a wire (6) to thereby provide a terminal-assembled wire member (2), and molded connector members (10, 11) and a wire circuit member (12) are formed in such a manner that a plurality of terminal-assembled wire members are arranged in an insulative covering layer (3). In the case where the terminals (4) are of the female type, the molded connector member comprises a connector housing, in which the terminal-assembled wire members (2) are inserted, and a terminal holder attached to a terminal-inserting side of the connector housing. The connector housing is of the waterproof type, and includes a waterproof wall which is formed in a bulged manner on an outer peripheral surface of a housing body, receiving the terminals therein, and extends in a direction away from the terminal-inserting side.

Abstract: A smart card connector includes an insulative support (52) with a horizontal card-engaging face (62) and contacts mounted on the support and having contact ends (102) projecting above the face to engage pads on the active face of a smart card. The pad-engaging ends lie within a contact-holding face part (202) which has a longitudinal length (L1) not greater than half the length of the card, with the card rear portion extending in a cantilevered fashion rearward of the contact-holding face part. The support has a rear edge (84), with the contacts having tails (104) lying at the rear edge, and with the tails protected by side guide extensions (88, 90). A card hold-down includes a sheet metal cover (54) that is soldered to a circuit board P on which the support lies. A switch (150) that detects full card insertion, lies in a polarized region (220) adjacent to the polarized wall (98) of the support.

Abstract: A compact electrical connector can receive two different kinds of circuit cards, of the type that are thin and flat and have contact pads on an active face, such as a MICROSIM card and a MMC card. The connector includes a body (52) with an insulative frame (81) and two sets of contacts (84, 114) on the frame, with each set of the contacts having pad-engaging ends arranged in patterns corresponding to the patterns of contact pads on the two types of circuit cards. A card-holder unit (54) has first and second card-holding compartments lying in horizontal planes that are vertically spaced. The cards can be inserted into the compartments and the unit is then slid into the body until pads of the two cards engage the two sets of contacts on the body.

Abstract: A joint connector for connection to first, second and third exterior electrical connectors, e.g. in a wire harness, has an insulation plate with parallel first bus bars on one face providing a set of first connection tabs and parallel second bus bars on a second face crossing the first bus bars. The second bus bars at opposite ends thereof constitute second and third sets of connection tabs. The first and second bus bars are electrically connected via through holes in the insulation plate to form a circuit in the joint connector. The insulation plate and bus bars are in a casing. In use the first connection tabs connect to a first exterior connector, while the sets of second and third tabs connect to respectively second and third exterior connectors. The interior circuit is such that the circuit connections from the first connection tabs to the second connector tabs and to the third connector tabs respectively are identical.

Abstract: A connector connecting structure of the present invention comprises: first connecting means 11 having a first engaging projection 14 provided on one of connector housings 2 and 3 and having a tapered portion 21 on the side of a wall 19 of a head 20, a first locking portion 16 provided on the other surface of the other connector housing 3 and the tapered portion 21 being locked to the first locking portion 16; and second connecting means 12 having a second engaging projection 24 provided on one surface of the connector housing 2 and including a hook 27, and a second locking portion 26 provided on the other surface of the other connector housing 3 opposed to any one surface of the one connector housing 2 and having a locking surface 29 that is perpendicular to a direction to an engaging direction, the hook 27 is locked to the second locking portion 26 in a state in which the connector housings 2 and 3 are laminated on each other.

Abstract: A waterjet-driven boat has a reversing bucket for controlling forward/reverse thrust and a rotatable nozzle for controlling sideward forces. A bucket position sensor is connected to the reversing bucket, and the bucket is controlled using the output of the position sensor to enable the bucket to be automatically moved to a neutral thrust position. Similarly, a nozzle position sensor is connected to the nozzle, and the nozzle is controlled using the output of the nozzle position sensor so that the nozzle may be automatically returned to a zero sideward force position. A joystick with two axes of motion may be used to control both the bucket and the nozzle. The joystick has built-in centering forces that automatically return it to a neutral position, causing both the bucket and nozzle to return to their neutral positions.

Abstract: A watercraft includes a lubrication system having a lubricant pump assembly and a lubrication reservoir defined between a lower crankcase member and an oil cover. At least one oil passage connects a crankcase to the reservoir. The oil cover, or both the oil cover and the crankcase member may contain one or more baffles configured to impede a flow of oil away from the lubricant pump assembly. Additionally, the cover may include one or more projections securing one or more plugs within one or more countersink portions of the crankcase member.

Abstract: A wettable fiber or filament comprises a melt additive to a thermoplastic polyolefin such as polypropylene.

Abstract: A wettable fiber or filament comprises a melt additive to a thermoplastic polyolefin such as polypropylene.

Abstract: An electrode structure for a display device comprising a gate electrode proximate to an emitter and a focusing electrode separated from the gate electrode by an insulating layer containing a ridge. When the focusing electrode is an aperture-type electrode, the upper surface of the ridge protrudes closer to the emitter than the sidewall of the gate electrode or the sidewall of the focusing electrode. When the focusing electrode is a concentric-type electrode, the ridge protrudes above the upper surface of the gate electrode or the upper surface of the focusing electrode. A method for making the aperture-type and concentric-type electrode structures is described. A display device containing such electrode structures is also described. By forming an insulating ridge between the gate and focusing electrodes, shorting between the two electrodes is reduced and yield enhancement increased.

Abstract: An element for constructing a structure by detachably connecting a plurality of the elements in edge-to-edge relationship is disclosed. The element comprises a plurality of margins, with at least one of the margins being an arcuate margin. Each margin comprises at least two projections having a recess therebetween. An end-face of one projection is formed with a protruding hinge-pip and an end-face of the other or another projection is formed with a recessed hinge-socket. The arcuate margin is adapted to mate with a complementary margin of another element with the hinge-pip of each element being urged into the hinge socket of the other element.

Abstract: The invention relates to a method and a device for open-loop control of the speed of an electrically driven toy car on a lane-guided racetrack. By means of a hand-actuatable closed-loop control device, the speed of the toy car can be adjusted to at least two speed levels. To adjust the magnitude of the first speed level as a fraction of the second speed level, the closed-loop control device is preferably programmable so that via the open-loop control device, the speed of the toy car is adjusted between a zero position and the first speed level and, after actuation of a selection switch, the speed of the traveling toy is adjustable between the zero position and the second speed level. The invention permits the adjustment of partial speeds of a toy car on a racetrack without using a transformer.

Abstract: An amusement device used to move a supported display object through an erratic path. The amusement device includes a base element in which is disposed a rotating assembly. A support spring is used to interconnect a display object to the rotating assembly in the base element. The support spring has a first end and a second end. The first end of the support spring is coupled to the rotating assembly within the base element, wherein the support spring is rotated by the rotating assembly. The remainder of the support spring extends freely from the base element. The display object is coupled to the second end of the support spring. As the display object rotates, it causes the support spring to oscillate, thereby causing the display object to move erratically from point to point.

Abstract: An amusement device used to move a supported display object through an erratic path. The amusement device includes a base element in which is disposed a vibration mechanism. A support spring is used to interconnect a display object to the vibration mechanism in the base element. The support spring has a first end and a second end. The first end of the support spring is coupled to the vibration mechanism in the base element. The remainder of the support spring extends freely from the base element. The display object is coupled to the second end of the support spring. As the display object vibrates, it causes the support spring to oscillate, thereby causing the display object to move erratically from point to point.

Abstract: A polishing apparatus includes an arrangement of a plurality of units to deal with various operations and a robot having at least one arm. The plurality of units are disposed around the robot and include a loading unit for receiving thereon a, e.g. dry, workpiece to be polished, a polishing system including at least one polishing unit for polishing the workpiece, a washing system and a drying system at least including one washing unit for washing and drying the polished workpiece, and an unloading unit for receiving thereon a resultant clean and dry polished workpiece.

Abstract: A polishing apparatus includes an arrangement of a plurality of units to deal with various operations and a robot having at least one arm. The plurality of units are disposed around the robot and include a loading unit for receiving thereon a, e.g. dry, workpiece to be polished, a polishing system including at least one polishing unit for polishing the workpiece, a washing system and a drying system at least including one washing unit for washing and drying the polished workpiece, and an unloading unit for receiving thereon a resultant clean and dry polished workpiece.