Abstract: A clock recovery circuit is provided for use in a memory with a clock synchronized interface, wherein an external clock is temporarily intercepted to shorten lock-in time when an internal clock is to be generated from the external clock. The clock recovery circuit includes a delay circuit array, receiving the external clock, for generating reference clocks, a control circuit comparing phases of the external clock and of the reference clocks and detecting the number of delay stages required for locking in, and a latching circuit for holding the number of delay stages required for locking in. Once synchronism is detected, the generation of internal clock can be resumed in a short period of time even if the supply of the external clock is temporarily suspended.

Abstract: An integrated circuit electrically is supplied with a voltage and includes an output MOS transistor having a gate driven by an output of a logic circuit and a circuit for biasing the gate of the output MOS transistor. The circuit for biasing the gate is provided for lowering a gate-source bias voltage of the output MOS transistor in a conductive state in relation to the gate-source bias voltage that would otherwise be provided by the output of the logic circuit. The present invention is particularly applicable to output stages for I2C buses.

Abstract: An object of the present invention is to provide a waveform shaping circuit by which the duty factor of clock pulses can be set to 50% with high accuracy even if the clock pulses are of a low voltage and a high frequency.

Abstract: A D-FF circuit for operating a master flip-flop and a slave flip-flop at each predetermined timing in accordance with a plurality of clock signals generated by a clock signal generating circuit, wherein the clock signal generating circuit generates the plurality of clock signals at different timings, the slave flip-flop starts operating in accordance with a clock signal which is generated at an earlier timing than another clock signal generated by the clock signal generating circuit, and the master flip-flop stops operating in accordance with a clock signal which is generated at a later timing than another clock signal generated by the clock signal generating circuit.

Abstract: Flip-flop circuits FF1 to FF6 are each constructed as a pair of cascade connected latch circuits 21 and 22 in an arbitrarily combination. The latch circuits L1 and L2 each comprises an input stage push-pull circuit PP and an output stage hold circuit HD as CVSL circuit. The latch circuit L1 includes an input stage having two pairs of nMOSTs 2 to 5 receiving input data DP and DN inputted thereto and connected in series each and in parallel connection of the pairs and a pair of nMOSTs 1 to 6 receiving a clock CP inputted thereto and connected to the opposite sides of the parallel connection. The output stage hold circuit HD includes a CVSI circuit having two pairs of nMOSTs 7 and 10 and a pair of pMOSTs 12 and 13 and an nMOST 11 receiving a clock CN inputted thereto. Thus obtained flip-flop (FF) circuit permits construction of a high density semiconductor integrated circuit (IC) with fast operation and low power consumption.

Abstract: A pulse generator, which only occupies a small area in a circuit chip by using a characteristic that the potential in both ends of a capacitor is maintained. The pulse generator comprises a voltage level control unit for controlling a voltage level of a first node according to the state of input signal; a first switching unit for controlling a voltage level of a second node by performing a switching operation according to the state of the input signal; a second switching unit for changing a voltage level of the second node by performing another switching operation, opposite to the first switching means according to the state of the input signal; a charge/discharge unit for charging/discharging a voltage between the first and the second nodes according to the switching state of the first and the second switching means; and an output unit for outputting a pulse signal according to the charging/discharging state of the charge/discharge means.

Abstract: A circuit extends the output voltage range of an integrator circuit wherein the input signal is used to produce an output signal, and the voltage of the output signal develops monotonically within a predetermined range of possible values. The integrator circuit is driven within an integration time period such that each time the signal at its output reaches a limit of the range of values, the integrator circuit starts a subsequent integration stage of the input signal in which the output signal develops again within the above-mentioned range. This takes place by resetting the integrator circuit or by a reversal of the characteristic slope of the output signal. This is combined with storing the number of occasions on which these interventions have occurred as determined by a counter.

Abstract: The load pump booster device with transfer and recovery of the charge including a charge pump circuit with an output terminal connected to a load capacitor by means of a load node. In turn, the charge pump circuit includes a plurality of transfer transistors connected to one another in series, and define a plurality of transfer nodes. Each transfer node is connected to a storage capacitor. The booster device also includes a plurality of controlled switches interposed between the load node and a respective transfer node, in order to connect to the load node a single one of the transfer nodes. By this means, between the load capacitor and the storage capacitors there takes place a phase of transfer of charge followed by a phase of recovery of charge, from the storage capacitors to the load capacitor.

Abstract: A charge pump type voltage conversion circuit comprises a voltage detector which detects whether a boosted output voltage is larger or smaller than a predetermined reference voltage. A clock generator generates a clock signal based on the result of detection by the voltage detector. A charge pump circuit produces the boosted output voltage in response to the clock signal. A transfer control circuit allows or inhibits transfer of the clock signal to the charge pump circuit depending on the result of detection by the voltage detector. When the condition of the transfer control circuit is changed from the inhibited condition to the allowed condition based on the clock signal outputted from the clock generator, an operation of the charge pump circuit always starts from a voltage boost sequence, thereby reducing a ripple components of the boosted output voltage.

Abstract: An internal voltage generation circuit with a small area, which has many correction points and can provide an output voltage with a high precision, has been disclosed. In this internal voltage generation circuit, some resistors, among the resistors which are connected in series constituting the feedback circuit, have different resistance and transfer gates are provided in parallel to the resistors of different resistance. This configuration has a decode function and, therefore, the decoder can be eliminated and the number of sets of an inverter, a transfer gate, and a resistor can also be reduced, resulting in a reduction in area without a reduction in the number of the correction points.

Abstract: A semiconductor integrated circuit comprising a first circuit block including an oscillation circuit considered to be a noise generator and a second circuit block including circuits considered to be easily affected by a noise generated by the oscillation circuit, being most likely led to a malfunction are created on a single semiconductor substrate with the first and second circuit blocks separated from each other. To put it more concretely, the first and second circuit blocks are respectively created in a first island area and a second island area on the surface of the semiconductor substrate. The first and second island areas are each enclosed by an insulating isolation band. A low-resistance semiconductor area is created in a base area excluding locations occupied by active elements in the first and second island areas and is connected to a stable voltage terminal.

Abstract: An amplifier circuit for a physical random number generator for amplifying a very small signal to generate a physical random number signal includes a pair of first differential input terminals including a first non-inverted input terminal TVin1+ and a first inverted input terminal TVin1−, a pair of second differential input terminals including a second non-inverted input terminal TVin2+ and a second inverted input terminal TVin2−, a differential amplifying section for receiving signals respectively from said pairs of first and second differential input terminals and for producing differential output signals in a form of a linear combination of the input signals, and a first pair of differential output terminals including a first inverted output terminal TVO− and a first non-inverted output terminal TVO+ to output the differential output signals. This configuration increases performance of the amplifier circuit for a physical random number generator.

Abstract: According to the present invention, there is provided a strain compensation amplifier which realizes miniaturization, loss reduction, and cost reduction.

Abstract: The present invention relates to a conversion circuit that converts a single-ended signal to differential signals. According to an embodiment of the present invention, crosstalk is avoided by insuring that none of the transistors in the conversion circuit are directly connected to ground. By not having a transistor directly connected to ground, ground current is avoided and crosstalk associated with ground current is eliminated.

Abstract: A phase-locked loop (PLL) 1 is provided with means for changing the frequency of the output signal to a desired frequency. The PLL 1 is operated during a first period with a feedback frequency division ratio set to an initial value N′ which controls the conduction time of the charge pumps during a first period having a predetermined length to place an amount of charge on the loop filter 6 during the first period sufficient to produce a control voltage for controlling the voltage-controlled oscillator 10 to output an output signal substantially at the desired output frequency. At the end of the first period, the feedback loop 11 is opened by disabling the charge pump 5 for a second period to allow the control voltage output from the loop filter 6 to settle. Subsequently the feedback loop 6 is closed and the feedback frequency division ratio is set to a proper value N2 such that operation of the PLL 1 subsequent to the second period locks the output frequency to the desired frequency.

Abstract: A programmable crystal oscillator is provided having a memory for storing frequency-defining parameters. Typically, one of these parameters is used to program an adjustable capacitive load circuit coupled to a crystal to thereby adjust the crystal source frequency. Additional parameters are used to program the output frequency of a phase locked loop circuit coupled to receive the adjusted source frequency. A further parameter can also be used to divide the output frequency of the phase locked loop circuit to supply a specified output frequency. The oscillators can be manufactured as generic programmable crystal oscillators without regard for output frequency and then quickly programmed to produce customer-specified output frequencies with a high degree of accuracy.

Abstract: A temperature compensated oscillator, a method of controlling a temperature compensated oscillator, and a wireless communication device are provided, where phase noise of the output signal can be reduced, frequency of the output signal stabilizes within a short time, and response of control does not become worse. Accordingly, a filter circuit is provided that removes noise contained in a temperature compensation voltage. A switching circuit is connected in parallel to this filter circuit. A power control circuit controls power supply to a voltage controlled oscillation circuit 28 and the like. The power control circuit turns on the switching circuit for a specified period when power supply to the voltage controlled oscillation circuit is started.

Abstract: ? An RF Voltage Controlled Oscillator (VCO) design having improved power supply noise immunity. More particularly, a VCO resonant circuit that provides a high circuit Q, immunity to noise, and is tunable over multiple distinct bands. The resonant circuit is implemented in conjunction with an integrated circuit oscillator that requires a tuned circuit to determine the frequency of operation. When the integrated circuit oscillator is used as a Local Oscillator (LO) within a wireless phone it is subjected to numerous sources of power supply noise. In a Code Division Multiple Access (CDMA) wireless phone system the power supply to portions of the RF transmit path are cycled on and off depending on the transmitted data rate. The present invention provides an oscillator with increased immunity to the noise induced on the power supply due to power supply cycling.

Abstract: An isolator device with a built-in power amplifier includes a single dielectric multi-layered substrate, a high frequency power amplifier circuit, an isolator element, and circuit elements provided to the dielectric multi-layered substrate. The high frequency power amplifier circuit and the isolator element are connected with each other through the circuit elements and united with the single dielectric multi-layered substrate.

Abstract: A variable phase shifter is improved in liquid crystal response characteristics by using a thin liquid crystal material as a dielectric substrate. The variable phase shifter includes two substrates disposed parallel to each other. The substrates have alignment layers on their mutually opposing inner surfaces. A liquid crystal layer is sealed in the area between the substrates. A transmission line is formed to meander on the inner surface of one of the substrates. A grounding conductor is formed on the inner surface of the substrate along the transmission line at a predetermined distance therefrom. External electrodes are formed at least in regions on the respective outer surfaces of the substrates, each of which regions corresponds to the gap between the transmission line and the grounding conductor. A bias voltage source applies a bias voltage between the upper and lower external electrodes.

Abstract: An edge reflection type surface acoustic wave filter includes a piezoelectric substrate having two opposing edges and at least one interdigital transducer. The interdigital transducer includes split electrodes of paired electrode fingers arranged on the piezoelectric substrate such that a shear horizontal (SH-type) surface acoustic wave is excited on the piezoelectric substrate and is reflected between the two opposing edges. Each of the edges is preferably located at a distance of at least about {fraction (&lgr;/2)}-{fraction (5&lgr;/128)} from a center of the paired equipotential electrode fingers, located at the respective outermost portions, in the surface acoustic wave propagation direction, of the interdigital transducer and less than about {fraction (&lgr;/2)} from the center of the paired equipotential electrode fingers, where &lgr; is a wavelength of the SH-type surface acoustic wave excited on the piezoelectric substrate.

Abstract: A magnetostatic wave device of the invention comprises a ferrimagnetic film for exciting and propagating magnetostatic waves and a magnetic field generator for applying a magnetic field to the ferrimagnetic film. The magnetic field generator comprises a permanent magnet and one pair of yokes that are magnetically connected to the permanent magnet and are opposite to each other with an air gap located between them. The air gap has the ferrimagnetic film received therein. According to the first embodiment of the first aspect of the invention, the post and yokes are fixed together by the engagement of a protrusion formed on either one of the yokes and post into a recess formed in the other. According to the second embodiment of the first aspect, the post and yokes are fixed together by the engagement of a rod member into recesses formed in the respective post and yokes.

Abstract: A mechanism for operating a plurality of circuit interruption mechanisms of a circuit breaker, the mechanism applies a uniform force to the circuit interruption mechanisms. The mechanism applies a force to an elongated member for manipulating the circuit interruption mechanisms. The mechanism applies a force to the elongated member at a first position and a second position, the first position and the second position being intermediate to a center of the elongated member and the plurality of circuit interruption mechanisms.

Abstract: An electromagnet assembly for an electromagnetic apparatus has a ring member, a coil bobbin having an electrical wire wound a spool of the ring member, and a ring case. The ring member is disposed in an annular groove of the ring case. An opening is formed through the ring case adjacent to its closed end surface. A connector, which is disposed on the ring case and covers the opening, includes a case having a closed shape and a bottom, and a cap closing an open end of the case. Ends of the electrical wire and ends of a lead wire are joined in the connector. A projection portion is formed around a fringe portion of a first end surface of the cap and abuts an open end surface of the case. The cap is secured fixedly to the case after the projection portion is melted.

Abstract: A multilayer inductor in which a DC resistance is small so that a high direct current can be applied thereto, has a structure in which a plurality of magnetic layers is stacked and coil conductor patterns are provided between the magnetic layers. The coil conductor patterns are spirally connected to each other via through-holes formed in the magnetic layers. The coil conductor patterns are arranged such that the areas of projected planes of the coil conductor patterns on main surfaces of the magnetic layers are within a range from about 35% to about 75% of the areas of the main surfaces of the magnetic layers.

Abstract: An electromagnetic coil assembly for an electromagnetic apparatus has a bobbin, a coil formed of an electrical wire wound a spool of the bobbin, a thermal protection device including a pair of lead wires, a first and a second lead wires, extending from thereof. The first lead wire is connected to one end of the electrical wire through a first connecting member. The second lead wire is connected to one end of a lead wire of an electric circuit through a second connecting member. At least one securing member having a groove-shaped cross-section is secured, e.g., welded securely or fittied pressedly, on a first end surface of the bobbin. The thermal protection device, the first connecting member, and the second connecting member are disposed on the first end surface of the bobbin and are covered by the securing member.

Abstract: A mobile electronic apparatus in which biometrics information, free from being stolen or faked by a unauthorized person, is used for user verification, virtually perfectly protecting an authorized user's personal data stored in a storing section of the apparatus. A verifying section compares a user's biometrics feature information with the authorized user's reference biometrics feature information to discriminate whether the fingerprint feature information for verification matches the reference fingerprint feature information. If it matches, a display control section reads out the personal data stored in the storing section and controls a display section to display the read-out personal data.

Abstract: An automatic ticket gate apparatus comprising a box defining the passage for ticket checking and a communicating face inclined to the horizontal to the side of passage, which is provided on the top of box and is provided with a wireless communicator communicating with a wireless ticket, and a ticket checking unit, which performs the ticket checking process basing upon the result of communication with a wireless ticket through the wireless communicator.

Abstract: When a dividing ratio data is written in a counter/timer register 530, a counter/timer circuit 534 divides a frequency of an oscillation signal of the oscillator 532 as much as the dividing ratio data. When an output enabling data is written in the port B register 536, a variable gain control signal is output from an envelope producing circuit 538. A variable gain control circuit 540 changes amplitude of a dividing signal as much as the value responsive to a voltage of the variable gain control signal. When an output disabling data is written in the port B register 536, the variable gain control signal is not output from the envelope producing circuit 538. The variable gain control circuit 540 stops the amplitude control of the dividing signal.

Abstract: A pressure-sensitive sensor is provided with a tube member having a hollow portion defined by an inner wall and made of flexible material, a first belt-like electrode disposed on an upper side of the tube member in the tube member and a second belt-like electrode disposed on a lower side of the hollow portion in the tube member so as to oppose the first belt-like electrode. When the pressure-sensitive sensor is pressed, the first belt-like electrode and the second belt-like electrode are capable of contacting each other so as to ensure conductivity. Further the pressure-sensitive sensor has a contact adjusting portion provided on an inner wall of the tube member and for adjusting a contact between the first belt-like electrode and the second belt-like electrode. Additionally, a connector capable of being combined with such a pressure-sensitive sensor is also disclosed.

Abstract: A security system for use in supermarkets and other retail outlets comprises a plurality of shopping carts and at least one point of sale terminal 10. Each point of sale terminal 10 comprises a transmitter 14 which provides an adjacent cart 13 with an electronic token once the goods in the cart have been paid for.

Abstract: An apparatus for indicating the level of harvested cotton in a basket assembly of a cotton harvester is provided. The apparatus includes a transducer, a control circuit and an indicator. The transducer is coupled to a motor of a compaction member of a compaction assembly of the cotton harvester and measures the pressure exerted by the harvested cotton upon the compaction member. The transducer generates a pressure signal that is received by the control circuit. The control circuit generates a basket level indication signal a short time after the pressure signal indicates a predetermined pressure has been measured. Alternatively, the control circuit generates the basket level indication signal when the pressure signal indicates the basket assembly is approximately full. An indicator, such as a lamp or buzzer, receives the basket level indication signal and provides an indication to the operator of the level of harvested cotton in the basket.

Abstract: An optical signal transmission circuit for a probe is switched on by an optical switch-on signal comprising a burst 42 of pulses having a predetermined length. This is detected by a circuit which discriminates whether an input signal is a genuine switch-on signal or an interference burst 44, on the basis of the duration of the switch-on signal.

Abstract: In a vehicle backward movement assisting apparatus for in-line parking, at a stop position of a vehicle, a seesaw switch is manipulated until an in-line guide line is superimposed on a target point which is a corner of a frame of a parking space, and a steering wheel is turned until the vehicle space mark is superimposed on the parking space, and the vehicle is moved backward while the steering angle of the steering wheel is held. When an eye mark is superimposed on the parking space, the vehicle is stopped, and the steering angle of the steering wheel is made maximum and the vehicle is moved backward, to thereby complete the in-line parking at the parking space.

Abstract: A remote controller, methods of use and manufacture thereof, for controlling electronic devices or host devices, the controller including a housing, electronic circuitry, power source and structuring for communicating with the electronic device to be controlled. A plurality of finger depressible buttons are exposed and interfacing with sensors associated with the circuitry. The buttons are for user selection of communication information sent to the host. At least one sensor is a pressure-sensitive analog sensor structured for varying electrical conductance through at least three readable states dependant upon user selected varying depressive pressure levels applied to the associated button. The circuitry reads the states of the analog sensor and information representing the state or value of the sensor is communicated to the host. A user can select any of a plurality of selectable pressure levels associated with analog sensor.

Abstract: A data processing system comprises a data compression decoder arranged in operation to decode first and second encoded data to produce first and second uncompressed data representative of first and second source data from which the first and second encoded data were produced in accordance with a compression encoding algorithm respectively. The data compression decoder also produces first and second compression parameter data representative of encoding decisions made by the compression encoding algorithm when the first and second source data was compression encoded.

Abstract: A data modulating/demodulating method and apparatus for an optical recording medium that is capable of keeping a digital sum value at a minimum value. In the method, a source data is converted into a coded data by a first conversion table in which the coded data corresponding to the source data is registered. The coded data is converted into a first channel data suitable for the optical recording medium. A second conversion table is registered with a coded data for suppressing a DC component in correspondence with a specific source data such that a digital sum value of the first channel data becomes a minimum value. The specific source data is converted into the coded data for a direct current restraint by the second decoding table and then converted into a second channel data. A digital sum value for the first and second channel data is calculated to select a coded data in which the digital sum value becomes a minimum value from the first and second conversion tables.

Abstract: The invention relates to programmable voltage regulator that programmably provides a desired operating voltage to a power pin based upon operating voltage configuration data. The programmable voltage regulator includes an operating voltage configuration data decoder arranged to decode the operating voltage configuration data. The programmable voltage regulator also includes a programmable voltage down converter connected to the operating voltage configuration data decoder. The programmable voltage down converter uses the decoded operating voltage configuration data to convert the first voltage to the desired operating voltage which is then output to the power pin.

Abstract: A D/A conversion system includes means (18) for arranging a stream of digital samples into frames, each frame including a guard time period. Means (52) are provided for determining a measure of the overall magnitude of digital samples in each frame. Means (50) increase the magnitude of all samples of frames that have a measure that falls below a predetermined threshold by shifting the samples a common number of bits. A D/A converter converts frames with shifted and frames with unshifted samples. An attenuator (54) attenuates the D/A converted samples of frames with shifted samples to compensate for the magnitude increase.

Abstract: An antenna test range uses direct spread-spectrum based test signals to test the performance of an antenna. Since a spread spectrum waveform has high autocorrelation properties with itself and high cross-correlation properties with signals other than itself, in the receiver coupled to the antenna it is possible to effectively electronically reject all unwanted signals that may be present in the test range, and thereby allow both main beam and off-axis performance of the antenna to be completely and accurately measured.

Abstract: A mobile cellular telephone (100) is disclosed comprising a communications transmitter (103) and receiver (102) arranged for two-way communication with a base station (BS), and a GPS receiver (105, 106) arranged to power up in response to direct interaction between a user and the mobile phone (100) after the telephone has been switched on.

Abstract: GPS receiver (1) is disclosed together a mobile unit especially in the form of a mobile cellular telephone (30) incorporating the same. The GPS receiver (1) comprises a GPS signal antenna (10) for receiving externally transmitted GPS signals; an analogue-to-digital converter (11) coupled to the antenna for sampling the received GPS signals; a memory (12) for storing the GPS signal samples; and a digital GPS signal processor (13, 14) for retrieving pseudorange information from the GPS signal samples stored in the memory (12). The receiver (1) has a dormant mode of operation in which received GPS signals are sampled and stored in the memory (12) but the signal processor (13, 14) is not operative for retrieving pseudorange information, and an active mode of operation in which the signal processor (13, 14) is operative for retrieving pseudorange information.

Abstract: A time synchronization system comprises a GPS (Global Positioning System) receiver for receiving a time signal from a Global Positioning System (GPS), and outputting a UTC (Universal Time Coordinated) synchronization reference signal synchronizing with UTC and a UTC synchronization absolute time signal, and a time signal distributor for generating a reference time signal synchronizing with UTC from the synchronization reference signal and the absolute time signal, and transmits this reference time signal in distribution to a plurality of distributed control oriented terminal devices. The time synchronization between the plurality of distributed control oriented terminal devices can be thereby taken.

Abstract: According to a case construction of the satellite-broadcast receiving converter of the present invention, air from the outside can enter and exit from a housing through a filter by way of a hole. Accordingly, a case and a sealing member can be prevented from being destroyed because of the expansion and contraction of air in the housing and, at the same time, water such as rain entering a cavity through the hole can be prevented from entering the housing deeper by the filter.

Abstract: A transmission system delays a carrier wave and program audio in the digital domain. The carrier wave and the program audio are converted to analog and the carrier wave is modulated by the program audio. The system includes a master oscillator that generates a digital carrier wave. The digital carrier wave is transmitted to a delay stage that delays the digital carrier wave by a certain delay value. The system further receives an analog or digital signal that is representative of programming. If an analog signal is received, the signal is transmitted to an analog-to-digital converter where it is converted to digital audio. The digital audio is then transmitted to a delay stage that delays the digital audio by the same delay value. The digital carrier wave and the digital audio are converted to an analog carrier wave and analog audio respectively. A modulator modulates the analog carrier wave by the analog audio and sends the amplitude modulated carrier wave to a power amplifier.

Abstract: A dielectric slab is arranged on one surface of a ground plane to form a transmission guide for transmitting an electromagnetic wave along the surface from one end to the other end between the dielectric slab and the ground plane. A perturbation is loaded on the dielectric slab to leak the electromagnetic wave from the surface of the dielectric slab. A feed supplies an electromagnetic wave to one end of the transmission guide formed by the ground plane and dielectric slab. A dielectric layer is interposed between the ground plane and the dielectric slab, and has a lower permittivity than that of the dielectric slab.

Abstract: The invention relates to a microdisplay system that utilizes a small high resolution active matrix liquid crystal display with an illumination system and a magnifying optical system to provide a display for a portable communication device. A handset for the communication system incorporates the display for use as, for example, a wireless telephone or paging device. The small display can provide a high resolution color image at low power thus providing for portable battery powered operation.

Abstract: In a reset period, through applying a rectangular pulse (Pya) of positive polarity to an electrode (Y) and applying a CR pulse (Pxa) of negative polarity to an electrode X, a full lighting pulse is applied between the electrodes (X and Y). The application of the voltage is stopped before a CR pulse (Pxc) reaches a final potential, to generate the pulse (Pxa). A full erase pulse (Pxb) made of a CR pulse having a polarity reverse to that of the pulse (Pxa) is applied to the electrode (X). An erase operation reverses the polarity of wall charges accumulated by a full lighting to effectively perform a potential control operation. The potential control pulse (Pxc) is applied to the electrode (X) to generate a discharge, and the state of the wall charges in a discharge cell is controlled by the discharge to generate an optimal amount of wall charges for a subsequent addressing discharge. The final voltage of the pulse (Pxc) is set equal to a voltage (−Vxg) of an address pulse (Pa).

Abstract: A PDP energy recovery apparatus and method controls the time point of charging and discharging energy to a plasma display panel (PDP) optimally and performs a high speed addressing. The PDP energy recovery apparatus includes a PDP, a driving integrated circuit unit for driving the PDP; and a PDP energy recovery circuit units for supplying energy to the PDP, charging an electric charge in the PDP at the time point when the electric charge discharged from the PDP is outputted the smallest, discharging the electric charge charged in the PDP, to thereby quicken the operating speed of the PDP.

Abstract: The present invention discloses a quad type liquid crystal display device, comprising: a liquid crystal panel having gate and data lines which define sub-pixel regions; gate driving integrated circuits for driving the gate lines; and a plurality of data drive integrated circuits arranged on one side of the liquid crystal panel, each of the data drive integrated circuit having “m” (m is natural number) number of channels, wherein (3n−1)th (n is natural number) channels for each data drive integrated circuit are floating.