Abstract: A traffic statistical processing unit of a switching processor measures a load to be relayed on a network, and the measured load data is exchanged between apparatus. A statistical data recorder records load data to be relayed over the network, respectively of each of other apparatus and each terminal and received from the traffic statistical processor unit. A terminal address table records as an entry a source address of each terminal from which data is relayed over the network. A filtering condition setter judges from the load data of the recorder whether the load of the apparatus is largest or relatively large, and if the load is largest or relatively large, determining an entry being passed to other apparatus having a smallest or relatively small load. A terminal table manager notifies the entry determined by the condition setter to the other apparatus and deleting the entry from the terminal address table.

Abstract: There is provided a multiple-processor information processing system which is capable of reducing adverse influence of overload of a given communication process on other communication processes than the given communication process. In this multiple-processor information processing system, a virtual IP address definition section defines virtual IP addresses on a process module-by-processor module basis. A storage device stores the virtual IP addresses defined by the virtual IP address definition section and information indicative of ones of the processor modules corresponding to the virtual IP addresses, respectively, in a state correlated with each other. A notification section notifies a router of a virtual IP address of each processor module and a real IP address of the each process module as routing information, for the each processor module having the virtual IP address stored in the storage device.

Abstract: An advertising method using a code image physically or electronically represented and an apparatus thereof are provided. According to the method, information for providing network services related to advertisements is physically or electronically represented by a code image in various advertising media, and a user can directly user network services provided by the advertiser, by clicking on the image or scanning or photographing the image with an optical input apparatus.

Abstract: To construct directories automatically in a group of terminals of a local area network, a given terminal that has just been connected broadcasts a message containing its name and address. Another terminal of the group decodes the broadcast message, extracts the name and address of the given terminal from the broadcast message in order to insert them in a directory, and transmits its name and its address in a response message containing the address of the given terminal. The given terminal decodes the response message, extracts the name and the address of the other terminal from the response message, and inserts them in a directory.

Abstract: The object of the present invention is to provide a DNS server and terminals both of which are capable of sending and receiving communication by means of a small number of IP addresses. In the case where a firewall is not provided, when the DNS server receives an inquiry of a FQDN, it sends a broad cast frame for searching a terminal to which an IP address is assigned via all the network devices. When a terminal monitors the broad cast frame and finds the FQDN to be its own FQDN, it returns the uni-cast frame to the DNS server. When the DNS server receives the uni-cast frame, it makes a look-up table and a reverse look-up table. As a result, the terminal can receive the communication by an ordinary method. In the case where the firewall is provided, by processing an IP address conversion between the external IP address and the internal address by the use of an IP address conversion means NAT in addition to making the look-up table and the reverse look-up table, the terminal can receive communication.

Abstract: A system for protocol processing in a computer network has an intelligent network interface card (INIC) or communication processing device (CPD) associated with a host computer. The INIC provides a fast-path that avoids protocol processing for most large multi-packet messages, greatly accelerating data communication. The INIC also assists the host for those message packets that are chosen for processing by host software layers. A communication control block for a message is defined that allows DMA controllers of the INIC to move data, free of headers, directly to or from a destination or source in the host. The context is stored in the INIC as a communication control block (CCB) that can be passed back to the host for message processing by the host. The INIC contains specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU.

Abstract: This invention has as its object to reduce network traffic when a remote copy process is done using network devices. To achieve this object, a computer (13) acquires stub drivers (610, 612) from image input/output devices (12-1, 12-2) (S1601, S1602), and sends the stub driver (610) to the image input/output device (12-1) (S1605). The image input/output device (12-1) drives the image input/output device (12-2) by executing the received printer stub driver (610), sends scanned data, and makes the image input/output device (12-2) print the data.

Abstract: In a data processing system, a plurality of modules connected to a system bus thereof are assigned with identifiers. When a source module initiates a split read access to another module, the source module sends an address of the access destination module and an identifier of the source module. When sending a response to the source module, the destination module returns response data and the identifier of the source module thereto. Checking the identifier from the destination module, the source module determines the response data returned as a response to the initiated access.

Abstract: A storage system stores multiple copies of data on physical storage implemented, for example, with multiple disk units. Input/output read requests are received from host systems and distributed in a manner that allows parallel read operations to be conducted over the multiple disk units of the physical storage.

Abstract: In a method for time synchronization of units (2) in a system (A) which has a timebase unit (1) which is connected via a deterministic communications network (3) to the units (2), the timebase unit (1) transmits protocol packets (P) via the deterministic communications network (3) to the units (2) at a defined time interval (t). These units (2) receive the protocol packets (P) and use the time interval (t) between the received protocol packets (P) for at least approximately identical clocking of the units (2). This results in high accuracy in the synchronization of system parts, using simple means.

Abstract: Priorities are set in order of an internal register access packet, a response system packet, and a command system packet which are transmitted/received by a packet transmitting/receiving unit. In a transfer waiting state of the command system packet of the low priority to a certain transmission destination, in the case where the response system packet or internal register access packet of the high priority to another transmission destination is received from an external module, the packet transmitting/receiving unit withdraws the transfer waiting state and transmits the packet of the high priority.

Abstract: The present invention includes a memory subsystem comprising at least two semiconductor devices, including at least one memory device, connected to a bus, where the bus includes a plurality of bus lines for carrying substantially all address, data and control information needed by said memory devices, where the control information includes device-select information and the bus has substantially fewer bus lines than the number of bits in a single address, and the bus carries device-select information without the need for separate device-select lines connected directly to individual devices.

Abstract: A parallel, fault-tolerant computer system in which data is transferred between processes in a single CPU by two methods. In a first method, the data is copied each time it is transferred. In a second method, the data is not copied, but is passed through a shared memory, queueing system. The first method is used to ensure fault-tolerance and linear expandability. The second method is used to minimize the time required for inter-process communication. Use of the shared memory queueing system allows for faster communication between processes executing in a same CPU.

Abstract: The invention concerns a new bus protocol for the serial transfer of data between two electronic components (SLAVE, MASTER) via a 3 line bus connection.

Abstract: A distributed type input buffer switch system includes at least one input data processing unit matched to an input port for storing and managing input data by target output ports, requesting arbitration for switching, and storing and managing information on an arbitration-requested data; an arbitration unit for managing an arbitration request signal received from the input data processing unit according to the input data processing unit and the target output port and performing arbitration according to an arbitration request; and a switching unit for receiving data from the input data processing unit and transmitting the same to the output ports by performing switching according to a command from the arbitration unit.

Abstract: In a programmable controller which executes a user program process, an I/O refresh process and a peripheral service process by using a same microprocessor, the cyclic execution of the peripheral service process by a prescribed amount is ensured so as to enable a satisfactory data relay function without regard to the time period required for the execution of the user program process. The user program process which is being executed by the normal process means is interrupted by the peripheral service process which is executed by a prescribed amount according to an interruption procedure every time an interruption trigger is generated.

Abstract: The present invention aims at restoring backup data in a predetermined order and avoiding damage from being given to the system even when the backup data are destroyed. Flags Ferr and Feeprom and a variable i stored in a DRAM are initialized (S1 to S3). When the variable i is smaller than the number n of EEPROMs (hereinafter referred to as “PROM(s)”), the ID code of a PROM in question is read and loaded into the DRAM (S4 to S6). When the variable i equals the number n, the variable i is cleared (S7). Then, a variable j is initialized (S9), and it is determined whether or not each PROM ID stored in the DRAM matches with a mask ROM ID until the variable j becomes greater than the number n of PROMs (S11). If the answer is “No”, the variable j is incremented (S13), while if “Yes,” a number corresponding to the variable j then assumed is loaded into the DRAM as the flag Feeprom (S14).

Abstract: The present invention is to realize a data storage control method and apparatus for an external storage device using flash memories. The method and apparatus can eliminate the data erasure waiting time, eliminating the calculation of the erasure numbers of flash memories, elongating the life-time of the flash memories. Data is stored sequentially from a first flash memory for rewrite data to a third flash memory for rewrite data. When there is no vacant area in the third flash memory for rewrite data, a CPU instructs a first flash memory for garbage collection among the first and second flash memories for garbage collection to perform the garbage collection of the first flash memory for rewrite data. When a host computer issues a write access request, the write process is performed in the first flash memory for garbage collection with the first priority.

Abstract: A dynamic random access memory circuit including a memory plane formed of an array of memory cells, as well as at least two cache registers enabling access to the memory plane and adapted to ensure the reading from and the writing into the memory. The circuit also includes several registers indicating the location of new words to be written, each of the indicative registers being coupled with one of the cache registers adapted to ensuring the writing into the memory.

Abstract: The present invention suppresses a data writing speed in mirroring and increases expandability. For a write request from a host, a disk controller stores write data in cache memory, and then transforms it into optical signals by a light emitting apparatus and sends them to an optical bus. The signal light inputted to the optical bus is broadcast-transmitted by the optical bus and read into disk drives simultaneously through a light receiving apparatus. This suppresses reduction in a data writing speed in mirroring and increases expandability.

Abstract: A logic which enables implementation of a 80-bit wide or a 96-bit wide cache SRAM using the same memory array. The logic implementation is accomplished by merging tag, and data into an order block of information to maximize bus utilization. The logic reduces the bus cycles from four cycles for an 80-bit to three cycles for a 96-bit implementation.

Abstract: Various methods of caching web resources include caching in accordance with a number of times accessed, a frequency of access, or a duration of access. One method of caching web resources includes the step of accessing a first web resource. The first web resource is cached, if no other web resource is accessed after a pre-determined period of time. Another method of caching web resources includes the step of accessing a first web resource. The first web resource is cached, if the first web resource is subsequently accessed more than a pre-determined number of times. Another method of caching web resources includes the step of accessing a plurality of web resources. The accessed web resources are cached as cached web resources in accordance with at least one of a number of times accessed, a frequency of access, or a duration of access. An apparatus comprises storage media containing caching logic for caching web resources.

Abstract: A method and device for memory management in digital data transfer, in which the device consists of first memory rows (61) and second memory rows (62) and in the method, a bit column with fixed values is added as the first column (64) of the second memory rows, first bit rows are copied (63) as second bit rows in accordance with the Add-Compare-Select unit's selections, and the selection for the decoded bit is performed based on the values of elements in the column (66) formed by the second bit rows or based on some other row formed by the second bit columns.

Abstract: A heap is a memory resource managed in units of cells and it is used in units of cells by the execution of an application program. A full garbage collection unit collects free cells based on the check result of the state of use of cells. A partial garbage collection unit collects free cells from cells that are used after the check of the state of use of cells recently made by the full garbage collection unit, based on the check result of the state of use of cells. A full/partial control unit improves the process efficiency of parallel type garbage collection by making either the full garbage collection unit or the partial garbage collection unit perform a subsequent collection of free cells based on the state of collections made in the past.

Abstract: In the control section, an operation instruction not prescribing a functional specification, and a unit for processing the specific application-purpose operation instruction is provided within the processor core. The structure of this unit can be changed based on a flexible pipeline structure, and is separately designed for each application field. A register that prescribes a latency from when an instruction of the above unit is issued till when a result can be utilized is also provided in the processor core so as to prevent contention of an output port. Another register that prescribes a latency relating to a constraint of an interval of issuing an instruction of the above unit is also provided in the processor core so as to prevent contention of a resource with the preceding instructions.

Abstract: A method and instruction for converting a number between a floating point format and an integer format are described. Numbers are stored in the integer format in a register of a first set of architectural registers in a packed format. At least one of the numbers in the integer format is converted to at least one number in the floating point format. The numbers in the floating point format are placed in a register of a second set of architectural registers in a packed format.

Abstract: A processor is provided with a set of instructions formed, in general, of an operation section and an operand section. For at least one of the instructions, the operand section represents operation control signals of the processor. In this way, an extension of the set of instructions can be achieved for tailoring the set of instructions to the user's own requirements. Consequently, the processor control unit should be capable of coupling its outputs to its inputs upon receiving one such instruction, thereby to transfer such internal operation control signals without interpretation.

Abstract: A security protocol entity (20) is provided that includes a mechanism for enabling a first party (11) to communicate securely with a second party (60) through an access-controlling intermediate party (13) by nesting within a first security session (64) established with the intermediate party (13) a second security session (65) with the second party (60). The protocol data units, PDUs, associated with the second security session (65) are encapsulated in PDUs associated with the first security session (64) when sent out by the first party, the intermediate party extracting the encapsulated PDUs for sending on to the second party (possibly with a change to the destination address included in the PDU to be sent on). Each PDU includes a message type field explicitly indicating to the intermediate party (13) if a received PDU encapsulates another PDU intended to be sent on.

Abstract: This invention developed a communication method which satisfies confidentiality to secure the contents from tapping transmission and user authentication to confirm the identification of parties involved in the communication.

Abstract: The present invention relates to a transmission apparatus, a reception apparatus, a transmission method and a reception method, which are used for transmission and reception of encrypted digital data protected against illegal decryption of the encrypted digital data by a third party capable of inferring an encryption algorithm by decryption of a pattern having a known pre-encryption value, and relates to a recording medium for recording the encrypted digital data.

Abstract: A memory rewriting system for a vehicle controller is provided. The system comprises a vehicle controller and an external rewriting device. A vehicle controller comprises a rewritable memory storing first security data. The first security data is used to determine whether rewriting to the rewritable memory is permitted. The rewriting device transfers new security data to the vehicle controller. The vehicle controller deletes the first security data and writes the new security data into the rewritable memory. Rewriting the new security data is performed by a program stored in a non-rewritable memory. Thus, the security data that is used to determine whether rewriting to the rewitable memory is permitted is rewritten with the new security data. Therefore, if the existing security data stored in the vehicle controller is invalidated, the security feature of the vehicle can be recovered. The vehicle may includes an anti-theft system.

Abstract: A security management and audit of a business information system in accordance with an information security policy is simplified. Provided is a security management and audit program database 133 in which the information security policy and an object system correspond to management and audit programs. The management and audit program corresponding to a range of the information security policy and the object system, which are designated by an operator, is retrieved and automatically executed. The management and audit program performs a management and audit concerning an information security policy of an object system corresponding to itself.

Abstract: A multicast system comprises: a sender terminal for transmitting multicast data; a receiver terminal for receiving multicast data; an authentication server processor for managing the sender terminal and the receiver terminal; a first user processor provided in the sender terminal for transmitting a login requirement to the authentication server processor; and a second user processor provided in the receiver terminal for transmitting a login requirement to the authentication server processor, so that a user is identified by individually authenticating the user using a specified authentication server.

Abstract: An electronic control system includes a microprocessor and a boost circuit to boost a supply voltage to the microprocessor. The microprocessor generates a boost control signal to control the boost circuit.

Abstract: An 8051 microprocessor core having an ability to operate via an external crystal oscillator or be switched to operate in a low power mode via an internal ring oscillator.

Abstract: A method for activating a microprocessor, which is part of a microcontroller, within the framework of a boundary scan test procedure according to Institute of Electrical and Electronic Engineers (IEEE) standard 1149, using a Joint European Test Action Group (JTAG) interface of the microprocessor. To be able to test a microcontroller, using the boundary scan test procedure, even when the JTAG interface is not accessible by a separate hardware adaptor of a JTAG tester, it is proposed that the JTAG interface of the microprocessor be activated by a test routine executable on the microprocessor.

Abstract: A device for testing a digital signal processor in a DVD (Digital Video Disc) reproducing apparatus. The test device includes a computer for generating test data for testing the digital signal processor, and displaying test results on a screen thereof; a track buffer for storing data processed by the digital signal processor and the test results for the digital signal processor; and an interface for transferring the test data output from the computer to the digital signal processor, and reading out the test results from the track buffer to transfer the read test results to the computer. Further, the test device includes a switch for alternately switching the track buffer to the interface and the digital signal processor on a basis of time division, so as to allow the digital signal processor to write the test results in the track buffer and the interface to read the test results stored in the track buffer.

Abstract: A monitor includes a display panel, a displaying circuit, a connector and a self testing circuit. The self testing circuit has a testing signal generator, a switch circuit and a detecting circuit. When the detecting circuit detects the video signals transmitted from the computer, the detecting circuit switches off the switch circuit so as to avoid the testing signal generated from the testing signal generator being transmitted to the input port of the displaying circuit. When no video signals transmitted from the computer are detected, the detecting circuit switches on the switch circuit to allow the testing signal generated from the testing signal generator to be transmitted to the displaying circuit.

Abstract: A signal used in the transmission of data in a communication system (for example in an ATM network), comprised of immediately successive cells. For the purpose of cell synchronization, filler cells (I) containing a predefined bit pattern are provided. This pattern is provided with an error protection code that differs from the error protection code used for the user data. Even if the user data should coincidentally contain the predefined bit pattern, the synchronization circuit will not be able to be simulated, since this false bit pattern is provided with a different error protection code. In order to test and ensure the synchronization state, a BIP value at the end of the cell is checked at the receiver end.

Abstract: In a Bit Interleaved Parity (BIP)-N calculating apparatus (N is an integer) according to the present invention, serial/parallel conversion circuit 1 performs a byte-interleaved separation on input STS-3c concatenated signals. The separated signals are supplied to the serial/parallel conversion circuits 2 to 4 where these signals are subjected to a bit-interleaved separation to attain N-bit signals. Each serial/parallel conversion circuit respectively provides the N-bit signal to BIP-N calculation circuit 5 to 7. Outputs from the BIP-N calculation circuit 5 to 7 are held in flip-flops 8 to 10 and then supplied to exclusive-OR gates 11 to 13. The exclusive-OR gates 11to 13 and concatenation control circuits 14 to 16 are connected in a concatenation manner, so that a calculation is performed in a concatenation manner on the results of the BIP-N calculation circuits 5 to 7. The EX-OR gate 11 outputs a signal as the BIP-N calculation result.

Abstract: A data error-correction method, applied in an optical storage device, for correction an original data read from an optical storage media. A bit modulation is performed on the original data. The data is thus checked to see if the original data is error. If error exists, an error bit is added to the error-contained modulated data. An error-correction procedure is carried out to correct error in the error-contained modulated data.

Abstract: In the event that during write to a storage device such as a DVD, data does not fill up a unit of generation of an error correction code (ECC), an increase in the data transfer amount caused by reading a shortage of data from a storage medium can be prevented. Controlling is carried out such that write data is not immediately written to the storage medium but write operation is deferred until an amount of data of ECC generation unit is complete in a buffer memory. As a result, the ECC can be generated and written to the storage medium by using only the write data without resort to read of the shortage of data from the storage medium.

Abstract: To provide a parallel processing Reed-Solomon encoding circuit that allows arbitrary parallel processing number to be taken and the parallel processing number optimal to the system to be adopted. The multiplier factors corresponding to the first inputs of the first Galois field product sum circuit to the fourth Galois field product sum circuit are the zeroth to third order coefficients of the generator polynomial G(x). The multiplier factors corresponding to the second inputs of the first Galois field product sum circuit to the fourth Galois field product sum circuit are the zeroth to third order coefficients of a polynomial of a remainder from x5 divided by the generator polynomial G(x). The multiplier factors corresponding to the third inputs of the first Galois field product sum circuit to the fourth Galois field product sum circuit are the zeroth to third order coefficients of a polynomial of a remainder from x6 divided by the generator polynomial G(x).

Abstract: The invention relates to the receiving and displaying of short audiovisual transmissions broadcast by a transmitter to digital television receivers. The receivers are furnished with a large recording capacity. The short audiovisual transmissions are typically advertising spots. According to the invention, the short audiovisual transmissions are, upon reception in the receiver, automatically replaced by transmissions of the same type previously recorded in the receiver. The receiver resumes normal displaying of the transmissions at the end of the broadcasting of the audiovisual transmissions of a certain type.

Abstract: A configuration comprising a plurality of individual seat apparatuses which output operation signals from operation switches for flight attendant call and for reading, the first and the second lights for flight attendant call and for reading, first distributors for outputting light control information which corresponds to an operation signal from each of said operation switches, first and second driving apparatuses that drive said first and second lights and second distributors for distributing light signals for flight attendant call or for reading to the driving apparatuses in response to the light control information from said first distributors.

Abstract: The present invention describes a non-human transgenic mammal that produces in its leukocytes, a recombinant human leukotriene B4 receptor (BLTR), having physiological activity of human BLTR. The transgenic mammal has stably integrated into its genome an exogenous gene construct which includes (A) 5′ expression regulating sequences, including a BLTR specific promoter, (B) DNA encoding the BLTR and a signal sequence effective in directing overexpression of the BLTR into leukocytes of the transgenic mammal and (C) 3′ regulatory sequences that result in the overexpression of the DNA in the leukocytes. In one embodiment, (A), (B), and (C) are operably linked in the gene construct to obtain production of the BLTR in the leukocytes and overexpression thereof in the transgenic mammal.

Abstract: Compositions and methods for enhancing disease resistance to a pathogen in a plant are provided. Methods of the invention comprise stably transforming a plant with an antisense nucleotide sequence for a gene encoding an enzyme in the C-5 porphyrin metabolic pathway and operably linking said antisense sequence to a pathogen-inducible promoter, such that invasion of a cell by a pathogen elicits a hypersensitive-like response that results in confinement of the pathogen to cells of initial contact. Transformed plants and seeds are provided. Nucleotide sequences encoding a wild-type maize urod gene useful in the present invention and the amino acid sequence for the protein encoded thereby are provided. These compositions are also useful for regulating cell death in specifically targeted tissues. A maize lesion mimic, dominant mutant phenotype, designated Les22, and the molecular basis for its manifestation are also provided.