Abstract: An electronic system interconnect. The interconnect comprises a first node and a second node coupled to the first node. The interconnect is initially configured to include the first and second nodes. A third node is added to the interconnect after the interconnect is initially configured, and the first node responds to the addition of the third node by initiating a new connect handshake with the third node. The first node begins by transmitting a first signal to the third node. The first node signals that the third node has been added to the interconnect if the third node responds to the first signal by transmitting a second signal. The first node causes the interconnect to be reconfigured if the third node transmits a third signal in response to receiving the first signal.

Abstract: This invention relates generally to communications with distributed nodes in a computer network, and more specifically with change management in a computer network.

Abstract: A system for serving web pages manages a plurality of web servers. The system provides an operator with features and tools to coordinate the operation of the multiple web servers. The system may manage traffic by directing web page requests to available web servers and balancing the web page request service load among the multiple servers. The system may collect data on web page requests and web server responses to those web page requests, and provide reporting of the data as well as automatic and manual analysis tools. The system may monitor for specific events, and may act automatically upon the occurrence of such events. The events may include predictions or thresholds that indicate impending system crises. The system may include crisis management capability to provide automatic error recovery, and to guide a system operator through the possible actions that can be taken to recover from events such as component failure or network environment problems.

Abstract: Route control and resource reservation mechanisms are integrated so as to perform multicast communication efficiently. In response to a connection establishment request from a new receiver (host F) with a sender (host A), resources are temporarily reserved and a route suitable for the receiver initiated request is selected, and the connection establishment request is transferred to an upper node. A similar process is performed in host D, and a connection establishment request is transferred to an upper node. In host C, resources are reserved, a confirmation request is transferred to a lower node, and the confirmation request is transferred to the host F via host D. In host F, the quantity of resources is adjusted, and the establishment of the connection with host A is completed.

Abstract: Client's (106-1-106-N, 107-1-107-M) on local area networks (102, 103) making requests to hot sites, which are connected on a wide area network (100) such as the Internet, are redirected through one of a possible plurality of different redirectors (101, 103) to one of a possible plurality of caching servers (S1, S2, S3), which each have responsibility for mapping one or more of the hot sites. Each request is probabilistically directed by one of the redirectors to one of the caching servers that map the requested hot site in accordance with weights that are determined for that redirector-hot site pair so as to minimize the average delay that all client requests across the network will encounter in making requests to all the cached hot sites.

Abstract: A system and method provide random access to a multimedia object over a network. One embodiment of the invention includes a streaming media server that is connected to a client computer over a network. The streaming media server includes at least one multimedia object that is adapted for transmission (“streaming”) across the network. A pre-roll calculation program determines a pre-roll for each segment of the multimedia object and generates a modified multimedia object which includes a pre-roll for each of its segments, a pre-roll identifying a portion of the multimedia object to be transmitted by the streaming media server and received by the client computer prior to playback of the multimedia object at a selected segment. The pre-roll allows the client computer to present, starting at a selected segment, the multimedia object in its entirety without interruption.

Abstract: In an information sending and receiving system in which an information sending equipment and at least one information receiving equipment send and receive information through a transmission medium, a management message is sent from the information sending equipment to the information receiving equipment thereby to create a list of a content code expressing a data message registered on the information receiving equipment side within the information receiving equipment. Then, a data message containing a content code and data is transmitted from the information sending equipment to the information receiving equipment. The information receiving equipment selects a data message by comparing a content code of a data message and a list of its own content code. The content code list may be created within the information sending equipment based on a property value in an answer message from the information receiving equipment.

Abstract: A method, system and computer program product for managing transmission of electronic data between network entities. Two network entities are interfaced so that Electronic Data Interchange (“EDI”) data from one network entity is transmitted to the other network entity in a secure exchange using Transmission Control Protocol/Internet Protocol (“TCP/IP”) for connectivity and Secure Sockets Layer, Version 3 (“SSL3”) for security in transmission. The transmitted electronic message includes a header portion and a message data portion, and optional trailer portions, depending on a predefined format of message desired to be transmitted. The header portion includes a message format identifier and a length of a data message for a data message to be included in the message data portion.

Abstract: A multilingual Domain Name System allows users to use Domain Names in non-Unicode or ASCII encodings. An international DNS server (or iDNS server) receives multilingual DNS requests and converts them to a format that can be used in the conventional Domain Name System. When the iDNS server first receives a DNS request, it determines the encoding type of that request. It may do this by considering the bit string in the top-level domain (or other portion) of the Domain Name and matching that string against a list of known bit strings for known top-level domains of various encoding types. One entry in the list may be the bit string for “.com” in Chinese BIG5, for example. After the iDNS server identifies the encoding type of the Domain Name, it converts the encoding of the Domain Name to Unicode. It then translates the Unicode representation to an ASCII representation conforming to the universal DNS standard.

Abstract: A system for providing a graphics tool access to a computer graphics system to evaluate and control a graphics application executing on the computer graphics system. The system includes application program interface (API) event generators for performing predetermined operations relating to a graphics library function call and for generating a hook event containing results of the predetermined operations; dispatch table manger for selecting an active dispatch table from a normal operations dispatch table having function pointer to the graphics library finctions and a hooks dispatch table having pointer to the API event generators; and hook event manager for enabling and configuring selected ones of the API event generators in response to a graphics tool event request. The system further includes internal event generators, integrated along various locations of a graphics pipeline managed by the graphics library, for performing predetermined diagnostic operations in the graphics system.

Abstract: A method and system in a multithreaded processor for processing events without interrupt notifications. In one aspect of the present invention, an operating system creates a thread to execute on a stream of the processor. During execution of the thread, the thread executes a loop that determines whether an event has occurred and, in response to determining whether an event has occurred, assigns a different thread to process the event so that multiple events can be processed in parallel and so that interrupts are not needed to signal that the event has occurred. Another aspect of the present invention provides a method and system for processing asynchronously occurring events without interrupt notifications. To achieve this processing, a first thread is executed to generate a notification that the event has occurred upon receipt of the asynchronously occurring event.

Abstract: A computer system is provided. The computer system includes a host processor (HP), a system memory (SM), and an input/output (I/O) master device to perform a read of a continuous stream of data to the SM. The computer system also includes a bridge coupled to the HP, SM, and I/O master device. The bridge reads ahead to the SM when the I/O master device reads a continuous stream of data from the SM. The bridge aborts read ahead accesses to the SM, prior to an access commit point to the SM, responsive to disengagement of the I/O master device.

Abstract: Techniques are provided herein for reducing vibrations in various modes of a dynamic system. One such technique comprises incorporating vibration limiting and sensitivity constraints into a partial fraction expansion equation model of the system so as to reduce vibrations to specific levels. Another technique comprises shaping a command determined using the partial fraction expansion equation model to produce a desired output. The entire command may be shaped or only selected portions thereof which produce vibrations. Another technique involves commanding in current to produce saturation in voltage. By doing this, it is possible to command voltage switches. The times at which the switches occur can be set to reduce system vibrations. Other techniques are also provided. These include varying transient portions at the beginning, middle and/or end of a move and using Posicast inputs, among others.

Abstract: The present invention is a method and apparatus for exchanging information between an electronic book and a cartridge. The electronic book has an on-board storage and the cartridge contains a cartridge storage. It is determined if the cartridge is present. If the cartridge is present, a transfer mode is identified. The information between the on-board storage and the cartridge storage is then transferred according to the identified transfer mode.

Abstract: A communication system for monitoring and/or controlling communication parameters of a communication device. The communication system monitors a communication channel that is created when the communication device connects to a network, controls the communication device as it operates on the network, and configures the communication device. The communication device is commonly a modem and is communicatively coupled to the network to carry out ongoing communications between the modem and the network through the communication channel. Further, a software module is associated with the modem, and the software module accesses the internal settings of the modem via the communication channel (if necessary) and performs operations such as monitoring, controlling, and configuring the modem (or other communication device) using the internal settings of the modem.

Abstract: A network adapter and a terminal system capable of supplying various statuses of a terminal device to a manager device are presented. A CPU of a print server senses a powered-on status of a printer, sends a dedicated transmission command to the printer, and receives response data indicating a present status of the printer after a status change, from the printer. The CPU of the print server determines whether the received response data is a response to the dedicated transmission command or a response to a normal transmission command output by a personal computer. If the response data is a response to the normal transmission command, the CPU sends the response data to the personal computer. If the response data is a response to the dedicated transmission command, the CPU of the print server stores status data contained in the response data into a status information storing area of a RAM of the print server.

Abstract: A method and system, implemented in hardware, for quickly and efficiently reassembling Fibre Channel data sequence data received by a Fibre Channel port in host memory buffers. The host memory buffers are referenced by a transaction status block allocated and initialized by the host. The transaction status block is referenced by the Fibre Channel port during transfer of data received in each Fibre Channel data frame of the Fibre Channel data sequence. The host memory buffers may be or arbitrary size and need only be byte aligned. The host computer can specify any number of host memory buffers by appropriate initialization of the transaction status block.

Abstract: A circular queue system is implemented using either a ‘mirror space’ appended to the circular portion of the queue (or buffer) or an ‘borrow’ space appended to the circular portion of the queue (or buffer). In each implementation, address verification or checking within the queue is not implemented until such time as the read or write portion to the queue has substantially completed. Where the address would normally exceed the physical or logical end address of the circular queue, the ‘mirror space’ or ‘borrow’ space provides sufficient storage to prevent overflow into other valid data.

Abstract: An interconnectivity scheme for a PC Theatre system includes the use of compatible plug and display connectors on both the display and the host computer. Audio/video signals received by either the display or the computer may be processed by the computer and transmitted between these devices in a standardized signal format using the compatible connectors. The control scheme for facilitating master-slave control of the display by the computer includes the use of various standardized signals and formats as well to ensure compatibility between products manufactured by different companies.

Abstract: An integrated HDD system provides, in a single integrated circuit, RDC, servo logic, ATA interface, microprocessor, and other formerly discrete components in one highly integrated system design. The integrated circuit is rendered using a single integrated circuit technology type (e.g. digital CMOS) for all components. Analog and digital circuits are combined in such a way as to eliminate or reduce noise or interference in digital circuits from analog circuit components. The invention takes advantage of existing circuit design modules provided in the integrated circuit as “hard block” components which are unchanged by integrated circuit design software. Changes in operability of the overall integrated circuit may be readily achieved by altering “soft block” components to customize or tailor the design for a particular hard drive.

Abstract: A system and method for constructing a resistance integrated coupler adapted to be coupled between a data bus and a terminal device. The system and method includes the steps of calculating a desired resistance of a set of data-bus windings, wherein the desired resistance is substantially (1.5×Zo), wherein Zo is a selected data bus cable nominal characteristic impedance; winding the set of data-bus windings to form a first part of the resistance integrated coupler using a specified amount of high resistance wire, the specified amount of high resistance wire having a total resistance substantially equal to the calculated desired resistance; and winding a set of terminal device windings to form a second part of the resistance integrated coupler. The resistance integrated coupler is constructed substantially in accordance with the guidelines of MIL-STD-1553B.

Abstract: A method and system for indexing adapters within a data processing system where the data processing system contains multiple existing adapters, where each of the multiple existing adapters is identified by particular indexing data. All adapters within the data processing system are scanned. A determination of whether or not any additional adapters have been added to the data processing system in addition to the multiple existing adapters is made. Particular indexing data is assigned to any additional adapters in response to determining that additional adapters have been added to the data processing system, where any additional adapters added to the data processing system are indexed into the data processing system without changing the particular indexing data of each of the multiple existing adapters.

Abstract: A portable electronic device adapted to be connected to or disconnected from an external device comprises a housing which accommodates an electrical circuit and which has a terminal adapted to be connected to the external device. A lid member is pivotally supported by the housing for movement between a first position covering the terminal and a second position exposing the terminal.

Abstract: Computer system comprising a communication bus, a plurality of units connected to the bus, in which the bus includes a plurality of bus segments, each bus segment being concatenated with at least one adjacent bus portion by means of buffer registers to transfer a data item from the adjacent bus segment to the bus portion, the computer system further comprising an arbitration unit to control, for each bus segment, the simultaneous access to the different segments, in a mutually exclusive way, by the units connected to each of the segments and by the buffers for concatenation of each of the segments with at least one adjacent segment.

Abstract: One aspect of the present invention provides a packer-unpacker (PUP) for a digital serial interface which allows a plurality of processors to access time slot registers of a serial data stream relating to the digital serial interface. A configuration register is maintained either by one of the plurality of processors or by each of the processors to arbitrate access to the individual time slot registers. Another aspect of the invention allows one or more processors to efficiently access and/or write more bits to a resource such as a time slot register than the width of the processor's respective data bus allows. Extra bits registers are maintained for at least one of the read and write direction data busses. The extra bits correspond to the least significant bits conventionally ignored in changing from a data bus of one width to a data bus of a narrower width. The extra bits in the write direction are accessed, e.g.

Abstract: A system for accessing control and status registers for a device within a computer system. These control and status registers are used to control and configure the device and to read status information from the device. The system operates by serially shifting an index into an index register within the device. This index specifies a target register to be accessed within the control and status registers. During a write operation to the target register, the system serially shifts a data value into a data register within the device, and then moves the data value from the data register into the target register. During a read operation from the target register, the system loads a value into the data register from the target register, and serially shifts the value from the data register to a location outside the device to complete the read operation.

Abstract: The present invention relates to a routing control apparatus for performing a round robin arbitration and an adaptive routing control. The present invention relates to a routing controller for performing an arbitration and a routing control which are nucleus functions of the crossbar routing switch and, in particular, to a normal routing controller unit for performing a priority based round robin arbitration and an adaptive routing controller unit for performing an adaptive routing control by adding an adaptive routing switch logic to the normal routing controller.

Abstract: A segmented fiber channel communications system includes a segmentation router, including a plurality of ports. Control instructions associated with the segmentation router establish the segmentation router as a master router by initializing each of at least a predetermined subset of the plurality of ports on a fiber channel arbitrated loop associated with the segmentation router. This causes the segmentation router to win the LISM process performed by the fiber channel arbitrated loop. Control instructions further includes instructions for transmitting LIPA, LIHA, and LISA frames to the fiber channel arbitrated loop from each of the ports. Transmission begins with LIPA frames having all but the LIPA frame range of address bits set to 1. This prevents other network loop ports attached to a router other than the master router from acquiring a duplicate address. The system then establishes a plurality of sub-loops each associated with a predetermined set of physical addresses.

Abstract: Systems and methods consistent with the invention write and read data cells to and from a bank of cell buffer memories. The system includes a plurality of memory units for storing data cells. An address memory outputs a memory address and a memory selecting unit selects one of the plurality of memory units based on the outputted memory address. The system then performs a read or write operation at the outputted memory address of the selected memory unit. The system may write data cells to one memory unit while at the same time reading data cells from one of the other memory units.

Abstract: A method and apparatus for addressing memory in a processing system that includes a cache structure and supports multiple data streams is presented. The cache structure may be an N-way (where N is a number) cache that includes multiple sets or may be a simple set associative cache. A portion of the cache is divided into a number of blocks where each of the blocks is used to store data associated with a particular stream. Thus, different streams utilize different portions of the cache structure. In order to support the division of the stream portion of the cache into multiple blocks, addresses corresponding to stream data operations are modified for use in addressing the cache.

Abstract: A memory cache system is used in a multiprocessor environment. The first processor accesses data using a first level 1 cache, and the second processor accesses data using a second level 1 cache. A storage control circuit is positioned between the first and second level 1 caches and a level 2 cache and main memory. The level 2 cache maintains copies of data in main storage and further maintains an indication of those level 1 caches having copies of data and whether those copies have been modified. When a processor accesses data that is not resident in the connected level 1 cache, a request is delivered to the level 2 cache for this data. The level 2 cache then determines whether it can return a copy of the data to the level 1 cache or must access the data from main memory.

Abstract: System and method for controlling the contents of a browser cache. A data stream from a host server to a client browser includes a clear cache tag. Responsive to the clear cache tag, the browser clears its cache. The data stream may also include a start cache tag, and one or more data files which are cached by the client browser. Responsive to the clear cache tag, the browser cache is cleared of data files received in the data stream between the start cache tag and the clear cache tag, or alternatively of all data files in cache associated with a cache identifier received in the start cache and clear cache tags. Either the client local file system or a field in a cache table is used to differentiate between successive start cache tags.

Abstract: Disclosed is a predictive instruction cache system, and the method it embodies, for a VLIW processor. The system comprises: a first cache; a real or virtual second cache for storing a subset of the instructions in the second cache; and a real or virtual history look-up table for storing relations between first instructions and second instructions in the second cache. If a first instruction is located in a stage of the pipeline, then one of the relations will predict that a second instruction will be needed in the same stage a predetermined time later. The first cache can be physically distinct from the second cache, but preferably is not, i.e., the second cache is a virtual array. The history look-up table can also be physically distinct from the first cache, but preferably is not, i.e., the history look-up table is a virtual look-up table. The first cache is organized as entries.

Abstract: A size configurable data buffer includes a plurality of data cache memory registers and a variable number of prefetch memory registers. A computer controller determines the allocation of the data buffer which is data cache memory registers or prefetch memory registers. The size configurable data buffer may be included within a single size configurable data buffer SRAM circuit.

Abstract: The present invention is a method and apparatus for preventing the occurrence of deadlocks from the execution of multiply-initiated multiply-sourced variable delay system bus operations. In general, each snooper excepts a given operation at the same time according to an agreed upon condition. In other words, the snooper in a given cache can accept an operation and begin working on it even while retrying the operation. Furthermore, none of the active snoopers release an operation until all the active snoopers are done with the operation. In other words, execution of a given operation is started by the snoopers at the same time and finished by each of the snoopers at the same time. This prevents the ping-pong deadlock by keeping any one cache from finishing the operation before any of the others.

Abstract: A computing apparatus connectable to a cache and a memory, includes a system port configured to receive an atomic probe command or a system data control response command having an address part identifying data stored in the cache which is associated with data stored in the memory and a next coherence state part indicating a next state of the data in the cache. The computing apparatus further includes an execution unit configured to execute the command to change the state of the data stored in the cache according to the next coherence state part of the command.

Abstract: According to one embodiment, a computer system is disclosed. The computer system includes a processor, a memory, an inverting device, a storage device coupled to the inverting device and a device coupled to the storage device. The device receives byte enable information and inverted information and provides inverted byte enable information to the memory upon a write back operation to the memory.

Abstract: A cache coherency protocol uses a “Exclusive-Deallocate” (ED) coherency state to indicate that a particular value is currently held in an upper level cache in an exclusive, unmodified form (not shared with any other caches of the computer system, including caches associated with the same processing unit), so that the value can conveniently be modified without any lower level bus transactions since no lower level caches have allocated a line for the value. If the value is subsequently modified in the upper level cache, its coherency state is simply switched to “modified” without the need for any bus transactions. Conversely, if the value is evicted from the upper level cache without ever having been modified, it can be loaded into the lower level cache with a coherency state indicating that the lower level cache contains the unmodified value exclusive of all other caches in other processing units of the computer system.

Abstract: A multiple agent system providing each of a plurality of agents, i.e., processors, access to a shared synchronous memory. A super agent may be an agent from among a plurality of agents which accesses a shared synchronous memory most frequently. The super agent has direct access to the shared synchronous memory, without negotiation and/or arbitration, while the non-super agents access the shared synchronous memory under the control of an arbiter-and-switch. Open windows are generated when the super agent is not accessing the shared synchronous memory. The non-super agents can be allowed interim access to the shared synchronous memory even before the super agent terminates ownership of the shared synchronous memory.

Abstract: A data processing system, circuit arrangement, integrated circuit device, program product, and method utilize source identification information to selectively route data to different memory sources in a shared memory system. This permits, for example, data to be routed to only a portion of the memory sources associated with a given requester, thereby reducing the bandwidth to other memory sources and reducing overall latencies within the system. Among other possible information, the source identification information may include an identification of which memory source and/or which level of memory is providing the requested data, and/or an indication of what processor/requester and/or what type of instruction last modified the requested data.

Abstract: A computer system comprises a plurality of processing modules that can be configured into different partitions within the computer system, and a main memory. Each partition operates under the control of a separate operating system. At least one shared memory window is defined within the main memory to which multiple partitions have shared access, and each partition may also be assigned an exclusive memory window. Program code executing on different partitions enables those partitions to communicate with each other through the shared memory window. Means are also provided for mapping the physical address space of the processors in each partition to the respective exclusive memory windows assigned to each partition, so that the exclusive memory windows assigned to each partition appear to the respective operating systems executing on those partitions as if they all start at the same base address.

Abstract: A method and apparatus for asynchronously sharing a networked backup device among multiple users. A series of processes opportunistically perform operations, broadcast requests for physical media based upon the operations, and provide a series of canceling and status checking interfaces for users.

Abstract: A method and apparatus for managing data storage in a computer system including a host computer and a storage system that stores data accessed by the host computer. A performance condition that impacts system performance is detected, and in response thereto, the data within the storage system is reconfigured to improve system performance. In one aspect, this detection and reconfiguration is done automatically within the storage system in a manner transparent to the host computer. Examples of performance conditions that can be detected and alleviated include logical volumes including hot spots that are larger than the cache storage dedicated to the volumes, data segments that are accessed frequently by the host but not sufficiently frequently so that they remain in the cache between accesses, and large data segments that are accessed frequently and sequentially by the host and are stored on the same physical device within the storage system.

Abstract: A processor architecture and associated method improve efficiency of memory accesses and thereby reduces power consumption. New addressing modes reduce most instructions to one or two bytes in length, including immediate addressing of 32-bit addresses. A full instruction set provides complete arithmetic and logical operations using index registers and accumulator while minimizing external memory access.

Abstract: Without making the address control more complex than necessary, a memory can be effectively utilized by accessing a square memory area. According to a processor of the present invention connected to memory apparatus having a two-dimensional memory area comprised of rows and columns, the processor comprises registers for storing a start address, an end address, and a number of columns per row of a square area on the memory. The registers are used to generate access addresses for accessing the square area. The processor is provided with the address generation and control unit for outputting the generated access addresses. The address generation and control unit includes a modulo addressing control unit for generating the access addresses for cyclically accessing the square area. A square circulation mode information decides whether or not to access cyclically the square area. Based on a value of the square circulation mode information, whether or not to cyclically access the square area is decided.

Abstract: A method and apparatus are presented for implementing the next-address determination within a binary search algorithm. A binary search algorithm searches for a compared within a one dimensional sorted array of elements. Typically, a binary search algorithm comprises a comparator and a next address generator. The next address generator determines the address of the next array element (the “next address”) a comparator will search using both a “compared is greater” signal from the comparator and a signal which indicates the address of the last array the comparator searched (the “previous address”). The time needed to search an array for a compared inserts a delay in applications where a binary search algorithm is employed. One method of expediting the searching process is to minimize the number of gates between the input and output of the next address generator (the “critical path”).

Abstract: An Address Generation Unit (AGU) for a processor such as Digital Signal Processor that includes a data memory addressable to obtain X and Y operands and a program decoder. The AGU is connected to the data memory and the program decoder and includes two Arithmetic Logic Units that are used to generate the X and Y operands. Each alu a has a triplet of registers associated there with and include a linear path of a first DBLC adder. The first DBLC adder has an A input, a B input, a carry input connected to receive a first control signal, and a summation output. The linear path further includes a by pass connection for by passing the first DBLC adder. A multiplexer selects either the summation output or the by pass as a linear output. Each alu also includes a modulo path that is in parallel with the linear stage. The modulo path has a series connection of a Carry Sum Adder (csa) and a second DBLC adder with a modulo output. A second multiplexer selects either the linear output or the modulo output as a result.

Abstract: A general purpose register stores a 16-bit fixed length instruction. A bypass circuit speedily outputs the result of a comparison instruction when the next conditional branch instruction is executed. An ALU performs a logic process and so forth. A high speed multiplying device/high speed dividing device performs an arithmetic operation at high speed. An address calculating portion calculates an address. An instruction decoder/pipeline controlling portion decodes an instruction and controls a pipeline. A dedicated control register is used as an interrupt stack pointer or the like. An interrupt controller performs a multiple interrupt process. A coprocessor bus is disposed independently from a data bus.

Abstract: The present invention provides an efficient method for fetching instructions having a non-power of two size. In one embodiment, a method for fetching instructions having a non-power of two size includes fetching a first instruction cache line having a power of two size for storage in a first line buffer of an instruction fetch unit of a microprocessor, fetching a second instruction cache line having a power of two size for storage in a second line buffer of the instruction fetch unit, and extracting and aligning instruction data stored in the first line buffer and the second line buffer to provide an instruction having a non-power of two size.

Abstract: A microprocessor with reduced context switching overhead and a corresponding method is disclosed. The microprocessor comprises a working register file that comprises dirty bit registers and working registers. The working registers including one or more corresponding working registers for each of the dirty bit registers. The microprocessor also comprises a decoder unit that is configured to decode an instruction that has a dirty bit register field specifying a selected dirty bit register of the dirty bit registers. The decoder unit is configured to generate decode signals in response. Furthermore, the working register file is configured to cause the selected dirty bit register to store a new dirty bit in response to the decode signals. The new dirty bit indicates that each operand stored by the one or more corresponding working registers is inactive and no longer needs to be saved to memory if a new context switch occurs.