Abstract: To provide a semiconductor storage apparatus and a manufacturing method thereof in which a memory cell source area is not silicided and a resistance dispersion caused by insufficient silicidation is therefore eliminated, and in which a silicide film is prevented from being formed in the step portion of a self-aligned source structure and therefore a resistance dispersion by a disconnected silicide film is not generated. In a semiconductor storage apparatus having a memory cell portion in which a source area is formed by a self-aligned process, a silicide blocking portion is disposed in a part of the surface of a source diffusion layer such that the resistance dispersion caused by the insufficient silicidation of the source diffusion layer is not generated.

Abstract: A semiconductor body has first and second opposed major surfaces. A first region meets the first major surface and at least one second region meets the second major surface. The semiconductor body provides a voltage-sustaining zone between the first and second regions. The voltage sustaining zone has third regions of one conductivity type interposed with fourth regions of the opposite conductivity type with the second and third regions providing a rectifying junction such that, in use, when the rectifying junction is forward biased in one mode of operation by a voltage applied between the first and second regions, a main current path is provided between the first and second major surfaces through the first region, the voltage-sustaining zone and the second region.

Abstract: By improving profile of impurity concentration in a channel portion of an FET or an IGBT of a trench gate type, variation of threshold value is lessened, and a destruction caused by current concentration is prevented while suppressing deterioration of cut-off characteristics. An island of a base region of p-type is formed in a semiconductor substrate of n-type by carrying out high acceleration ion implantation twice followed by annealing, so that the impurity concentration profile in a channel portion changes gradually in a depth direction. Accordingly, it is possible to lessen variation of the threshold value and to reduce pinch resistance while at the same time improving sub-threshold voltage coefficient and conductance characteristics.

Abstract: An LDMOS structure is formed in a region of a first type of conductivity of a semiconductor substrate and comprises a gate, a drain region and a source region. The source region is formed by a body diffusion of a second type of conductivity within the first region, and a source diffusion of the first type of conductivity is within the body diffusion. An electrical connection diffusion of the second type of conductivity is a limited area of the source region, and extends through the source diffusion and reaches down to the body diffusion. At least one source contact is on the source diffusion and the electrical connection diffusion. The LDMOS structure further comprises a layer of silicide over the whole area of the source region short-circuiting the source diffusion and the electrical connection diffusion. The source contact is formed on the silicide layer.

Abstract: Bipolar junction transistors utilize trench-based base electrodes and lateral base electrode extensions to facilitate the use of preferred self-alignment processing techniques. A bipolar junction transistor is provided that includes an intrinsic collector region of first conductivity type in a semiconductor substrate. A trench is also provided in the substrate. This trench extends adjacent the intrinsic collector region. A base electrode of second conductivity type is provided in the trench and a base region of second conductivity type is provided in the intrinsic collector region. This base region is self-aligned to the base electrode and forms a P-N rectifying junction with the intrinsic collector region. An emitter region of first conductivity type is also provided in the base region and forms a P-N rectifying junction therewith.

Abstract: A high resistivity silicon for RF passive operation including CMOS structures with implanted CMOS wells and a buried layer under the wells formed by deep implants during well implantations.

Abstract: A semiconductor device comprises a relatively lower threshold level MOSFET and relatively higher threshold level MOSFETs of n- and p-types. The higher threshold level MOSFETs have gate oxide films which is thicker than that of the lower threshold level MOSFET and, in addition, the gate oxide film of the higher threshold level MOSFET of n-type is thicker than that of the higher threshold level MOSFET of p-type. To fabricate the semiconductor device, implantation treatments of fluorine ions are carried out before the gate oxide treatment. Specifically, as for the higher threshold level MOSFETs of n- and p- types, implantation treatments of fluorine ions are independently carried out with unique implantation conditions.

Abstract: The ESD protective circuit proceeds from a modified lateral pnpn “latch-up” protective structure having a highly doped n-type zone, which is arranged on the well boundary, along that section of the periphery of the well which runs between the two oppositely doped regions. The highly doped zone is formed of pads arranged with intermediate spacing along the section of the periphery of the well. The result is a low triggering voltage in conjunction with a low on resistance.

Abstract: A microelectronic device fabricating method includes providing a substrate having a mean global outer surface extending along a plane. A first portion is formed over the substrate comprising a straight linear segment which is angled from the plane and forming a second portion over the substrate comprising a straight linear segment which is angled from the plane at a different angle than the first portion. A layer of structural material is formed over the first and second portions. The structural material layer is anisotropically etched and a first device feature is ultimately left over the first portion having a first base width and a second device feature is ultimately left over the second portion having a second base width which is different from the first base width. Integrated circuitry includes a substrate having a mean global outer surface extending along a plane.

Abstract: A micromechanical sensor is described which contains electrodes that are disposed on a substrate, and electrode bars made of silicon that can move with regard to the electrodes. A deformation of the substrate is measured by determining differential changes in a capacity of the electrode bars in comparison to adjacently disposed electrodes. Two groups of electrode bars are preferably used which are interlocked with one another in an alternating comb-like manner, which, are separate from one another, and are interconnected at the ends thereof in an electrically conductive manner, and which are anchored on the substrate.

Abstract: A light-receiving element having a light-receiving portion is formed on a chip surface. A digital circuit element, an analog circuit element and a circuit adjusting element are provided for cooperatively processing a detection signal produced from the light-receiving element. And, a light-shielding film is provided for selectively setting a light-receiving region on the chip surface.

Abstract: A microelectromechanical switch includes a substrate, an insulator layer disposed outwardly from the substrate, and an electrode disposed outwardly from the insulator layer. The switch also includes a dielectric layer disposed outwardly from the insulator layer and the electrode, the dielectric layer having a dielectric constant of greater than or equal to twenty. The switch also includes a membrane layer disposed outwardly from the dielectric layer, the membrane layer overlying a support layer, the support layer operable to space the membrane layer outwardly from the dielectric layer.

Abstract: A semiconductor substrate has a main surface oriented to {1 1 0} face, a first orientation flat formed on a peripheral portion of a semiconductor substrate and oriented to one of {1 1 1} face and {1 1 2} face perpendicular to the {1 1 0} face. It is easy to select (determine) {1 1 1} face for forming a trench in the semiconductor substrate based on the first orientation flat. In addition, the trench whose face is oriented to {1 1 1} face has few defects on its inner surface.

Abstract: A layer of doped or undoped germanosilicate glass is formed on a substrate and the layer of germanosilicate glass is thermally treated in steam to remove germanium from the germanosilicate glass, and thereby raise the reflow temperature of the germanosilicate glass so treated. The layer of germanosilicate glass on the substrate may be a nonplanar layer of germanosilicate glass. When thermally treating the nonplanar layer of germanosilicate glass in steam, the layer of germanosilicate glass may be planarized simultaneously with the removal of germanium from the planarized germanosilicate glass. This process may be repeated to create a hierarchy of reflowed glass where each underlying layer reflows at a higher temperature than the next deposited glass layer. The steam thermal treatment step may be preceded by a thermal pretreatment of the layer of germanosilicate glass in at least one of a noble gas and nitrogen gas, to reflow the layer of germanosilicate glass.

Abstract: A compensation component includes a drift path formed of p-conducting and n-conducting layers which are led around or along a trench. A process for producing the compensation component is also provided.

Abstract: A semiconductor device enabling precise and accurate measurement of an inspection mark in a simple manner is obtained. The semiconductor device includes a device forming area and a dicing line area arranged to surround the device forming area on a semiconductor substrate. In the dicing line area, first and second registration marks formed in different shots are provided, and the first and second registration marks include auxiliary marks for identifying the first and second registration marks.

Abstract: A method of forming a composite silicon oxide layer over a semiconductor device. The composite silicon oxide layer is formed between the semiconductor device and a doped silicate glass layer. The composite silicon oxide layer comprises two silicon oxide layers, each having a different silicon/oxide composition. The oxygen-rich oxide layer or silicon dioxide layer is formed directly above the semiconductor device, and the silicon-rich oxide layer is formed above the silicon dioxide layer next to the doped silicate glass layer. Both the silicon dioxide layer and the silicon-rich oxide layer are formed in the same plasma deposition chamber.

Abstract: A semiconductor device includes a substrate and wirings located on the substrate. A passivation film including a first insulating film containing an impurity is located on the wirings. The first insulating film is formed from silicon oxide film materials containing greater than one percent carbon.

Abstract: A semiconductor device comprises: a first semiconductor chip having a control circuit; a plurality of second semiconductor chips whose operation is controlled by the control circuit; and a resin sealing body for sealing the first semiconductor chip and the plurality of second semiconductor chips, wherein: the first semiconductor chip is arranged in the central portion of the resin sealing body; and the plurality of second semiconductor chips are arranged on a periphery of the first semiconductor chip. A fuse element is further arranged outside the plurality of second semiconductor chips.

Abstract: A semiconductor device comprising a lead frame that includes a large area mount pad having small elevated pads to which a semiconductor chip is attached. The small mount pads coupled with usage of a minimal amount of chip attach adhesive provide improved reliability against vapor phase package cracking, and further allow a given lead frame to be used by a family of chip sizes and shapes. The large pad provides good thermal dissipation, as well as stress relief during fabrication of the lead frame.

Abstract: In a surface-mounting-type electronic-circuit unit, circuit elements, including capacitors, resistors, and inductive devices, and electrically conductive patterns connected to the circuit elements are formed on an alumina board as thin films. Semiconductor bare chips for a diode and a transistor are wire-bonded to connection lands in electrically conductive patterns. And end-face electrodes connected to grounding electrodes, input electrodes, and output electrodes of electrically conductive patterns are formed at side faces of the alumina board.

Abstract: A stackable Ball Grid Array (BGA) semiconductor chip package and a fabrication method thereof increases reliability and mount density of a semiconductor package. The stackable BGA semiconductor chip package includes a supporting member that includes a supporting plate and a supporting frame formed on edges of the supporting plate. Conductive patterns are formed in and extend through the supporting member. First metal traces are formed on a bottom of the supporting plate and the first metal traces are connected to first ends of the conductive patterns in the supporting member. Second metal traces are attached to an upper surface of a semiconductor chip, and the semiconductor chip is attached to the supporting member. The second metal traces are connected to bond pads of the chip, and to upper ends of the conductive patterns in the supporting member. A plurality of conductive balls are then attached to exposed portions of the first and/or the second metal traces.

Abstract: An apparatus package for high-temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor devices.

Abstract: A method and apparatus for testing unpackaged semiconductor dice having raised contact locations are disclosed. The apparatus uses a temporary interconnect wafer that is adapted to establish an electrical connection with the raised ball contact locations on the die without damage to the ball contact locations. The interconnect is fabricated on a substrate, such as silicon, where contact members are formed in a pattern that matches the size and spacing of the contact locations on the die to be tested. The contact members on the interconnect wafer are formed as either pits, troughs, or spike contacts. The spike contacts penetrate through the oxide layer formed on the raised ball contact locations. Conductive traces are provided in both rows and columns and are terminated on the inner edges of the walls of the pits formed in the substrate.

Abstract: An SO-8 type package contains a control MOSFET die mounted on one lead frame section and a synchronous MOSFET and Schottky diode die is mounted on a second lead frame pad section. The die are interconnected through the lead frame pads and wire bonds to define a buck converter circuit and the die and lead frame pads are overmolded with a common insulation housing.

Abstract: A method for making a bond-wire interconnect to pass signals between different substrates is described. According to this process, a first compensated bond wire interconnect is made to connect two substrates of a first type at an operating frequency, the first interconnect comprising a bond-wire of a fixed length and a first pair of compensation structures formed from a lowpass filter prototype. A second compensated bond wire interconnect is made to connect two substrates of a second type at the operating frequency, the second interconnect having a bond-wire of the fixed length and a second pair of compensation structures formed from the lowpass filter prototype. A bond-wire of the fixed length, one compensation structure from the first pair, and one compensation structure from the second pair, are combined to make a third compensated bond wire interconnect to connect a substrate of the first type with a substrate of the second type at the operating frequency.

Abstract: In a semiconductor device, an insulating substrate has a plurality of through holes. A plurality of conductive posts are buried in the through-holes. The conductive posts are classified to at least one first conductive post and a pair of second conductive posts. A semiconductor element has at least one surface electrode at a surface side. The surface electrode is connected to the first conductive post by a face-down method. A metal block is formed to a square-arch shape in a cross sectional view and has a ceiling portion and both end portions. A back surface of the semiconductor element is secured to the ceiling portion while the both end portions are secured to the second conductive posts. A sealing-resin seals the semiconductor element.

Abstract: A reliable, chip scale or flip chip semiconductor device which can be directly attached to a PC board without the use of an underfill material to absorb stress on the solder joints interconnecting the device and board is provided by a silicon chip, having the substrate thinned until the chip thickness is in the range of 50 to 250 microns, attaching a backing or cap layer with specific thermal properties to approximate those of a printed circuit board (PCB), and providing solder bump contacts attached to the input/output terminals.

Abstract: The present invention discloses an improved method for carry out a flip chip packaging process for attaching a semiconductor integrated circuit (IC) wafer having a plurality of input/output terminals, to a substrate. The method includes the steps of: 1) securely placing a plurality of solder balls on the substrate with each of said solder balls corresponding to a location of one of the input/output terminals on the integrated circuit wafer; 2) flipping the integrated circuit wafer for aligning each of the input/output terminals of the IC wafer to one of the solder balls; and 3) mounting the IC wafer onto the substrate for placing the I/O terminals on a corresponding solder ball and applying a reflow temperature for soldering the IC wafer to the substrate.

Abstract: The invention relates to an electronic device having a multiplicity of contact bumps and an intermediate support. In this case, the intermediate support connects the multiplicity of contact bumps to contact areas of a semiconductor chip via a multiplicity of flat conductors which have contact connecting lugs exposed in a bonding channel window of the intermediate support. The contact areas are configured in the bonding channel window via the bonded contact connecting lugs of the flat conductors. The width of the bonding channel window is increasingly greater with increasing distance from the neutral point of the semiconductor chip.

Abstract: A semiconductor device comprises a semiconductor element mounted on a first surface of a wiring substrate, and a plurality of conductive land portions formed and exposed at a second surface of the wiring substrate which is opposite to the first surface. A plurality of solder balls are respectively joined to the plurality of conductive land portions. A plurality of reinforcement resin film portions are formed to reinforce coupling between the solder balls and the conductive land portions. Each of the reinforcement resin film portions is formed around a portion of the solder ball joining to the conductive land portion. Each of the reinforcement resin film portions being bent to form a portion along the wiring substrate and a portion along the side surface of the solder ball. The coupling between the solder balls and the conductive land portions is reinforced by elastic force of the bent portions of the reinforcement resin film portions.

Abstract: Planarizing solutions, and their methods of use, for removing titanium nitride from the surface of a substrate using a fixed-abrasive planarizing pad. The planarizing solutions take the form of an etchant solution or an oxidizing solution. The etchant solutions are aqueous solutions containing an etchant and a buffer. The etchant contains one or more etching agents selective to titanium nitride. The oxidizing solutions are aqueous solutions containing an oxidizer and a buffer. The oxidizer contains one or more oxidizing agents selective to titanium nitride. In either solution, i.e., etchant or oxidizing solution, the buffer contains one or more buffering agents. Titanium nitride layers planarized in accordance with the invention may be utilized in the production of integrated circuits, and various apparatus utilizing such integrated circuits.

Abstract: A metal wire comprising a metal member and a barrier metal is formed within each of trenches formed in an insulating film placed on a semiconductor substrate. A first metal diffusion preventive film is formed on the insulating film so as to make contact with an upper portion of the barrier metal formed on the sides of the metal. Further, a second metal diffusion preventive film is formed on the first metal diffusion preventive film and the metal wire.

Abstract: A method is provided for wiring semiconductor integrated circuits which produces a shielding effect while increasing the wiring area to a small extent.

Abstract: The present invention provides a high-frequency signal amplification device, in which insufficient isolation is compensated and which is made smaller, as well as a method for manufacturing the same. A substrate, in which a plurality of metal conductors arranged between the plurality of dielectric layers and/or at a surface of the dielectric multilayer substrate are exposed at a first region of the surface, and a metal surface that is arranged at a position lower than the plurality of metal conductors is exposed from a remaining portion of the first region not including the region on which the plurality of metal conductors are arranged, is used as a dielectric multilayer substrate. The semiconductor element is mounted in the first region such that a high-frequency signal is input into the semiconductor element via at least one of the plurality of metal conductors, and an amplified high-frequency signal is output from the semiconductor element via at least another one of the plurality of metal conductors.

Abstract: Described in the present invention is a semiconductor device in which a plurality of interconnect lines are disposed, through an insulating layer, on the same layer above a semiconductor substrate having a semiconductor element; a first interlevel insulator is formed selectively in a narrowly-spaced region between adjacent interconnect lines; a second interlevel insulator is formed in a widely-spaced region between said adjacent interconnect lines, and the first interlevel insulator has a smaller dielectric constant than the second interlevel insulator. According to such a constitution, strength and reliability can be heightened and performance can be improved easily even in a miniaturized interconnect structure.

Abstract: A flip chip type semiconductor device is provided with a semiconductor chip with a plurality of pad electrodes on one surface. A solder electrode is connected to each pad electrode and a metallic post is connected to each solder electrode. The surface of the semiconductor chip on a side on which the pad electrodes are provided is coated with an insulating resin layer and whole the pad electrode and solder electrode and part of the metallic post are buried in the insulating resin layer. The remaining portion of the metallic post is projected from the insulating resin layer to form a protrusion. Then, an outer solder electrode is formed so as to cover this protrusion. The outer solder electrodes are arranged in a matrix on the insulating resin layer. The height of the protrusion is made 7 to 50% of the distance between an end of the outer solder electrode and the surface of the insulating resin layer.

Abstract: For a four-stroke engine, a carburetor with a fuel pump diaphragm which defines a fuel pump chamber on one side and a pressure pulse chamber on its other side in communication with the engine to receive pressure pulses which actuate the fuel pump diaphragm to draw fuel into the carburetor and to discharge fuel under pressure to a downstream fuel metering assembly. An air passage communicates an air supply with the pressure pulse chamber to provide an air flow within the pressure pulse chamber which sweeps away, dries out or aerates and removes any liquid fuel within the pressure pulse chamber to avoid puddling of liquid fuel therein. In one form, a throttle valve carried by the carburetor body for movement between idle and wide open positions also actuates a valve which controls the flow of fluid through the air passage as a function of the position of the throttle valve.

Abstract: A carburetor comprising four distinct features providing improved performance: A sculpted chamber comprising D-shaped configuration; a fuel flow interference needle multiply comprised with bevel zones; easily accessible needle advancement and retraction means; and a centrally disposed auxiliary fuel jet aperture emission site.

Abstract: Retroreflective prism sheeting is formed in a mold with textured facets and/or windows thereon. Smaller prisms are formed adjacent larger prisms. Optionally, the optical axis of the prisms may be tilted with respect to one another, preferably in a negative direction. The textured facets or windows provide more uniform retroreflected light intensity distribution and whiteness of the sheeting.

Abstract: Apparatus for producing thermoplastic injection-molded parts reinforced with long fibers, includes a compounder having two meshing screws rotating in a same direction for continuously generating a stream of melt of thermoplastic material reinforced with long fibers. Melt is alternatingly conducted to at least two piston and cylinder units for injection into at least one cavity of an injection mold at a suitable pressure. Each of the piston and cylinder units includes a cylinder and a differential piston movably received in the cylinder and dividing the cylinder into a feed chamber and an injection chamber, wherein the piston has a relatively greater piston surface, adjacent the injection chamber, and a relatively smaller piston surface, adjacent the feed chamber.

Abstract: Near net shape free standing articles can be produced by chemical vapor deposition techniques when a suitable substrate is suspended in a chemical vapor deposition zone according to the disclosed technique. By suspending such substrates from linear suspension supports such as ropes, cables and wires, multiple near net shape articles can be produced with substantial manufacturing cost savings over previously employed techniques.

Abstract: A thermally conductive and electrically insulative polymer composition and a method for creating the same is provided. Thermally conductive filler material is coated with a thermally conductive and electrically insulative coating material and mixed with a base polymer matrix. The mixture is molded into the desired shape. The electrically insulative coating material prevents the transfer of electricity through the filler material thus resulting in an electrically insulative composition.

Abstract: Particles of silica-rich plant material are bonded into a rigid unitary body. The silica content of such materials is believed to enter into bonding reactions when the materials are combined with a polymeric resin base material such as PAPI that has been previously converted by reaction with a colloidal gel formed from silica and a basic solution. The resulting product exhibits characteristics superior to most engineered wood products. A theoretical analysis of the bonding chemistry is proposed.

Abstract: A thermoplastic shaped resin article may include, for example, a shaped base material and a thermoplastic resin sheet. A discontinuous metal film may be disposed on one surface of the resin sheet. The base material may be adhered to the resin sheet so that the metal film faces the base material. As a result, shaped resin articles may be prepared that have a metallic appearance and transmit visible light.

Abstract: Pultruded composites of longitudinally oriented reinforcing fibers in a matrix of a thermoplastic resin are shaped in-line during the pultrusion process to provide a variety of non-linear or variable cross-section articles.

Abstract: Biodegradable starch-based extruded products and methods of manufacturing those products are provided. In particular, extruded starch products processed by compression, stretching or compression and stretching provide excellent flexibility, pliability, dimensional stability, resiliency, abrasion resistance and other properties making them attractive for use as packaging materials.

Abstract: A resilient article and method of manufacturing the same using recycled materials are described. Predetermined amounts of thermoset material and thermoplastic binder are mixed and extruded into a die, from which the mixture emerges in the form of a sheet having the approximate thickness of the finished article. The mixture then enters a calibrator, which more precisely shapes the sheet to the desired thickness. The sheet is then cooled and cut to the desired dimensions to provide the finished article. The thermoset material used in the mixture is preferably ground vehicle tire rubber with the fabric and metal removed and the thermoplastic binder is preferably waste polyethylene. The apparatus and method according to the present invention is particularly well suited for manufacturing resilient articles for use as expansion joint material.

Abstract: Lids, for example lids for machine-lidding of e.g. beakers, dishes, menu dishes, goblets, small packages etc., containing a substrate material featuring, with respect to a container on which the lids are used, a smooth outward facing surface bearing printing. On the inward facing side of the lid is a sealing layer deposited by extrusion laminate coating. The sealing layer exhibits on the free surface embossing with a depth of roughness of up to 50 &mgr;m. The embossing is transferred to the sealing layer in the form of a roughness pattern on the cooling roll on depositing the laminate coating of the substrate material and extruded sealing layer. The free side of the substrate material is smooth and exhibits no embossing. Printing on the free surface is therefore of higher quality. The extruded sealing layer on the substrate material exhibits embossing on the free side. If the lids are drawn from a stack of lids, for example in a filling machine, the embossing allows them to be separated individually.

Abstract: The combination of fluoropolymer processing aid with foam cell nucleating agent gives a combined processing aid that is far superior to either individually when used in the extrusion of melt processible polymers.