Patents Issued in December 6, 2001
  • Publication number: 20010049730
    Abstract: Disclosed is a communications network element that is capable of routing signaling messages and also performing inter-network management functions in a converged telephony-data network environment. A signaling gateway routing node is adapted to facilitate signaling communication between nodes in a signaling system 7 network and nodes in an Internet protocol (IP) type network. In addition to basic message routing functionality, the signaling gateway routing node is adapted to notify nodes in the IP network when a node in the SS7 network becomes congested or unavailable. In certain cases, the signaling gateway selectively notifies only IP nodes that are concerned with the status of the troubled SS7 node, while in other cases, notification messages are broadcast to all relevant IP nodes. The signaling gateway also serves to filter redundant congestion status queries or polling type messages that are conveyed from IP nodes through to the distressed SS7 node.
    Type: Application
    Filed: January 26, 2001
    Publication date: December 6, 2001
    Inventors: Dan Alan Brendes, Joseph William Keller, Seetharaman Khadri
  • Publication number: 20010049731
    Abstract: The invention relates to a method of managing a suspend state of a packet-switched service in a system which comprises a terminal (MS) and another peer (12), there being a packet-switched connection between the terminal and the other peer over which the terminal and the other peer transmit packets to each other. The terminal (MS) is able to use only either a circuit-switched service or a packet-switched service at the same time. When the terminal (MS) switches to the suspend state in the packet-switched service to use a circuit-switched service, a predetermined first packet (31) is transmitted from the terminal (MS) to the other peer (12) to prevent transmission of packets from the other peer (12) to said terminal (MS) during the suspend state. The invention also relates to a terminal and software.
    Type: Application
    Filed: May 29, 2001
    Publication date: December 6, 2001
    Inventors: Jarmo Kuusinen, Mika Liljeberg
  • Publication number: 20010049732
    Abstract: According to the invention, a content exchange apparatus for cacheing content objects is disclosed. Included in the content exchange apparatus are a content store, a content tracker, an origin server database, and a catalog of content objects. The content store includes a plurality of content objects. A determination is made by the content tracker determines as to which content objects are stored in the content store. The origin server database includes a list of origin servers associated with the content exchange. The catalog of content objects stored in the content store is maintained.
    Type: Application
    Filed: May 29, 2001
    Publication date: December 6, 2001
    Inventors: Nathan F. Raciborski, Mark R. Thompson
  • Publication number: 20010049733
    Abstract: A content distribution system, capable of creating content and changing itself easily, is provided. In a content server 30, contents created by data written in the basic language, which can easily be converted into other languages, are stored. The content server 30 identifies the type of a terminal device accessing thereto. Content being requested is converted into data written in a display language appropriate for the terminal device on a real time basis and the resultant data is transmitted to the terminal device. At the terminal device, display according to the display language data is carried out.
    Type: Application
    Filed: March 30, 2001
    Publication date: December 6, 2001
    Inventors: Hiroshi Tokumaru, Hiroshi Yoshida, Kouichi Ozawa
  • Publication number: 20010049734
    Abstract: In the use-limitation homepage providing system, the communication terminal (15) reads barcode data on the card (21) and transmits product identification information therein and IP address of the terminal (15) to the URL conversion server (17) through the Internet (11). The URL conversion server (17) obtains URL address of the management server (19) corresponding to the received product identification:information and transmits the product identification information and IP address of the communication terminal (15) to the management server (19) addressed by URL address. When receiving the product identification information through the URL conversion server (17), the management server (19) transmits a permission to access a use-limitation homepage corresponding to the product identification information.
    Type: Application
    Filed: May 23, 2001
    Publication date: December 6, 2001
    Inventors: Youko Suwabe, Masao Isshiki, Yuka Yoda, Morio Hirahara, Takuya Kishimoto, Mitsuo Takahashi
  • Publication number: 20010049735
    Abstract: A calculation service providing system, comprising calculation servers, a Web server and terminals which are connected to one another on a network, wherein each of the calculation servers stores one or more applications for providing calculation service, wherein the Web server stores and publishes on the network one or more procedure data files, in each of which procedure data defining a calculation service using the one or more applications stored in one or more of the calculation servers is described, and wherein each of the terminals executes a procedure processing program for having one or more of the calculation servers execute one or more applications on the basis of the procedure data described in the procedure data file downloaded from the Web server.
    Type: Application
    Filed: May 25, 2001
    Publication date: December 6, 2001
    Inventors: Eiichi Nakano, Hitoshi Nonomura
  • Publication number: 20010049736
    Abstract: An interactive information delivery system server 2, delivering text or other visual data to a display unit 3 is accessed by a user by means of his own telephone 6, through an interface unit 1.
    Type: Application
    Filed: March 18, 1998
    Publication date: December 6, 2001
    Inventors: ROBIN THOMAS MANNINGS, DAVID LYNTON GIBSON
  • Publication number: 20010049737
    Abstract: A method of configuring a network access device connected to an access network connected to a plurality of service networks, the network device having a first network address allocated to a subscriber of services of a first service provider provided by a first service network, with a new network address allocated to a second subscriber of services of either the first service provider, or a second service provider provided by a second service network. The method comprises the steps of: displaying a plurality of service providers on a graphical user interface; in response to a subscriber selection on the graphical user interface, sending a request from the network access device to the access network requesting a change to a second service provider; receiving a response from the access network; and initiating a network address change request using a configuration protocol.
    Type: Application
    Filed: March 20, 2001
    Publication date: December 6, 2001
    Inventors: Sean E. Carolan, John W. Garrett, Charles Robert Kalmanek, Han Q. Nguyen, Kadangode K. Ramakrishnan
  • Publication number: 20010049738
    Abstract: A call originating method applied to a mobile communication terminal for connecting the mobile communication terminal to a service provider over network using a connection information item corresponding to a service provider and a user's present location, the method comprising storing a plurality of connection information items corresponding to respective regional service providers, in a memory device, specifying the user's present location, retrieving, from the memory device, the connection information items corresponding to the specified user's present location and a service that is required by the user requiring the network to connect the mobile communication terminal to the regional service provider, using a retrieved connection information item.
    Type: Application
    Filed: May 31, 2001
    Publication date: December 6, 2001
    Inventor: Miwako Doi
  • Publication number: 20010049739
    Abstract: In a device that interworks a VLAN network and an MPLS network, a VLAN ID is associated with an MPLS label. In a device that performs interworking from a VLAN network to an MPLS network, an output MPLS label is determined from a pair of a VLAN ID and the information in the layer 3 or layer 4 header of a packet. The output MPLS label is assigned an independent value for each VLAN. In a device that performs interworking from the MPLS network to another VLAN network, the input MPLS label is associated with a VLAN ID.
    Type: Application
    Filed: February 12, 2001
    Publication date: December 6, 2001
    Inventors: Koji Wakayama, Kenichi Sakamoto, Takeshi Aimoto, Takahisa Miyamoto
  • Publication number: 20010049740
    Abstract: Systems and methods for delivering streaming data content to a client device over a data communication network in response to a request for the data content from the client device. The client request is received by a server or a controller device that is typically located on a network switch device. If received by a server, the server sends a request to the controller device to control the transfer of the requested data to the client. The controller device includes the processing capability required for retrieving the streaming data and delivering the streaming data directly to the client device without involving the server system. In some cases, the controller device mirrors the data request to another controller device to handle the data processing and delivery functions. In other cases, the controller device coordinates the delivery of the requested data using one or more other similar controller devices in a pipelined fashion.
    Type: Application
    Filed: March 22, 2001
    Publication date: December 6, 2001
    Inventor: Wayne T. Karpoff
  • Publication number: 20010049741
    Abstract: A system and method for balancing the load on virtual servers managed by server array controllers at separate data centers that are geographically distributed on a wide area network such as the Internet. The virtual servers provide access to resources associated with a domain name request by a client program. When a Primary Domain Name System (DNS) determined the requested domain name is delegated to a EDNS, the EDNS employs metric information and statistics to resolve an ip address for a virtual server that is selected by the EDNS to optimally balance the load and provide access to resources associated with the domain name. The EDNS may employ a static or a dynamic load balancing method to select the virtual server most suited to balance the load across all of the virtual servers. The EDNS may include a Primary DNS or a Secondary DNS.
    Type: Application
    Filed: December 13, 1999
    Publication date: December 6, 2001
    Inventors: BRYAN D. SKENE, SCOTT P. TENNICAN, THOMAS E. KEE
  • Publication number: 20010049742
    Abstract: A flow control technique prevents overflow of a write storage structure, such as a first-in, first-out (FIFO) queue, in a centralized Duplicate Tag store arrangement of a multiprocessor system that includes a plurality of nodes interconnected by a central switch. Each node comprises a plurality of processors with associated caches and memories interconnected by a local switch. Each node further comprises a Duplicate Tag (DTAG) store that contains information about the state of data relative to all processors of a node. The DTAG comprises the write FIFO which has a limited number of entries. Flow control logic in the local switch keeps track of when those entries may be occupied to avoid overflowing the FIFO.
    Type: Application
    Filed: May 29, 2001
    Publication date: December 6, 2001
    Inventors: Simon C. Steely, Hari Krishan Nagpal, Stephen R. Van Doren
  • Publication number: 20010049743
    Abstract: A message transformation selection tool and method for use in a distributed message processing system running applications on subsystems using incompatible message formats, selects the most appropriate output message format for a given input message format. Firstly, the tool determines compatibility of each field of the input message format with fields of all possible output message formats. Next, it statistically analyses the values of message fields in messages stored in message logs for each of the subsystems. On the basis of this analysis, the tool selects the best fit output message into which to transform a given input message.
    Type: Application
    Filed: January 17, 2001
    Publication date: December 6, 2001
    Applicant: International Business Machines Corporation
    Inventors: Robert William Phippen, John Michael Knapman
  • Publication number: 20010049744
    Abstract: Significant performance improvements can be realized in data processing systems by confining the operation of a processor within its internal register file so as to reduce the instruction count executed by the processor. Data, which is sufficiently small enough to fit within the internal register file, can be transferred into the internal register file, and execution results can be removed therefrom, using direct memory accesses that are independent of the processor, thus enabling the processor to avoid execution of load and store instructions to manipulate externally stored data. Further, the data and execution results of the processing activity are also accessed and manipulated by the processor entirely within the internal register file. The reduction in instruction count, coupled with the standardization of multiple processors and their instruction sets, enables the realization of a highly scaleable, high-performing symmetrical multi-processing system at manageable complexity and cost levels.
    Type: Application
    Filed: March 2, 2001
    Publication date: December 6, 2001
    Inventors: Terrence Hussey, Donald W. Monroe, Arnold N. Sodder
  • Publication number: 20010049745
    Abstract: A method for forwarding of communications from a sender to a recipient through a separate forwarding server, using an address which is known or believed to be temporarily or permanently invalid to communicate with the recipient through a medium, including media other than that in which the address was formerly (but is not currently) valid. The invention enables and facilitates the transmission and reception of communications when the current destination of a communication to an intended recipient (e.g. street address, telephone number, e-mail address) is unknown to the sender, but a previous destination or other group or personal old address, now not currently active, is known. This method may be applied to electronic mail, telephony, postal mail, and other types of communications that require an addressed destination for the communication to be received.
    Type: Application
    Filed: May 3, 2001
    Publication date: December 6, 2001
    Inventor: Daniel Schoeffler
  • Publication number: 20010049746
    Abstract: A communication system which allows IP-based communication regardless of whether an Internet protocol (IP) connection exists in a mobile telephone network, and a method thereof are provided. The method includes the steps of receiving a request for an IP address of the other terminal, the request being made using a telephone number, checking whether or not an IP address corresponding to the telephone number is registered upon receipt of the request, and assigning an IP address of the other terminal corresponding to information from an IP address server, if the IP address is not registered. Thus, in a mobile telephone network using a telephone number, a terminal can carry out IP-based video and audio communications with the other terminal via a name server or network, regardless of an IP connection of the other terminal.
    Type: Application
    Filed: January 31, 2001
    Publication date: December 6, 2001
    Inventor: Sang-hyun Shin
  • Publication number: 20010049747
    Abstract: A method and apparatus for mapping between a host name and a host address is provided. According to one aspect of the invention, a multi-threaded name server handles multiple concurrent name requests, and is particularly well suited for a host system controlling information relating to a large number of domain names. In a preferred embodiment as described herein, a multi-threaded name server comprises a request dispatcher thread capable of spawning multiple child threads. For each name request received by the request dispatcher thread, the request dispatcher spawns a child thread to handle the request. The child threads query a host name hash table to determine whether the host name hash table comprises a host name matching a host name in the name request. The result is a multi-threaded, non-blocking name server capable of handling multiple concurrent name requests for a large number of domain names.
    Type: Application
    Filed: August 6, 1999
    Publication date: December 6, 2001
    Applicant: NAMEZERO.COM, INC.
    Inventor: FRANCIS J. STANBACH
  • Publication number: 20010049748
    Abstract: Site access method enables to use support system site with a sense that the user accesses site which he or she uses daily when access is made via the accounting office site. The method enables the user to recognize the use of the support system on the side of the site which the user daily uses and enabling the side of the service provider to enjoy the benefit obtained through the expansion of usage by new users. When access to the support system site from the user terminal is access via the accounting office affiliated with the site, the support system site generates page information for the accounting office by changing the name of the service provider of the page information of the support system into the accounting office name or the like to transmit this generated page information to the user terminal of the accounting office site.
    Type: Application
    Filed: May 29, 2001
    Publication date: December 6, 2001
    Applicant: Casio Computer Co., Ltd.
    Inventors: Toshihito Terada, Kazumasa Morichika, Toshio Tohara, Masaaki Fukumura
  • Publication number: 20010049749
    Abstract: During recovery of a master system, a mismatch between data in the master system and that in a backup system is obviated quickly to shorten time consumed before resumption of operation of the master system. The backup system controls, as second difference information, update data generated over a substitutive operation period between occurrence of a disabled state of the master system and recovery thereof and when the master system is enabled to operate, a range of addition of first difference information inside the master system and the second difference information or only a range of the second difference information is copied to the master system to eliminate the data mismatch.
    Type: Application
    Filed: May 24, 2001
    Publication date: December 6, 2001
    Inventors: Eiju Katsuragi, Toshio Nakano, Yoshinori Okami, Takao Satoh
  • Publication number: 20010049750
    Abstract: A data-based software type link integrity module is implemented separately in hardware (e.g., using physical gates, using a microcontroller, etc.) and separated from core CPU functionality in a network device, such that the link integrity module may remain powered in a cold power mode (e.g., when core functionality is powered down). The separately powered data-based link integrity module is powered by an auxiliary backup power source. Thus, when in a power down mode (e.g., when in an ACPI defined D3 type cold state) a minimal power source may be used to power the separate link integrity module separate from the power source to the core network device functionality. The separately powered data-based link integrity module may be redundant to a software driver type data-based link integrity module implemented in core memory and enabled or disabled as desired.
    Type: Application
    Filed: January 17, 2001
    Publication date: December 6, 2001
    Inventors: William R. Bullman, Matthew Henry, Ryan S. Holmqvist, Steven E. Strauss
  • Publication number: 20010049751
    Abstract: A system and a method, capable of executing a process operation by using a plurality of applications, are provided. While a corresponding relationship of data used in these applications is previously defined, a data converting unit converts data about an execution result of an application. An application initiating unit executes another application by using the converted data. The present invention has an object to provide both a system and a method, capable of controlling an execution of an application program, while data can be transferred/received among plural application programs having no specific relationship with each other. Furthermore, the present invention has another object to provide both a workflow system and a workflow method, capable of utilizing application programs which are different from each other every process previously defined in the workflow.
    Type: Application
    Filed: March 20, 2001
    Publication date: December 6, 2001
    Inventors: Atsushi Nakamura, Hitoshi Yui, Jun Yoshida
  • Publication number: 20010049752
    Abstract: A computer network includes a client and a server which are preferably independently operable computers that cooperate to perform different procedures of an application program. The server executes its procedure in response to a remote procedure call transmitted over the computer network from the client. The remote procedure call typically includes one or more data structures or parameters used as arguments for executing the remote procedure. The server receives the remote procedure call at an RPC buffer. In accordance with the present invention, the server interprets the parameters while the remote procedure call resides in the RPC buffer whenever the selected format of the parameters of the remote procedure call matches the data structure format processed by the server.
    Type: Application
    Filed: January 12, 2001
    Publication date: December 6, 2001
    Applicant: Microsoft Corporation
    Inventors: David E. Kays, Jr., Vibhas D. Chandorkar
  • Publication number: 20010049753
    Abstract: A first data processor (GPP) can manage resources of a second data processor (DSP) by making a remote procedure call (RPC) to the second data processor to invoke on the second data processor a program that supports management of data processing resources of the second data processor. The second data processor executes the program in response to the remote procedure call.
    Type: Application
    Filed: March 30, 2001
    Publication date: December 6, 2001
    Inventor: Scott Paul Gary
  • Publication number: 20010049754
    Abstract: A stepping motor, head, or other drive mechanism is driven with high precision without using a high speed CPU or dedicated hardware. Timing data controlling the timing at which drive mechanism operation changes, and plural control data controlling drive mechanism operation at each timing change, are stored to memory. After a drive command from the CPU is received, timing data is read from memory by a direct memory access (DMA), and sent to a timer. Based on a time-up signal from the timer, the drive control data is read sequentially from memory by DMA for each of plural control data types and sent to a drive control unit. Afterward, the next timing data is sent to the timer and the operation repeated. The drive control unit drives the drive mechanism based on the control data.
    Type: Application
    Filed: April 12, 2001
    Publication date: December 6, 2001
    Inventor: Yuji Kawase
  • Publication number: 20010049755
    Abstract: A method of direct memory access (DMA) includes receiving a first notification at a DMA engine that a first list of descriptors has been prepared, each of the descriptors in the list including an instruction for execution by the DMA engine and a link to a succeeding one of the descriptors, except for a final descriptor in the list, which has a null link. The DMA engine reads and executes the descriptors in the first list. When the DMA engine receives a second notification that a second list of the descriptors has been prepared, it rereads at least a part of the final descriptor in the first list to determine a changed value of the link, indicating a first descriptor in the second list. It then reads and executes the descriptors in the second list responsive to the changed value of the link.
    Type: Application
    Filed: May 31, 2001
    Publication date: December 6, 2001
    Inventors: Michael Kagan, Ariel Shahar, Diego Crupnicoff
  • Publication number: 20010049756
    Abstract: A transport convergence (TC) subsystem for use as a form of logical pipeline processor is disclosed. The TC subsystem includes a number of ASIC computing blocks interconnected through a local bus for transferring data objects used as a form of common data I/O for each ASIC. The data object includes both control and data portions. A TC scheduling circuit coordinates transfer of data objecst to and from a TC data object memory that is local or external. The TC data object memory is shared in common with all the ASIC blocks so that computation results from each ASIC TC signal processing circuit can be passed between other ASICs to form a logical pipeline. The data objects output from the TC subsystem are used by other processing subsystems in an XDSL communications system, including a software based ATM TC subsystem, and a physical medium dependent subsystem. In addition, the architecture of the TC subsystem is configured so that it can be shared by multiple ports in an xDSL system.
    Type: Application
    Filed: March 1, 2001
    Publication date: December 6, 2001
    Inventor: Ming-Kang Liu
  • Publication number: 20010049757
    Abstract: A task scheduler for a TC subsystem is disclosed. The task scheduler is responsible for responding to computation block requests from the TC subsystem, and retrieving/storing data objects for such computation blocks. The task scheduler thus facilitates a type of logical pipeline by exchanging such data objects with a common TC memory used by each computation block. The task scheduler generally includes a queue, a state machine and a bus master for satisfying the data object requests.
    Type: Application
    Filed: March 1, 2001
    Publication date: December 6, 2001
    Inventor: Ming-Kang Liu
  • Publication number: 20010049758
    Abstract: A storage media for automating a control and a computer system including the storage media, which abolishes the restriction between the hardware models and the software processes, and in which a desired software process can be simply utilized in any hardware models, and a computer system including the storage media are provided. In the intelligent disk 1 having the disk 3 for storing information and the electronic circuit portion 2 for processing the information, wherein the disk stores a plurality of information to be used in an external system, and wherein the electronic circuit portion distinguishes the information stored in the disk, which matches with the external system. Also, the disk unit or the electronic circuit further includes an emulator for matching the system program with the external system.
    Type: Application
    Filed: July 25, 2001
    Publication date: December 6, 2001
    Applicant: Kabushiki Kaisha OPTROM
    Inventors: Takashi Shigetomi, Tetsuo Saito, Tsunematsu Komaki
  • Publication number: 20010049759
    Abstract: With respect to design regarding a bus cycle, it has been necessary to consider a data conflict, if an output disable time of a device is long. A bus controlling unit is installed in a processor. In the bus controlling unit, parameters regarding output disable times of external devices such as a first device are utilised. When a device with a long output disable time is read in a bus cycle, an idle state is forcibly inserted before a following bus cycle activation to avoid a data conflict.
    Type: Application
    Filed: September 16, 1997
    Publication date: December 6, 2001
    Inventors: HIROKI MIURA, YASUHITO KOUMURA, KENSHI MATSUMOTO
  • Publication number: 20010049760
    Abstract: The invention relates to a bus controller for a bus (7) which can be used by several masters, characterized in that it comprises at least two modules (7a, 7b) each of which contains an arbiter and an arbiter supervisor, the function of one at least of the arbiter supervisors being to enable the output of the arbiter of the same module as long as it observes that this arbiter is operating correctly and to disable this output when it observes that the arbiter of the same module is not operating correctly.
    Type: Application
    Filed: November 30, 2000
    Publication date: December 6, 2001
    Inventor: Hugo Delchini
  • Publication number: 20010049761
    Abstract: This invention is an intelligent home control bus (IHbus). It comprises at least one input node (sensor, announcer) A and at least a output node (operator, listener) L. A control instructions are input from the input node A, and transferred to the output node L through a control bus, and the output node L outputs a logic operation result based on the instructions. The node A is a control device for transmitting data and has at least one input circuit for inputting a special logical state. The node L is a device for receiving data and performing a operation and has at least one output circuit for outputting a special logical state.
    Type: Application
    Filed: February 27, 2001
    Publication date: December 6, 2001
    Inventor: Geng Huang
  • Publication number: 20010049762
    Abstract: The operation processing apparatus comprises a trap selecting register which stores trap maps for selecting one operating system in which the operation processing apparatus is applied out of a plurality of operating systems, a read/write controller which selects data for selecting the operating system from the trap selecting register, and a trap type encoder which encodes a trap request from an execution unit such as an integer unit, into trap type code, according to the trap maps corresponding to the selection data.
    Type: Application
    Filed: December 6, 2000
    Publication date: December 6, 2001
    Inventor: Akihiko Ohwada
  • Publication number: 20010049763
    Abstract: Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable pipelined array processing containing multiple processing elements and distributed memories and register files. When an interrupt occurs, interface signals are provided to all PEs to support independent interrupt operations in each PE dependent upon the local PE instruction sequence prior to the interrupt. Processing/element exception interrupts are supported and low latency interrupt processing is also provided for embedded systems where real time signal processing is required. Further, a hierarchical interrupt structure is used allowing a generalized debug approach using debut interrupts and a dynamic debut monitor mechanism.
    Type: Application
    Filed: February 23, 2001
    Publication date: December 6, 2001
    Inventors: Edwin Frank Barry, Patrick R. Marchand, Gerald G. Pechanek, Larry D. Larsen
  • Publication number: 20010049764
    Abstract: A system and method for reliably managing a Flash ROM memory resource while preserving the integrity of the data held in the memory in spite of power outages that can occur during memory compressing operations. The memory management system uses three memory status registers to track the status to each page in the memory being managed. Two of the memory status registers non-volatile memory and one is always determined to be the active memory status register. The third memory status register is located in RAM and used as a scratchpad. If the memory management routine determines the memory needs to be cleaned or compressed (202), the RAM memory status register is initialized (204) and a swap segment is cleared. Valid pages are copied into the swap segment, filling the space taken up by the invalid pages (210).
    Type: Application
    Filed: December 21, 2000
    Publication date: December 6, 2001
    Inventors: Xiaodan Hu Lu, Raymond J. Bonneau, John P. Powers
  • Publication number: 20010049765
    Abstract: The rewriting system for rewriting data stored in a memory of a vehicle controller with new data is provided. The rewriting device is capable of communicating with the vehicle controller. The rewriting device enters a waiting state in which there is no exchange of message between the vehicle controller and the rewriting device. The rewriting device is in a waiting state until a predetermined waiting time has elapsed from the time at which a signal for requesting the vehicle controller to delete the data or write the new data is sent, or from the time at which a signal indicative of start of deleting operation of the data or writing operation of the new data is received. Thus, an erroneous determination of offline due to a busy state of the vehicle controller caused by deleting or writing operation is avoided.
    Type: Application
    Filed: April 13, 2001
    Publication date: December 6, 2001
    Applicant: Honda Giken Kogyo Kabushiki Kaisha
    Inventors: Masanori Matsuura, Naohiko Mizuo, Tetsuya Yashiki
  • Publication number: 20010049766
    Abstract: A memory device having multiple interfaces is described. The memory device may be configured to operate with different interfaces using configuration circuitry in the device that enables switching between the multiple interfaces.
    Type: Application
    Filed: August 10, 2001
    Publication date: December 6, 2001
    Inventor: William R. Stafford
  • Publication number: 20010049767
    Abstract: The present invention relates to a method of efficiently managing a memory cell array. A new memory cell array management method of the present invention allows reduction of power consumption and improvement of performance of a memory system. In a method of efficiently managing a memory cell array according to the present invention, only some sub-word lines after activation of a main word line are activated, and then a window including a memory cell array connected with the activated sub-word lines is activated and managed. Then, a memory address region included in the window is mapped.
    Type: Application
    Filed: January 22, 2001
    Publication date: December 6, 2001
    Inventors: Yong Ha Park, Hoi Jun Yoo
  • Publication number: 20010049768
    Abstract: An input/output control device uses all of its cache memory effectively and allows cache memory modules to be added in increments of one. When cache memory included in the input/output control device is operating normally and the input/output control device receives a write request from a processing device, the input/output control device returns a write request completed response after writing data to cache memory as set forth in configuration information included in the input/output control device. The write data in the cache memory is then written to one or more disk devices asynchronously with the write completed response. When there is a problem with a cache memory module, the write data that was to be written to the region controlled by the cache memory module where the problem occurred is divided among the remaining cache memory modules.
    Type: Application
    Filed: February 9, 2001
    Publication date: December 6, 2001
    Inventors: Tadaomi Kato, Hideaki Omura, Hiromi Kubota
  • Publication number: 20010049769
    Abstract: A cache memory control device enables an external instruction ROM to be co-owned by plural processors while minimizing the lowering of the processing performance of the processor and curtailing the number of external terminals of the LSIs. In a multi-processor system having a processor, an instruction RAM bank and an instruction RAM controller for each physical layer PHY, there is provided one instruction ROM for storing instruction data. The RAM controller of each PHY outputs time allowance information to a pre-fetch request of the instruction data. If there are simultaneously output pre-fetch requests from plural PHYs, the pre-fetch controller selects a pre-fetch request having the smallest time allowance.
    Type: Application
    Filed: May 25, 2001
    Publication date: December 6, 2001
    Applicant: NEC CORPORATION
    Inventor: Mitsuhiro Ono
  • Publication number: 20010049770
    Abstract: A system includes multiple program execution entities (e.g., tasks, processes, threads, and the like) and a cache memory having multiple sections. An identifier is assigned to each execution entity. An instruction of one of the execution entities is retrieved and an associated identifier is decoded. Information associated with the instruction is stored in one of the cache sections based on the identifier.
    Type: Application
    Filed: December 8, 1998
    Publication date: December 6, 2001
    Inventors: ZHONG-NING CAI, TOSAKU NAKANISHI
  • Publication number: 20010049771
    Abstract: A dynamically configurable replacement technique in a unified or shared cache reduces domination by a particular functional unit or an application such as unified instruction/data caching by limiting the eviction ability to selected cache regions based on over utilization of the cache by a particular functional unit or application. A specific application includes a highly integrated multimedia processor employing a tightly coupled shared cache between central processing and graphics units wherein the eviction ability of the graphics unit is limited to selected cache regions when the graphics unit over utilizes the cache. Dynamic configurability can take the form of a programmable register that enables either one of a plurality of replacement modes based on captured statistics such as measurement of cache misses by a particular functional unit or application.
    Type: Application
    Filed: October 9, 1998
    Publication date: December 6, 2001
    Inventors: BRETT A. TISCHLER, RAJEEV JAYAVANT
  • Publication number: 20010049772
    Abstract: A digital data processing system is provided which includes a digital data processor, a cache memory having a tag RAM and a data RAM, and a controller for controlling accesses to the cache memory. The controller stores state information on access type, operation mode and cache hit/miss associated with the most recent access to the tag RAM, and controls a current access to the tag RAM just after the preceding access based on the state information and a portion of a set field of a main memory address for the second access. The controller determines whether the current access is applied to the same cache line that was accessed in the first access based on the state information and a portion of a set field of the main memory address for the second access, and allows the current access to be skipped when the current access is applied to the same cache line that was accessed in the preceding access.
    Type: Application
    Filed: December 20, 2000
    Publication date: December 6, 2001
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hoon Choi, Myung-Kyoon Yim
  • Publication number: 20010049773
    Abstract: A network includes one or more server(s), switching fabric(s), and storage devices and provides for using a plurality of cache devices connected to the switching fabric. Data cached in the cache devices is available to the server(s). The cache devices may be interconnected by a cache fabric, and at least one of the cache devices may be simultaneously connected to the switching fabric. Further, the cache fabric and the switching fabric may operate by sharing common control and management. In some cases, the cache fabric and that switching fabric are merged into a single fabric.
    Type: Application
    Filed: June 6, 2001
    Publication date: December 6, 2001
    Inventor: Shyamkant R. Bhavsar
  • Publication number: 20010049774
    Abstract: This invention describes structure and method for an efficient architecture allowing n-controllers to work together to improve system performance and fault tolerance, when n is greater than two. This invention provides a new type of RAID architecture using operational primitives in a message passing multi-controller environment to solve the problems presented in having multiple controllers distribute a non-uniform workload. This architecture allows for expansion of the I/O processing capability limited only by the efficiency of the underlying message transport method. In simple terms, the inventive technique breaks input/output (I/O) operations into a set of simple methods which can then be passed around as tokens, or pieces of work to be executed by whichever controller has the least amount of work to perform. (I/O operations include all operations needed to perform the tasks of a RAID controller. These include host read/write commands, rebuilds, data migration, etc.
    Type: Application
    Filed: June 4, 1999
    Publication date: December 6, 2001
    Inventors: NOEL S. OTTERNESS, JOSEPH G. SKAZINSKI
  • Publication number: 20010049775
    Abstract: A data carrier (2) includes memory means (16) adapted to store the information data (ID), and further includes first detection means (28) adapted to detect first command data (CD1), and further includes initialization means (33) adapted to initialize, after detection of the first command data (CD1), the memory means (16) for the storage of information data (ID), and further includes second detection means (29)adapted to detect second command data (CD2), and further includes write means (32) adapted to write the information data (ID) into the initialized memory means (16) after detection of the second command data (CD2).
    Type: Application
    Filed: March 19, 2001
    Publication date: December 6, 2001
    Inventors: Robert Rechberger, Stefan Posch
  • Publication number: 20010049776
    Abstract: A copy processing section aggregately copies differential data stored in a plurality of areas discretely existing on a copy source logical disk to a continuous area on a copy destination logical disk, and when a request to access to the copy source logical disk or copy destination logical disk is generated during the aggregation copying process, the aggregation copying process is stopped so that an accessing process is executed by an access processing section.
    Type: Application
    Filed: February 13, 2001
    Publication date: December 6, 2001
    Applicant: FUJITSU LIMITED
    Inventor: Naoaki Maeda
  • Publication number: 20010049777
    Abstract: A memory control device capable of controlling data writing into a buffer memory where the data reproduced from a disk recording medium are stored temporarily is disclosed. The control device comprises a signal generation circuit for generating a stable sync detection signal which is obtained at a normal detection timing of a synchronizing signal in response to a sync detection signal generated by detection of the synchronizing signal inserted in the reproduced data per predetermined data unit. The control device further comprises a data writing controller capable of reading out time base information inserted per predetermined data unit in synchronism with the timing of generation of the stable sync detection signal, and also capable of controlling the data writing into the buffer memory on the basis of the time base information thus read.
    Type: Application
    Filed: June 5, 2001
    Publication date: December 6, 2001
    Applicant: Sony Corporation.
    Inventors: Masaya Tomioka, Toshiyuki Ujisawa
  • Publication number: 20010049778
    Abstract: Storing of data items in a memory (31) is provided wherein the data items are divided into successive data pieces of decreasing significance, and the data pieces are stored in respective parts of the memory (31), and when applying a data piece to the memory (31) in case all candidate memory parts are assigned to other data pieces: if the significance of the applied data piece is lower than a lowest significance of the other data pieces, discarding the applied data piece; if the significance of the applied data piece is higher than the lowest significance, storing the applied data piece in one of the candidate memory parts at expense of a given other data piece which has a lower significance than the significance of the applied data piece. Advantageous use of the invention is made in applications using a device of fixed storage capacity for storing compressible data, such as video, images, audio, speech.
    Type: Application
    Filed: March 12, 2001
    Publication date: December 6, 2001
    Inventors: Renatus Josephus Van Der Vleuten, Richard Petrus Kleihorst
  • Publication number: 20010049779
    Abstract: An assigning system and an assigning method are provided for assigning a storage device or a unitary logical unit of the storage device. A VLU-LU correspondence table is provided which shows a correspondence between virtual logical units (VLU) virtually set in a host computer and logical units (LU) of a plurality of storage devices connected to a network. This table stores evaluation items of each storage device such as a delay time and an access frequency. An evaluation unit calculates an evaluation value of each evaluation item in the table, and a unitary logical unit of the storage is assigned in accordance with the evaluation value.
    Type: Application
    Filed: March 20, 2001
    Publication date: December 6, 2001
    Inventors: Naoki Shimada, Motoaki Hirabayashi