Abstract: A method and apparatus for performing a move mask operation. The present invention provides a method and apparatus for performing operations on packed data values of a first size and format and conversion of the results to data of a second size and format by eliminating redundant data. The present invention is useful, for example, when comparisons are performed on floating point data that is typically larger (e.g., 64 bits) than integer data (e.g., 32 bits) and integer operations are preformed based on the result. Because many processors branch based on integer data, the comparison results stored as floating point data must be transferred to an integer register prior to branching. The present invention takes advantage of redundancy of the floating point comparison results to transfer enough data to convey the comparison result to integer registers with a single instruction.

Abstract: A computer which performs parallel processing of a plurality of programs in a time-division fashion includes hardware resources divided into a plurality of areas, an evacuation unit which records identification information identifying a first program, and evacuates information stored in an area of said plurality of areas if the area is necessary for execution of a second program and is being used for execution of the first program, and a restoration unit which restores the evacuated information to the area based on the identification information when the second program comes to a halt or to an end.

Abstract: The inventive mechanism provides fast profiling and effective trace selection. The inventive mechanism partitions the work between hardware and software. The hardware automatically detects which code is executed very frequently, e.g. which code is hot code. The hardware also maintains the branch history information. When the hardware determines that a section or block of code is hot code, the hardware sends a signal to the software. The software then forms the trace from the hot code, and uses the branch history information in making branch predictions.

Abstract: A method and an installation for preventing premature termination of BIOS refresh operation due to accidental pressing of the reset button. A chipset issues a restrain signal to a logic device when the BIOS is carrying out data refresh so as to restrain any reset command issued from a reset device. At the end of the refresh operation, the chipset issues a non-restrain signal to the logic device granting any request for system reset when the reset device is pressed. With such arrangement, trouble with re-starting a computer after the interruption of a BIOS refresh operation by an unwanted system reset can be avoided.

Abstract: In a system for making a print of a digital image including a computer for storing a digital image data and a printing device for making the print of the digital image data, a method comprises a step of transmitting from the computer to the printing device the digital image data along with information indicative of a location of the digital image data in the computer, a step of making at the printing device the print based on the transmitted digital image data, and a step of adding at the printing device the transmitted information to the print.

Abstract: A method and system for authenticating the identity of a user by an authority makes use of presenting biometric data for the user in a predetermined shared secret sequence. The method and system can be augmented by requesting an additional shared secret, such as a PIN or additional credentials, to establish multiple layers of authentication. Varying the layers of authentication results in greater or lesser security, and the accuracy for any given layer can be relaxed without compromising the integrity of the entire method.

Abstract: A distributed storage system for storing at least one credential (46), provided by an issuing authority and relating to an identity (42, 44), is described. The system comprises: a plurality of unique identities (42, 44) each having a local store (40). Each local store (40) securely stores credentials (46) relating to the owner of the identity (42, 44). The system also comprises one or more security certificates (66) provided at each identity (42, 44) for ensuring the authenticity of the credentials (46). The security certificates (66) provide secure references to the issuers of the credentials (46) and this can be used in verifying the origin of each credential (46). The identity can be provided a website or a mobile phone for example.

Abstract: A system of distributed group management for generating authentication information relating to a group to which users belong at a high speed on a client side and, at the same time, wherein a server side can verify this at a high speed. This system provides a group certificate issuing apparatus for issuing a group certificate on a client side based on original group information including the name of the group to which the users belong and a group certificate verification unit for verifying a legitimacy of the certificate transmitted from the client side in a server.

Abstract: A signal is encoded, for example, perceptually and, during or after the perceptual coding process, a digital watermark is inserted into a quantized digital information signal resulting from the perceptual coding process in such a manner that its insertion is imperceptible to one later listening to, displaying or otherwise utilizing the information signal. Moreover, the digital watermark may be inserted in accordance with a key indicative of the location of the mark in the digitally encoded signal. The key may be protected with a trusted entity and distributed in such a manner as to be not detectable by a pirate. Consequently, the key may be utilized at watermarking apparatus that can be located anywhere in the distribution channel of a copyright protected work. The key may be embedded in a secure microprocessor of validating apparatus at a point of distribution or even at a point of sale.

Abstract: A method is provided for a secure transfer of data or data files between participants, subscribers, and users. A first graphic image of the first original form is generated from the first original form of the data file or of the data by a first transformation process. A second electronic seal is generated from the first graphic image in a second step. In the following, the first original form of the data file or of the data and the second electronic seal of the graphic image are transmitted to a receiver. In a further step, the receiver generates a second graphic image of the original form, received at the receiver, with the same transformation process. The receiver generates a fourth electronic seal from the second graphic image, generated by the second transformation process. The transmitted second seal and the newly generated fourth seal are compared to each other with respect to identity in a last step.

Abstract: The invention is a system and method of controlling an access of a subscriber to a network. The method includes sending an identification of the subscriber and a level of access to be provided to the subscriber from a visited network of a plurality of networks (12, 14, 16) connected to a home network (10); in response to the identification of the subscriber and a level of access to be provided to the subscriber, storing a subscriber profile of the authorized of access to be provided to the subscriber; and controlling access of the subscriber to any network dependent upon a comparison of access to be provided to the subscriber and the stored subscriber profile.

Abstract: The process for securing a communication between a recognition device and an identification unit able to communicate with the recognition device by a data exchange determined by a recognition protocol, one of these items of data corresponding to a reference event, the process communicating in such a way that the recognition device can authenticate the identification unit so as to instruct the unlocking of openable panels of a vehicle and/or permit the starting of a vehicle and furthermore comprising:

Abstract: Digital sound data is encrypted and recorded in a recording medium 200. Information 212 required for decoding the encrypted digital sound data 220 is recorded in a program 211 for controlling the reproduction of sound data separately from the digital sound data 220. This can prevent PCM sound data recorded in the recording medium as a part of a content, from being reproduced separately from the content.

Abstract: There are provided a method of efficiently establishing a security policy and an apparatus for supporting preparation of a security policy. According to a method of establishing a security policy in six steps, a simple security policy draft is first prepared. The security policy draft is adjusted so as to match realities of an organization, as required, thus completing a security policy stepwise. Therefore, a security policy can be established in consideration of a schedule or budget of the organization.

Abstract: A software write protection method for protecting the values in the registers of a programmable chip of a computer system. After setting the registers of the programmable chip, the computer system works according to the set function. Any tampering with data inside the register of the programmable chip is not allowed. When virus programs attempt to write erroneous data into the programmable chip, virus commands are changed by the interrupt service program. Hence, unnecessary changes to the values within the register of the programmable chip are prevented leading to a greater stability for the computer system.

Abstract: A method for processing Executable Objects, comprising: (a) providing analysis means capable of non-interfering analysis of data packets transmitted on a communication line between a browser and an HTTP server on the web, said communication line being established through a gateway; (b) analyzing the handshake between said browser and said server, to detect a “GET_” command sent by the user and an HTTP code sent in response by said server; (c) when such an HTTP code is detected, analyzing the data packets transmitted by said server to said browser, by: (c.1) providing ordering means to order data packets received in non-sequential order, and to forward them in sequential order to header checking means; (c.2) checking the data packets so as to analyze the contents of the header of the Executable Object, and to identify the resources of the system that it needs to employ; (c.3) transmitting to said gateway data representing the resources of the system that the Executable Object needs to utilize; (c.

Abstract: A non-programmatic method for bootstrapping a user database from the web tier using pass-through server-provided form targets is disclosed. A “form target,” used in this context, is the submission destination of an HTML form, submitted via HTTP (typically this is called an “action” in HTTP). The “form target” is usually the name of a CGI script, or an alias to an ASP, Servlet or JSP on the server, which will handle a form request. When the user submits a form via HTTP, the application server will extract security data and then pass control back to an application success target or a failure target.

Abstract: A circuit for adjusting a time when data is delivered to a data terminal with respect to an external clock signal includes a data passing circuit and a delay adjusting circuit. The delay adjusting circuit accepts a plurality of control signals each arranged to control passgates arranged in columns, with one column being controlled by a respective one of the control signals. A clock signal passes in parallel manner through a variety of delay gates, and each delay gate is coupled in series with one of the passgates. By selecting a path through desired passgates, one delay path is selected and the delay time added to the clock signal. This delayed clock signal is used to control the data passing circuit, which controls when data is output to the output terminals relative to the original clock signal. The control signals are created by selectively coupling or decoupling the control signals from a static voltage, and fuses or antifuses can be used to facilitate this coupling or decoupling.

Abstract: An uncorrectable error is detected in the data of a computer system. The erroneous data is allowed to be stored in first and second caches of the computer system while the system runs first and second processes, the first process being associated with the data. The first process is terminated when an attempt is made to load the data from the cache. Meanwhile, the second process continues to run.

Abstract: A disk array device maintains data reliability with few performance degradation problems. In a RAID 4 or RAID 5 disk array device, redundant data created during disk degeneration with a device control module is transferred to a memory of a subsystem control module. The memory is backed up with a battery. The redundant data is held in memory until a writing operation to disk drives is completed. Then, when recovering after a momentary power supply interruption, the write data and parity data stored in the memory are written out without writing data from the disk drive. When recovering after a momentary power supply interruption and the disks are normal, the redundant same-group data is read from disk drives other than those on which the data that is to be written and the parity are stored and based on those and the write data, new redundant data is created and written to the object disk.

Abstract: RAID information and physical position information of hard disk units are managed by a disk controller in a mapped fashion. When the physical position of the hard disk units is changed, the information mapping is retried. Further, the positional information of the hard disk units accommodated in a disk array system under the administration of the disk controller, is calculated so as to form n-dimensional coordinate system information, and the resulting information is stored in each of the hard disk units. When the hard disk units are inserted into the disk array system, the n-dimensional coordinate system information is read from each hard disk unit. If it is detected that there is difference from the current coordinate system information, then information before removal and that after the insertion are compared with each other and a data link is reconstructed.

Abstract: A dual-ported operator control panel (OCP) arrangement provides redundancy and fault tolerance capabilities in a distributed computer system. The arrangement supports the use of multiple OCPs in the computer system, which is preferably a symmetric multiprocessor (SMP) system having a management subsystem. A system control manager (SCM) microcontroller functions as a “master” of the management subsystem. One OCP functions as a primary OCP of the computer system and the others function as standby (or slave) OCPs. Two independent remote SCMs may be coupled to ports of the OCP to maintain communication between the OCP and an SCM in the event of an SCM failure. The OCP performs port arbitration to automatically select an SCM as the OCP “master” via election rules and, thereafter, only allows the elected master port control over light emitting diodes (LEDs) and a display of the OCP.

Abstract: A fault analyzing system presumes fault propagation paths for specifying nodes related to fault terminals once on plural time planes, and merges pieces of related fault terminal information representative of the fault terminals related to the nodes on different time planes in different manners so that plural list of plural kinds of fault are drawn up without repeating the time-consuming presumption.

Abstract: A microprocessor includes: a memory storing a program and various data; a processor core executing the program stored in the memory; an external bus interface serving as an interface portion of an external bus connected to an external device; a test circuit receiving a program counter value of an instruction to be executed by the processor core for outputting a test event signal for testing the microprocessor in synchronization with an operation timing of the processor core; a test event signal output terminal for outputting the test event signal to an external portion of the microprocessor, and an external event request signal input terminal provided for applying the processor core an external event request signal used by the external device to notify an event request with respect to the processor core.

Abstract: In an apparatus that performs a plurality of signal processings including the recording/reproduction operation, wire-communication operation, and radio-communication operation, part of each processing circuit or part of the function of each processing circuit is commonly used between different operations. An error-correction coding circuit, in part or entirely, is used commonly between a plurality of different signal processings so that the error-correction capability in error-correction coding or error-detection capability in error-detection coding is set to be different to the information data processed in the signal processings. With this arrangement, the apparatus is compact, low-cost, and of a simple construction, and the error-correction coding is properly performed in accordance with the quantity and nature of errors taking place in each signal processing.

Abstract: An apparatus, system, and method for testing packet-based semiconductor devices by using simplified test data packets. Simplified test data packets are generated by conventional memory testers in one format. The simplified test data packets are realigned to another, different format by test mode circuitry located on an integrated circuit chip, test interface, or tester prior to testing the memory device. The test method potentially reduces the number of pieces of data which must be generated using an algorithmic pattern generator on a per-pin basis. Furthermore, the test method potentially reduces the number of packet words that has a combination of data generated from an APG and vector memory. Packet-based semiconductor devices are also disclosed.

Abstract: The invention relates to an integrated circuit with at least an analog and a digital circuit that are interconnected by a signal path. In order to enable separate testing of the circuits, for example in accordance with the macro test approach, in the signal path a special seam circuit (200) is inserted. The seam circuit (200) is essentially a feedback loop (214) having a scannable flip-flop (210) and a multiplexer (220). The flip-flop (210) feeds a first input of the multiplexer (220), whereas a second input of the multiplexer (220) establishes an input (230) of the seam circuit (200). An output of the feedback loop (214) establishes an output of the seam circuit (200).

Abstract: A memory address generating apparatus and method of a dynamic memory testing circuit for generating addresses for testing a dynamic memory which uses all the available addresses of the dynamic memory, which does not use the most significant addresses, and which does not use middle addresses among all the available addresses are provided. The address generator can obtain an up-counted address by up counting the addresses used by the dynamic memory. It can obtain a down-counted address by inverting the N-bit up-counted value, or by subtracting the N-bit up-counted value from the maximum address, or by combining the inverted MSB portion of the N-bit up-counted value with the LSB portion of the N-bit up-counted value subtracted from the LSB portion of the maximum address used in the dynamic memory. The down and up counted addresses are used as addresses for selectively testing the dynamic memory according to a selected testing method.

Abstract: A checksum engine for use with a fast pattern processor and a method of operation thereof. In one embodiment, the checksum engine includes (1) a processing engine that performs partial checksums on at least a portion of each processing block associated with different protocol data units (PDUs), and (2) a controller that coordinates an operation of the processing engine to allow the processing engine to provide a complete checksum from the partial checksums of the processing blocks associated with each of the PDUs.

Abstract: Three dual-port RAMs of the number of bits=8 and the number of words=4 are provided in a path memory circuit. Path selection information is sequentially written into the three RAMs every clock in accordance with the control of a control circuit. On the other hand, the path selection information is read out every clock from the RAMs in accordance with the control of the control circuit and is inputted as read path selection information or the like to a tracing circuit. The tracing circuit executes the tracing operation as many as three times on the basis of the read path selection information and trace starting state information which is formed by the control circuit. On the basis of a tracing result, the decoding data and a trace starting state in the subsequent clock are obtained.

Abstract: For use in designing a logic circuit of a semiconductor device, a library (10) memorizes not only a delay value (TYP, MIN, or MAX) for each of signal paths of a circuit element of the logic circuit but also a standard deviation (&sgr;CHIP or &sgr;TR) of a variation of the delay value for each of the signal paths of the circuit element. Instead of the standard deviation, the library may memorize a variance of the variation. The variance is given by (&sgr;CHIP)2or (&sgr;TR)2 when the variation is a normal distribution.

Abstract: A pattern distortion correction device which performs distortion correction of a layout pattern is provided, considering not only an edge shift value but also a process margin. The pattern distortion correction device comprises a finished pattern anticipation section anticipating a finished pattern of a layout pattern, an edge shift value measure section measuring an edge shift value which is a gap between an anticipated finished pattern and a standard pattern, a process margin measure section measuring a process margin of the anticipated finished pattern, a measure result determination section determining whether or not a measured edge shift value and a measured process margin satisfy a determination standard, and a layout pattern temporary correction section correcting the layout pattern so as to satisfy the determination standard based on a determination result by the measure result determination section.

Abstract: Various systems and methods providing signal delay compensation for circuits such as a multi-pair gigabit Ethernet transceiver are disclosed. In an analog implementation a buffer with an adjustable delay may be used to minimize the delay mismatch between clock trees. The delay of the adjustable-delay buffer is controlled by bias voltages that determine the charging and discharging current to the adjustable buffer. A phase detector circuit is used to compare the clock phases for rising and falling edges, and to adjust the bias voltages that control these edges. In a digital implementation a selector switch, responsive to a phase detector, may be used to route clock signals through circuit elements to delay clock signals.

Abstract: An integrated circuit (IC) die includes a semiconductor layer, electronic components formed on the semiconductor layer, and a primary metal layer upon which is formed a primary power distribution network for distributing power to the electronic components. The IC die also includes a horizontal metal layer, a vertical metal layer, and a power mesh electrically connected to the primary power distribution network, the power mesh including horizontal power trunks formed on the horizontal metal layer and vertical power trunks formed on the vertical metal layer. Also provided is an integrated circuit (IC) die which includes a semiconductor layer, electronic components formed on the semiconductor layer. A fine power distribution network, formed on a first metal layer, distributes power to the electronic components.

Abstract: The problem of the disclosed technique is to realize an automatic logic design supporting method and apparatus capable of laying out a circuit of logic synthesis result so as to be able to satisfy delay constraints without changing the logic structure.

Abstract: Method and apparatus for suppressing change in wiring delay time resulting from cell interchange and thereby satisfying required specifications in a short period of time with certainty during LSI layout designing. Cells are arranged in parallel to each other and routed based on circuit designing information, thereby designing a block layout including a plurality of cell rows. A cell not satisfying the required specifications is extracted from the block layout, and a level of drivability required for the cell to satisfy the required specifications is calculated. The extracted cell in question is interchanged with a substitute cell. The substitute cell has equivalent logic, a required level of drivability and the same width and terminal position in the cell arrangement direction on a cell row as the counterparts of the cell in question and is provided in a stretchable cell library.

Abstract: A novel architecture for a multi-scale programmable logic array (MSA) to be used in the design of complex digital systems allows digital logic to be programmed using both small-scale blocks (also called gate level blocks) as well as medium scale blocks (also called Register Transfer Level or RTL blocks). The MSA concept is based on a bit sliceable Arithmetic Logic Unit (ALU). Each bit-slice may be programmed to perform a basic Boolean logic operation or may be programmed to contribute to higher-level functions that are further programmed by an ALU controller circuit. The ALU controller level in this new approach also allows the primitive logic operations computed at the bit-slice level to be combined to perform complex random logic operations. The data shifting capability of this new programmable logic architecture reduces the complexity of the programmable routing needed to implement shift operations including multiplier arrays.

Abstract: Supposing an information processing system having a server which receives a request of service via a transmission line or a network and provides the service, the server receives from a client address information such as an instruction address in an address space of the client to thereby provide the client with service corresponding to the address information, instead of calling a program of the server from the client. By adopting this protocol, the communication processing between the server and the client is simple. Furthermore, the cost reduction of the data processing system for providing a client or an information terminal apparatus with service via the network or the like can also be implemented.

Abstract: A method for operating a code cache in a dynamic instruction translator, comprising the steps of: storing a plurality of translations in a cold partition in a cache memory; maintaining a different associated counter for each of a plurality of translations in the cold partition of the cache memory; incrementing or decrementing the count in the associated counter each time its associated translation is executed; and moving the translation to a hot partition in the cache memory if the count in the associated counter reaches a first threshold value.

Abstract: The present invention is related to a communication system in which a transmitter (2) transmits cyclically a plurality of mutually related objects (20,22,24,26) to a terminal (10). If said objects are used in the terminal there is no mechanism to establish whether said objects are consistent, e.g. that they are originated at the same time. To ensure that the objects are consistent, they are combined in a common transport entity. The receiver is arranged to extract only the complete set of mutually related objects from the common transport entity. Consequently, the consistency is always ensured.

Abstract: A method for enhancing digital video recorder television advertising viewership provides a method wherein the first or last number of seconds of a commercial break are carefully authored to provide a “teaser” to entice the viewer to watch multiple commercials during the commercial break instead of skipping the commercial break using the fast forward or jump functions of the DVR. A bookending function displays an advertisement before and/or after a program that has been recorded on the DVR's storage device is played to the viewer. The viewer selects a recorded program from the DVR's storage device to playback. Before the program is played back, an advertisement is retrieved from the storage device and is displayed before the program is run. Another advertisement is retrieved and then played after the program is over.

Abstract: Content broadcast system enabling broadcast content and advertising data to be solicited at low cost, and enabling providers readily to offer content they create. The content broadcast system is configured with a central processing device (10) and a plurality of terminal devices connected via a network (2) for broadcasting content from the central processing device (10) to the terminal devices.

Abstract: A broadcasting system 1 provides a digital content to be broadcast with an attribute vector A thereof. A filter 12 is assigned with a selection vector S indicating user's taste. The filter 12 performs a standardized inner product operation between the selection vector S and the attribute vector A for selecting and recording broadcast programs.

Abstract: A television system is provided which includes at least a display screen (2). The television system receives video, audio and/or auxiliary data via a broadcast data receiver from a broadcaster at a remote location, and the data is used to generate an EPG for display on the display screen (2). The EPG comprises a series of selectable screen displays selected to be displayed on the display screen (2). The format of one or more of the EPG screen displays can be generated in one of a number of selectable formats and can be selected using control means.

Abstract: An Internet business model for conducting distribution of audio and multimedia programs, including the buying and selling of the advertisment space in the programs, integrating the selected ads into the programs, and distributing them to the listeners/viewers, using the internet. The Method includes techniques for accounting for royalties and fees associated with the distribution of the programming content as well as a open market for ad slot pricing based on consumer demand.

Abstract: A network device is connectable to a network for use in directing data. The receiving process is executed by receiving data having a physical address indicating a destination of the data, comparing the physical address of the received data with registered physical addresses, completing the receiving process when the physical address of the received data matches with one of the registered physical addresses, and otherwise canceling the receiving process. The transmitting process is executed by detecting a destination of data to be transmitted, selecting one of the registered physical addresses according to the detected destination of the data to be transmitted, and attaching the selected physical address to the data, thereby indicating an origin of the data.

Abstract: A method for selecting a channel of interest from a plurality of communication channels which carry audio or video information, by: extracting image or sound characteristic data from said audio or video information, searching for specific content of interest based on said image or sound characteristic data and selecting a channel based on said content of interest is described. Image and sound characteristic data are stored on a content-based channel search server, which includes video search engines capable of matching attributes related to user interest profiles with data corresponding to current content of multiple channels. User interact with the server via client terminals, which communicate with the server using the Internet protocol. Client terminal receive search results corresponding to matches between channel content and user profile. The client terminal controls a variety of viewing, recording and logging devices.

Abstract: Methods for providing a pathogen-free pig or pig fetus as a donor of tissue, cells and/or organs to a recipient human. Animals are free of zoonotic pathogens. When fetal tissues are used for transplantation, donor animals are free from zoonotic pathogens, pathogens able to cross the placental barrier, and tissue-specific pathogens, e.g., neurotropic pathogens. Tissues, cells and organs from pigs free of the above-listed pathogens are suitable for transplantation into humans, include fetal neuronal cells for treatment of Parkinson's disease and islet cells for treatment of islet insufficiency-related diseases.

Abstract: A method and system for controlling the expression of transgene products in specific tissues in a transgenic animal is provided. The method comprises: a) providing a fist transgenic parent animal whose genome comprises an F transgene comprising an exogenous gene operatively linked to a promoter that is upregulated by a transactivator protein; b) providing a second transgenic parent animal whose genome comprises i) a second transgene, comprising a second promoter that is downregulated by the transactivator protein and operatively linked to an antisense gene that encodes a sequence which inhibits or reduces processing of the F transgene transcript; and ii) a third transgene comprising a tissue specific promoter operatively linked to a gene encoding the transactivator protein; and c) breeding the first transgenic parent animal with the second transgenic parent animal to provide a transgenic offspring animal whose genome comprises the three transgenes.

Abstract: A method is described of selecting a porcine oocyte or a population of oocytes with improved developmental competence following either in vitro or in vivo maturation.