Abstract: A non-volatile memory includes a floating gate extending in a substrate between source and drain regions. A channel region may be confined by two insulating layers. The invention is particularly applicable to EPROM, EEPROM, Flash and single-electron memories using CMOS technology.

Abstract: MOS transistors are formed on island-shaped divided element regions of a silicon substrate, and provided with gate electrodes having the same widths as the element regions. Thereafter, capacitor grooves are formed at end portions of the element regions, and capacitor insulating films formed of BSTO are provided on inner walls of the capacitor grooves. Then, the capacitor grooves are filled with storage electrodes, thereby forming capacitors. Furthermore, connection conductors are formed to connect the storage electrodes and source diffusion layers of the MOS transistors. Then, word lines are formed to connect the gate electrodes of the MOS transistors, and further bit lines are formed to connect drain diffusion layers of the MOS transistors.

Abstract: A semiconductor device equipped with information storage capacitor comprising a first capacitor electrode, an oxide film, a second capacitor electrode and insulating films containing silicon as a main constituting element, wherein at least one of first and second capacitor electrodes contains as a main constituting element at least one element selected from rhodium, ruthenium, iridium, osmium and platinum, and as an adding element at least one element selected from palladium, nickel, cobalt and titanium, is excellent in adhesiveness between the capacitor electrodes and the insulating films.

Abstract: An attempt is made to achieve an upward leap in the capacitance of a capacitor of MIM structure and further improvements in the reliability of a semiconductor device. A method of manufacturing a semiconductor device has a step of forming an amorphous silicon film on the surface of a lower electrode of a capacitor, a step for roughening the silicon film, to thereby form rough polysilicon, and a step for etching metal film of a lower electrode while the rough polysilicon is taken as a mask, thereby roughening the surface of the lower electrode. Through the foregoing steps, the surface of a lower electrode of a capacitor of MIM (metal/insulator/metal) structure is formed roughly, thereby increasing the surface area of the capacitor. Thus, a large-capacitance capacitor of MIM structure can be fabricated.

Abstract: There is provided a CVD raw material, which can be stably transported (supplied) to a reactor in order to form a platinum metal, Cu or an oxide thereof as an electrode.

Abstract: The method for fabricating the semiconductor device comprises the steps of: forming an insulation film 56 above a substrate 10; forming an opening 60 in the insulation film 56 down to the substrate 10; forming a plate electrode 62 on at least a side wall of the opening 60; removing the insulation film 56 to form an opening 68 having a side wall surrounded by a plate electrode 62; forming a capacitor dielectric film 70 on at least a side wall of the opening 68; and forming a storage electrode 72 on the capacitor dielectric film 70. Whereby electric characteristics between the electrode, etc. in the below structure and the storage electrode are prevented from deterioration in high-temperature thermal processing in the step of forming the capacitor dielectric film.

Abstract: A metal-oxide semiconductor field effect transistor (MOSFET), a method of manufacturing the MOSFET and a power supply incorporating at least one such MOSFET. In one embodiment, the MOSFET includes: (1) a substrate having an epitaxial layer underlying a gate oxide layer, a portion of the epitaxial layer being a gate region of the MOSFET, (2) an N-type drift region located in the epitaxial layer laterally proximate the gate region and (3) source and drain regions located in the epitaxial layer and laterally straddling the gate and drift regions.

Abstract: A lateral semiconductor device includes an alternating conductivity type layer for providing a first semiconductor current path in the ON-state of the device and for being depleted in the OFF-state of the device, that has an improved structure for realizing a high breakdown voltage in the curved sections of the alternating conductivity type layer.

Abstract: A sidewall insulating film is formed on the side faces of a gate electrode on a substrate. A trench isolation film is also formed to be self-aligned with the gate electrode. The upper surface of the trench isolation film reaches a level higher than that of the gate electrode. And source/drain contacts, which make electrical contact with source/drain regions, are formed between the sidewall insulating film and the isolation film. Since the source/drain contacts and the isolation film are both self-aligned with the gate electrode, no mask overlay margin is needed. Thus, the size of the entire active region or the source/drain contacts (or source/drain regions) can be reduced in the gate length direction.

Abstract: A sidewall insulating film is formed on the side faces of a buried gate electrode on a substrate. A trench isolation film, self-aligned with the gate electrode, is also formed so that the upper surface of the isolation film is higher than that of the gate electrode. And source/drain contacts, which make electrical contact with source/drain regions, are formed between the sidewall insulating film and isolation film. Since the source/drain contacts and isolation film are both self-aligned with the gate electrode, no mask overlay margin is needed. Thus, the size of the entire active region and that of the source/drain contacts or source/drain regions can be reduced in the gate length direction.

Abstract: A silicon nitride film is formed between interlayer insulating films covering an upper surface of an element formed on a surface of a semiconductor layer. With this structure, a semiconductor device comprising an isolation insulating film of PTI structure, which suppresses a floating-body effect and improves isolation performance and breakdown voltage, and a method of manufacturing the semiconductor device can be obtained.

Abstract: The purpose of this invention is to ensure an active use of the inverse short-channel effect in the ratio circuit and to guarantee stable operation at low power source voltage. In this ratio circuit, N-channel MOS transistor 12 of CMOS circuit 10 on one side forms the drive element, while P-channel MOS transistor 18 of CMOS circuit 16 on the other side forms the load element. Said N-channel MOS transistor 12 on the drive side and P-channel MOS transistor 16 on the load side have their drain terminals electrically connected to each other through transfer gate 22 made of N-channel MOS transistor. MOS transistor 12 on the drive side has a single channel CHa with the inverse short-channel effect. MOS transistor 18 on the load side has plural, e.g., two, channels CHb1 and CHb2, connected in tandem, each of which displays the inverse short-channel effect.

Abstract: Disclosed is a semiconductor integrated circuit device (e.g., an SRAM) having memory cells each of a flip-flop circuit constituted by a pair of drive MISFETs and a pair of load MISFETs, the MISFETs being cross-connected by a pair of local wiring lines, and having transfer MISFETs, wherein gate electrodes of all of the MISFETs are provided in a first level conductive layer, and the pair of local wiring lines are provided respectively in second and third level conductive layers. The local wiring lines can overlap and have a dielectric therebetween so as to form a capacitance element, to increase alpha particle soft error resistance. Moreover, by providing the pair of local wiring lines respectively in different levels, integration of the device can be increased.

Abstract: A method and system for providing a semiconductor memory device is disclosed. The method and system include providing a plurality of gate stacks above a substrate. Each of the plurality of gate stacks includes a first edge and a second edge and crosses at least one field isolation region. The method and system also include providing a first source implant adjacent to the first edge of each of the plurality of gate stacks and driving the first source implant under the first edge of each of the plurality of gate stacks. The method and system also include providing a self-aligned source (SAS) etch that removes a portion of the at least one field isolation regions separating the plurality of source regions. The SAS etch is provided after the first source implant driving step. The method and system also include providing a first spacer and a second spacer for each of the plurality of gate stacks.

Abstract: In an insulated gate field effect semiconductor device, the gate electrode formed on the gate insulating film includes the first and second semiconductor layers as a double layer. An impurity for providing one conductivity type is not contained in first semiconductor layer which is in contact with a gate insulating film and is contained at a high concentration in the second semiconductor layer which is not in contact with the gate insulating film. Accordingly, by existence of the first semiconductor layer is which the impurity is not doped, the impurity is prevented from penetrating through the gate insulating film from the gate electrode and diffusing into the channel forming region. Also, by existence of the second semiconductor layer in which high concentration impurity is doped, the gate electrode has low resistance.

Abstract: A photoelectric converter of a high signal-to-noise ratio, low cost, high productivity and stable characteristics and a system including the above photoelectric converter. The photoelectric converter includes a photoelectric converting portion in which a first electrode layer, an insulating layer for inhibiting carriers from transferring, a photoelectric converting semiconductor layer of a non-single-crystal type, an injection blocking layer for inhibiting a first type of carriers from being injected into the semiconductor layer and a second electrode layer are laminated in this order on an insulating substrate.

Abstract: A semiconductor light-receiving device includes a plurality of first conductive type second semiconductor layers formed on a first surface of a first conductive type semiconductor substrate apart from each other. Each of the first conductive type second semiconductor layers is surrounded by a second conductive type third semiconductor layer with a first semiconductor layer therebetween. The first semiconductor layer has a lower impurity concentration than the second semiconductor layers. By completely depleting the first semiconductor layer occupying a large area within the light-receiving surface, the light entering the light-receiving surface is enabled to contribute to a photoelectric current while reducing the light absorption in the second semiconductor layers, so that the sensitivity characteristics of the semiconductor light-receiving device can be made superior and the production cost can be lowered.

Abstract: The present invention provide a solar cell and a method of manufacturing the same which is high in the efficiency of energy conversion and improved in the durability while its production process requires not particularly high accuracy.

Abstract: The semiconductor device is provided with an element isolating region disposed in a matrix to define a channel region on a semiconductor substrate, gate interconnection layers extending in a direction and disposed at predetermined intervals from each other above element isolating region, and aluminum interconnection layers extending in a direction intersecting gate interconnection layers and disposed at predetermined intervals from each other, aluminum interconnection layer being disposed above element isolating region. Thus, it becomes possible to provide a semiconductor device and a method of manufacturing thereof which enable the reduction in time required for the final manufacturing steps of the semiconductor device after the ROM specifications are determined.

Abstract: A fuse is programmed by being supplied with a current. The fuse is connected to a thyristor. A control circuit is connected to the gate of the thyristor. The control circuit turns the thyristor ON to allow the fuse to be programmed.

Abstract: An information write-register embedded in an integrated circuit (IC) is made of a plurality of independently addressable gate-controlled components formed in an isolated p-well nested in a n-well. Gates over the p-well are positioned on an insulator geometrically formed so that it is susceptible locally to electrical conductivity upon applying an overstress voltage pulse, whereby binary information can be permanently encoded into the write-register. The overstress voltage pulse is applied between the gate and the p-well and is created when a write-enable pulse of predetermined polarity and duration is superposed by a p-well pulse of opposite polarity and shorter duration.

Abstract: A significant and very effective decoupling capacitor and heat sink combination that, in a single structure provides both a heat sink and a decoupling capacitor in close proximity to the active circuit on the chip requiring either heat sinking or decoupling capacitance or both. This is achieved by forming on a semiconductor chip, having a buried oxide layer therein, an integrated high-performance decoupling capacitor that uses a metallic deposit greater than 30 microns thick formed on the back surface of the chip and electrically connected to the active chip circuit to result in a significant and very effective decoupling capacitor and heat sink in close proximity to the active circuit on the chip requiring such decoupling capacitance and heat sinking capabilities. The decoupling capacitance can use the substrate of the chip itself as one of the capacitive plates and a formed metallic deposit as the second capacitive plate which also serves as a heat sink for the active circuit formed in the chip.

Abstract: An Metal Insulator Metal (MIM) capacitor having improved performance in a high frequency range. The MIM capacitor comprises: a lower electrode; a second insulating film formed on the lower electrode; a capacitor insulating film formed on a portion of the lower electrode; an upper electrode formed on the capacitor insulating film; a third insulating film formed on the second insulating film and the upper electrode; a first lead electrode which connects to a portion of the lower electrode; a second lead electrode which connects to a portion of the upper electrode. The first lead electrode is continuously formed such that the first electrode surrounds at least three sides of the capacitor insulating film, and the width H of the capacitor insulating film and maximum frequency F satisfy the formula: H<(A/F)½, where, A is a predetermined constant determined depending on a structure and manufacturing process of the MIM capacitor to obtain desired admittance characteristics.

Abstract: A method and apparatus is disclosed for providing highly linear resistance with high sheet values, and for implementing resistors in a conventional CMOS process when either drain or source must operate near the rail of a circuit. Accordingly, a five terminal distributed MOS resistor device includes a drain terminal, a source terminal, and a channel region disposed between the drain terminal and the source terminal. A bulk terminal is adjacent the channel region. A first gate terminal is adjacent the source terminal and a second gate terminal is adjacent the drain terminal. Lastly, a gate region of resistive material is disposed between the first gate terminal and the second gate terminal, wherein upon application of a voltage to the first gate terminal and the second gate terminal, a voltage drop across the gate region is equally distributed along a length of an electrical channel in the channel region.

Abstract: A protection circuit in a semiconductor integrated circuit having a master slice I/O circuit comprises an internal circuit, a pad, and a desired number of protection elements connected in parallel between the internal circuit and the pad. Each protection element includes a P-channel MOS transistor which outputs a first power supply voltage level signal on the basis of an output signal of the internal circuit, a N-channel MOS transistor which outputs a second power supply voltage level signal on the basis of the output signal of the internal circuit, a resistor connected between a signal line connected to the pad and an output terminal of the P-channel MOS transistor, and a resistor connected between the signal line and an output terminal of the N-channel MOS transistor.

Abstract: An electronic device, integrated monolithically in a semiconductor substrate and comprising a bipolar transistor connected in series to at least one MOS transistor, the bipolar transistor having a base region that includes a first buried region and a first diffused region extending continuously from the substrate surface down to the buried region, and the diffused region is bordered by an isolation trench region extending in the buried region.

Abstract: A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to be etched is exposed first to plasma under a low power strike and subsequently to a conventional high power strike. CD loss has been found to be reduced by about 400 Angstroms and striations formed in the contact holes are reduced.

Abstract: A second or cap dielectric layer is interposed between the usual or base dielectric layer and the metallic circuitry layer of a semiconductor device. The base dielectric layer has a plurality of recesses in an inactive part of the semiconductor device into which parts of the cap dielectric layer extend to interlock the cap dielectric layer to the base dielectric layer and to oppose shearing or tearing of the either (1) the metallic circuitry layer as the metallic circuitry layer is subjected to chemical-mechanical polishing, or (2) a hard mask layer from the base dielectric layer as the metallic circuitry layer is subjected to chemical-mechanical polishing.

Abstract: An method and apparatus for high voltage control of isolation region transistors (320) in an integrated circuit. Isolation region transistors (320) are formed between active devices by selective implantation of channel stop implants (140). Isolation region transistors (320) are those areas with a conductor (130) over an isolation region (120) with no channel stop implant (140). This provides an isolation region transistor (320) with a lower threshold voltage than the areas with channel stop implant (140). The voltage threshold of the isolation region transistors 320 are adjustable to a range of voltages by varying the length of channel stop implant (140). The apparatus may be fabricated using conventional fabrication processes.

Abstract: In order to program a programmable element, it is proposed in a semiconductor circuit configuration to connect a first and a second connecting terminal of a programmable element to first and/or second potential devices provided in the semiconductor circuit configuration. In this manner, the first and second potentials are intrinsically made available to form a burning voltage for programming the programmable element.

Abstract: A semiconductor device is formed from a die and a lead frame having one or more bus bars. Portions of the bus bars are overlain with an electrically insulative material while leaving bonding areas unobstructed, whereby bond wires which span the bus bar(s) may be bonded with a shorter wire and a lower loop, without the danger of shorting to the bus bar(s). The incidence of harmful wire sweep in the encapsulation step is also reduced.

Abstract: A plane layer and a number of thin filamentary interconnection patterns disposed therearound are disposed on the upper surface of a flexible insulating tape. A semiconductor chip is mounted on the plane layer on the insulating tape by flip-chip bonding, and has terminals on its reverse side which are connected to the plane layer and the interconnection patterns, respectively. Some of the terminals of the semiconductor chip are connected through the plane layer to solder balls, providing ground interconnections. Other terminals are connected to the interconnection patterns to other solder balls, providing power supply interconnections. Still other terminals are connected to other interconnection patterns to still other solder balls, providing signal interconnections. The semiconductor device can simply be fabricated, requires no device hole for semiconductor chip, can be reduced in size, have electric interconnected reduced, and can have electric characteristics stabilized.

Abstract: A semiconductor device includes a substrate, a semiconductor chip mounted on one surface of the substrate, wherein the semiconductor chip has an integrated circuit and bonding pads formed on a main surface thereof. The main surface of the semiconductor chip has a quadrilateral shape with the bonding pads being disposed along four sides of the main surface. A plurality of conductors is disposed on the one surface of the substrate so as to surround the semiconductor chip along four sides thereof and a plurality of bonding wires electrically connect the bonding pads with tips of the conductors, respectively. A resin body seals the semiconductor chip, the conductors and the plurality of bonding wires. A pitch between adjacent bonding pads increases in a direction toward four corners defined by the four sides of the main surface of the semiconductor chip.

Abstract: A type of leadframe having a joined internal lead. A leadframe includes a plurality of adhesion pads and a plurality of leads. The leads are arranged around the adhesion pads. The adhesion pads are formed by joining some extended leads. The adhesion leads replace the conventional die pad to support and attach a chip.

Abstract: An electrode wiring structure is disclosed which realizes a smaller semiconductor apparatus as a power semiconductor module with the current path set as shortest as possible. The semiconductor apparatus includes: a plurality of semiconductor devices mounted in one array or more on a substrate; a main current electrode mounted along the array(s) of the semiconductor devices, and commonly connected to each of the plurality of semiconductor devices through the substrate by being connected to the substrate through a plurality of wires; an insulated base mounted on the main current electrode, and covering the connection area of the wires connecting the main current electrode; and a drive electrode mounted on the base, and commonly connected to each of the semiconductor devices.

Abstract: The present invention provides a semiconductor device which is stably operated even with respect to heat generated upon its operation and makes no use of an environmental harmful substance (lead). The semiconductor device includes a support plate for supporting a semiconductor chip and the semiconductor chip fixed onto the support plate with an adhesive interposed therebetween. The semiconductor chip is fixed to the support plate by a highly thermal conductive adhesive and a high junction strength adhesive provided so as to separate bonding areas from one another. The highly thermal conductive adhesive is provided in plural places within the whole fixing area. The highly thermal conductive adhesive is associated with a heated portion of the semiconductor chip. The high junction strength adhesive is provided so as to surround the highly thermal conductive adhesive. Both the adhesives do not contain lead corresponding to the environmental harmful substance.

Abstract: A semiconductor device including: a semiconductor member having thereon a plurality of interconnect pads: and a mounting member having a plurality of electrode terminals electrically and mechanically connected to the respective interconnect pads for mounting the semiconductor chip on the mounting member, the electrode terminals forming a plurality of I/O cells each having part of the electrode terminals, the part of electrode terminals including signal terminals, the I/O cells forming a first group of the I/O cells and a second group of I/O cells disposed on an inner position of the mounting member with respect to the first group. The higher integration of the semiconductor device having the higher performances can be realized because the interconnect lines can be drawn to the outer periphery of the chip from the interconnect pads corresponding to each of the I/O cells when the chip is miniaturized or the number of the ball electrodes is increased.

Abstract: An electrostatic charge protection structure, in which a conducting layer connecting the non-connected pins is added on the surface of an IC, is provided. The accumulated charges on the non-connected pins can then be attracted to the conducting layer and are discharged via the leakage capacitance between the conducting layer and the IC. Also, the conducting layer can be connected to a ground pin leading the accumulated charges to the ground. Alternatively, the conducting layer can be connected to a voltage source so that the accumulated electrostatic charges can be absorbed by the voltage source. As a result, the electrostatic charge protection structure provided in the present invention can effectively prevent the functional pins from being damaged by the ESD effect from the non-connected pins.

Abstract: A microelectronic component is fabricated by bonding a flexible sheet in tension on a rigid frame so that the sheet spans an aperture in the frame, and performing one or more operations on features on the flexible sheet which will be incorporated into the finished component. The fame maintains dimensional stability of the sheet and aids in regsitration of the sheet with external elements such as processing tools or other parts which are to be assembled with the sheet. Desirably, the frame has a coefficient of thermal expansion different from that of the sheet so that when the sheet is brought from the bonding temperature to the temperature used in processing, differential thermal expansion or contraction will cause increased tension in the sheet.

Abstract: The present invention is provides an LSI package without employing steps for forming solder bumps on a bare chip and soldering to an interposer. In the present invention, a bare chip is mounted on the LSI package by forming wiring patterns which connect to bare chip I/O terminals in a build-up layer of a substrate. Furthermore, the wiring patterns are formed so as to connect outer I/O terminals on the substrate.

Abstract: A test socket for a semiconductor device is provided having a contact member 30, which lies between the external terminals 25, projected from the package 24 of the IC 22 and the contact pads 26 of the test board 23 for making them in conductive with each other. The contact member 30 is made of a metallic contact member 29, which is in contact with the external terminals 25 through blades 32 and a conductive elastic contactor 28. The conductive elastic contactor 28 has an upper contact part 28a and a lower contact part 28b, which are projected from the top and bottom surfaces of the insulating base 27. The lower contact part 28b is in contact with the contact pads 26 of the test board 23.

Abstract: A central portion of a main face of a package substrate 2 is mounted with a memory chip 1 in face down bonding by a flip chip bonding system. Further, a plurality of chip condensers 7 are mounted at vicinities of the memory chip 1. A clearance between a main face (lower face) of the memory chip 1 and a main face of the package substrate 2 is filled with underfill resin (seal resin) 10 constituting a seal member for achieving protection of connecting portions for connecting both and relaxation of thermal stress. An outer edge of the underfill resin 10 is extended to an outer side of the memory chip 1 and covers entire faces of the chip condensers 7 mounted at vicinities of the memory chip 1.

Abstract: A surface mounted power transistor is provided with a heat sink by positioning a mounting plate of a heat sink between the power transistor and a solder pad on the circuit board. The mounting plate of the heat sink is provided with a plurality of openings through which the solder of the solder pad flows during the solder reflow process so that the mounting plate is securely adhered between the power transistor and the circuit board. The mounting plate of the heat sink is connected thermally to an extension member which extends generally perpendicular to the mounting plate, the extension member in turn being connected to a heat dissipation surface which may be one or several fins.

Abstract: An electronic assembly comprising an electronic module provided with optical interconnection and heat removal means, the heat removal means comprising a soleplate dedicated to removing heat on which the module is mounted. The interconnection means is independent of the soleplate and preferably comprises a printed circuit and an optical fiber included in the printed circuit. The optical fiber has an end put accurately in register with an optical contact of the module by a BGA type mounting of the printed circuit on the module. A BGA type mounting consists in placing with precision firstly balls on the module and secondly areas on the circuit, and then in bringing the balls and areas face to face so that the balls center themselves automatically with the areas by capillarity.

Abstract: An object is to provide a semiconductor device of a TCP or COF configuration including semiconductor chips mounted on a tape, which realizes compact mounting of a plurality of semiconductor chips on a single tape. In order to do so, a semiconductor chip having a lengthwise rectangular shape is mounted so as to have a long side substantially perpendicular to an extending direction of a Cu wiring pattern, thereby wiring numerous wires of the Cu wiring patterns substantially in parallel with each other, and substantially straight-line with respect to a destination of in-/output. Further, in the mounting of the plurality of semiconductor chips, a tape width can be reduced so as to miniaturize devices to be connected.

Abstract: An apparatus for connecting one substrate, such as flip-chip type semiconductor die, to an opposing substrate, such as a silicon wafer, printed circuit board, or other substrate. Each substrate has a plurality of conductive bumps on its facing surface wherein the conductive bumps on each substrate are the mirror-image of the other substrate. The substrates are attached to one another in a manner in which the conductive bumps on one substrate form an electrical contact with its respective conductive bumps on the opposing substrate without mechanical attachment.

Abstract: A ball grid array package semiconductor device having improved power line routing. The BGA package semiconductor device includes a semiconductor chip having a plurality of pads along its center, a substrate having a slot of a predetermined size along its center, and a signal line plane including a signal line pattern and a plurality of ball mounts on its one side, with the semiconductor chip being mounted on the other side. A bonding material is inserted between the semiconductor chip and the substrate to fix the semiconductor chip to the substrate. A plurality of balls are mounted on the plurality of ball mounts to be connected to an external circuit. The signal line plane is divided into two or more signal line planes including a first line plane and a second line plane. Lines for the first power are formed only on the first signal line plane, and lines for the second power are formed only on the second signal line plane.

Abstract: An object of the present invention is to provide a simple process for manufacturing a flexible printed wiring board having fine metal bumps.

Abstract: A method of de-oxidizing a surface onto which a refractory metal or molecule which contains a refractory metal atom will be adhered. The method utilizes a plasma which includes a gas such as argon, nitrogen, helium or hydrogen, or a mixture of any of the foregoing, to remove oxygen molecules from the surface to which adherence of the refractory metal is desired. Radicals in the plasma coat the surface to prevent further oxidation thereof. The method also includes techniques for depositing refractory metals onto a surface such as a substrate or layer of semiconductor material on which integrated circuitry has been fabricated.

Abstract: A semiconductor device includes a semiconductor substrate, a first interlayer dielectric film covering the semiconductor substrate, a second interlayer dielectric film covering the first interlayer dielectric, an opening having an upper-layer opening penetrating the second interlayer dielectric film, and a lower-layer opening penetrating the first interlayer dielectric film down to the surface of the semiconductor substrate and being connected to the upper-layer opening. The lower-layer opening being arranged such that diameter of the lower-layer reduces gradually from the upper-layer opening toward the semiconductor substrate. A conductive film covering at least the bottom surface of the lower-layer opening and side walls of the lower-layer and upper-layer openings.