Abstract: In a mass spectrometer, electrode element plates forming a virtual rod electrode have predetermined shapes at rim portions thereof in an ion optical axis side, and the electrode element plates are held at portions away from the ion optical axis by a holder, to thereby form a virtual rod multipole ion lens unit. Also, apart from the ion lens unit, there is provided a terminal unit for applying predetermined voltages to the respective electrode element plates. In the ion lens unit, the electrode element plates to which the same potential is applied are respectively connected by immovable short lines to form the groups. One of the electrode element plates in each group is electrically connected to the terminal unit.

Abstract: A mass spectrometer has an ion source for producing sample ions. The ions pass through an ion interface, to a reaction/collision cell section. An ion-neutral decoupling device is provided between the ion interface and the reaction/collision cell section, to provide substantial separation between ions and neutral particles, whereby only ions pass on to the reaction/collision cell section. The supersonic jet entering the spectrometer can have sufficient energy to cause the plasma gases, such as argon, to overcome the pressure differential between the reaction/collision cell and an upstream section of the spectrometer so as to penetrate into the reaction/collision cell; the decoupling device prevents this. The decoupling device can have offset apertures provided by plates or rods or other comparable arrangements, or can comprise a quadrupolar electrostatic deflector, an electrostatic sector deflector or a magnetic sector deflector.

Abstract: This invention relates to an electron optical system array having a plurality of electron lenses. The electron optical system array includes a plurality of electrodes arranged along the paths of a plurality of charged-particle beams. Each of the plurality of electrodes has a membrane in which a plurality of apertures are formed on the paths of the plurality of charged-particle beams, and a support portion which supports the membrane. At least two of the plurality of electrodes are arranged to form a nested structure.

Abstract: An optical system for a scanning probe microscope provides both an optical on-axis view and an optical oblique view of the sample by means of two optical paths each providing an image to a CCD camera via an auto-zoom lens. A shutter alternately blocks the image of either view from reaching the auto-zoom lens. The CCD camera provides the optical image to a video display which also displays the scanning probe image, thus eliminating the need for eyepieces and allowing easy viewing of both the optical and scanning probe images simultaneously.

Abstract: In order to provide a full-automatic scanning electron microscope which carries out investigation jobs full-automatically from fine adjustment to reviewing, the scanning electron microscope of the present invention has a function of calculating the accuracy of correction after correction of coordinates and displaying it with vectors 39, a function of automatically determining a searching magnification for automatic object detection from the obtained information after correction of coordinates, and a function of calculating the frequency of occurrence of objects or defects and a time required for measurement from the searching magnification and conditions of measurement.

Abstract: A method and apparatus for the inspection of a substrate provides consistent detection of defects such as cracks, differentiates between different types of defects, and, does not excessively heat the substrate. An infrared radiating source produces infrared energy which illuminates the substrate in a uniform manner at an incident angle. An infrared camera collects a portion of the infrared light which is reflected from the substrate. An image is created from the collected light which includes indicia of the defect. The image is examined as the incident angle is varied for changes in the appearance of the indicia.

Abstract: A radiation image sensor 10 comprises two optical members 12, 14; a scintillator 18 deposited on entrance end faces 12a, 14a of the optical members 12, 14; a plurality of light-guiding optical components 22; and a plurality of CCDs 20. Each of the optical members 12, 14 is an optical member in which several millions/cm2 of optical fibers are disposed parallel to each other and integrally molded, whereas the optical fibers have an axis forming an acute angle with the entrance end face 12a, 14a. The two optical members 12, 14 are arranged such that the optical fibers respectively constituting each of the optical members 12, 14 have a gap therebetween widening from the entrance end face 12a, 14a side to the exit end face 12b, 14b side. Respective side faces 12c, 14c of optical members 12, 14 are formed with ground surfaces 12d, 14d in which the respective side faces 12c, 14c of optical members 12, 14 are ground against each other.

Abstract: Method of acquisition of images of an object in an imaging system equipped with a rotating assembly comprising an energy beam emitter and an energy beam receiver, the energy beam being centered on an axis, in which a continuous path of the moving assembly is defined along at least two axes of a three-dimensional reference, the axis of the energy beam describing a left curve on the path; and, in the course of the path, the energy beam is emitted and images are acquired.

Abstract: An apparatus and method of detection and visualization of an infrared laser beam using an optically transparent or opaque solid medium doped with at least one active chromophore dye molecule to provide conversion of infrared radiation to visible light by means of two or three-photon absorption followed by emission of a visible photon is provided. A method of verifying mode-lock in mode-locked infrared laser sources and measuring the temporal and spatial shape of ultra short laser pulses having pulse durations between a few femtoseconds and hundreds of picoseconds is also provided.

Abstract: The present invention relates to a test method of a mask for electron-beam exposure which has a pattern region in which, by forming an electron-beam scatterer in prescribed shape on an electron-beam transmittable thin film, a scattering region with said electron-beam scatterer and a membrane region without said electron-beam scatterer are formed in prescribed pattern shape; wherein electron-beam irradiation onto a tested mask is carried out in a plurality of times, with each irradiated region subjected to irradiation at a time being scanned with the electron beam, and through detection of transmitted electrons which is made for each irradiated region subjected to irradiation at a time.

Abstract: The invention provides uniform ion dose at the wafer position by varying the current of the ion beam synchronously with the scan. The beam is scanned by a linear scan, and beam scan position information is sent from the beam scan electronics to the beam control circuit connected with the ion source; this information transfer preferably occurs over a fiber optic link to cross the high voltage between the two sets of electronics. At initiation, the beam current is held constant and a Faraday cup is scanned across the beam to measure the variation of dose with scan position. A beam versus scan position waveform is calculated to correct the variation in dose; and the waveform is then loaded into a memory in the ion beam control circuit. The ion beam control circuit then varies the output of the ion source synchronously with the scan to adjust the dose as a function of scan position, as determined by the waveform. If necessary, repeated measurements and waveform calculations can be made until the dose is uniform.

Abstract: An ion source (50) for an ion implanter is provided, comprising a remotely located vaporizer (51) and an ionizer (53) connected to the vaporizer by a feed tube (62). The vaporizer comprises a sublimator (52) for receiving a solid source material such as decaborane and sublimating (vaporizing) the decaborane. A heating mechanism is provided for heating the sublimator, and the feed tube connecting the sublimator to the ionizer, to maintain a suitable temperature for the vaporized decaborane. The ionizer (53) comprises a body (96) having an inlet (119) for receiving the vaporized decaborane; an ionization chamber (108) in which the vaporized decaborane may be ionized by an energy-emitting element (110) to create a plasma; and an exit aperture (126) for extracting an ion beam comprised of the plasma. A cooling mechanism (100, 104) is provided for lowering the temperature of walls (128) of the ionization chamber (108) (e.g., to below 350° C.

Abstract: A laser imaging apparatus for forming an image on a surface of a substrate is provided with a laser source that emits a laser beam, a table mounting the substrate, the table being movable in a first direction within a predetermined plane, a scanning optical system which receives and deflects the laser beam emitted by the laser source to form a scanning beam spot on the substrate, the scanning beam spot scanning in a second direction that is perpendicular to the first direction, and a mechanism that moves the scanning optical system in the second direction.

Abstract: An image reading apparatus includes three laser stimulating ray sources, a stage on which two or more kinds of image carriers can selectively be placed, a scanning mechanism for scanning the image carrier with a laser beam emitted from the laser stimulating ray sources, thereby stimulating the image carrier, a light detector for photoelectrically detecting light emitted from the image carrier in response to stimulation by the laser beam and a confocal optical system for leading light emitted from the image carrier to the light detector, the image reading apparatus further including a confocal switching member having pinholes of different diameters and disposed between the confocal optical system and the light detector.

Abstract: A valve for use in microfluidic structures. The valve uses a spherical member, such as a ball bearing, to depress an elastomeric member to selectively open and close a microfluidic channel. The valve may be operated manually or by use of an internal force generated to shift the spherical member to its activated position.

Abstract: A valve (12) for a motor vehicle air spring (2) having an ancillary volume (6) provides a finely metered continuous opening up to the complete cross section without throttle and a stable performance for flow forces results. The valve (12) is characterized by a star nozzle (50) which includes any desired number of slots nS (52) which mutually intersect and each slot has the length DS (58) and a width sS (56) and the slots are arranged so as to be concentric. The star nozzle peripheral length LUS (64) is increased compared to a round nozzle LUR. For the valve cross section, AVS=LUS·HS applies. The throughput cross section ADS of the star nozzle (50) is so large that it corresponds at least to the cross section AL of the inlet (68) and the outlet (70). A preferably triangular-shaped valley-like recess (66) is provided between each two mutually adjacent ones of the slots (52). The sealing body (40) of the valve (12) is preferably configured as a collar.

Abstract: A piezoelectric ceramic composition in which the dielectric constant, the mechanical quality factor Qm and the electromechanical coupling factor Kp are superior, and a high power output piezoelectric transformer made of it are disclosed.

Abstract: The present invention relates to the discovery of compositions which include fluoroethane, 2-fluoropropane or tert-butylfluoride. These compositions are useful as pure components or with at least one of tetrafluoroethane, difluoroethane, hexafluoropropane, a hydrocarbon or dimethylether.

Abstract: The present invention describes methods and chemical compositions for the spin etch planarization of surfaces, particularly copper and tantalum. An etching solution is brought into contact with the upper face of a spinning wafer through a nozzle, preferably an oscillating nozzle. The etching solution has a composition that oxidizes the spinning surface, forming a passivation layer thereon. The etching solution further contains reactants for removing the passivation layer exposing the underlying surface to further reaction, leading to the desired etching of the surface. The characteristics of the etching solution are adjusted such that reactant diffusion to lower regions of the surface limits the rate of etching. Faster reaction occurs at higher regions of the surface lying in more rapidly moving etching solution resulting in the desired planarization.

Abstract: The invention has an object to provide a solid chloride absorbent which can efficiently absorb inorganic chlorides such as hydrogen chloride flowing out from a process in which a heavy naphtha and the like are treated and inorganic chloride derived from crude oil, and which is difficult to powder and soften after absorbing the chlorides. The solid chloride absorbent according to the invention comprises zinc oxide, a porous refractory inorganic matter and an inert binder, has a long life, and hardly releases the absorbed chlorides.

Abstract: A method of producing an aluminate fluorescent substance, a fluorescent substance and a device containing a fluorescent substance. The method includes the steps of mixing an &agr;-alumina powder having an average primary particle size of from about 0.05 &mgr;m to less than 0.3 &mgr;m with a metal salt, and calcining the resulting mixture.

Abstract: A route to the fabrication of electronic devices is provided, in which the devices consist of two crossed wires sandwiching an electrically addressable molecular species. The approach is extremely simple and inexpensive to implement, and scales from wire dimensions of several micrometers down to nanometer-scale dimensions. The device of the present invention can be used to produce crossbar switch arrays, logic devices, memory devices, and communication and signal routing devices. The present invention enables construction of molecular electronic devices on a length scale than can range from micrometers to nanometers via a straightforward and inexpensive chemical assembly procedure. The device is either partially or completely chemically assembled, and the key to the scaling is that the location of the devices on the substrate are defined once the devices have been assembled, not prior to assembly.

Abstract: The present invention provides a system and method suitable for inspecting a semiconductor device whose terminals are formed from solder balls and protrude from a package, thus enabling high-speed inspection of a semiconductor device having a plurality of pins. Metal protuberances corresponding to respective terminals projecting from the bottom of a package of a semiconductor device are provided on an interface substrate. Contact sections corresponding to the respective metal protuberances are provided within each of a plurality of slide sections. The semiconductor device is set on the slide section such that the terminals are disposed opposite the respective metal protuberances. The slide sections are slid over the interface substrate, thereby bringing the side surfaces of the terminals of the semiconductor device into contact with the contact sections. Each of the contact sections is formed from a conductive contact plate, a elastic film, and a slide guide having rigidity.

Abstract: Each pixel of an EL display panel includes a diode element, an organic EL element, and a capacitor. The cathode of the diode element, the anode of the organic EL element, and one of the electrodes of the capacitor are electrically connected to one another at a common terminal. The anode of the diode element is connected to a signal electrode. The other electrode of the capacitor is connected to a scanning electrode. The cathode of the organic EL element is connected to the scanning electrode. A forward direction of the diode element and a forward direction of the organic EL element coincide. The voltage between the scanning electrodes is controlled to control the current flowing through the organic EL element. As a result, it is possible to provide an emitter having stable luminance with improved efficiency, and an emitting device and a display panel employing such an emitter.

Abstract: The present invention has an object to provide a photoreceptor array with an excellent device property and no short fault between adjacent photoreceptors and to provide a method of manufacturing such the photoreceptor array with a high yield. On a transparent substrate (31), a transparent electrode (32) and a p-type amorphous silicon layer (33) are formed. An insulating layer (41) is deposited thereon to form a trench (42). In the trench (42), an i-type amorphous silicon layer (34), an n-type amorphous silicon layer (35) and an n-side electrode (36) are buried in turn to form the photoreceptor array.

Abstract: A device region surrounded by a device isolation region has a rectangular shape with a width in a direction in which a gate electrode of a transfer gate extends. A signal accumulation region of a photodiode is disposed on the entirety of that portion of the device region, which is located on a source side of the gate electrode of the transfer gate. A detection section having a width in the direction in which the gate electrode extends is disposed on that portion of the device region, which is located on a drain side of the gate electrode of the transfer gate. The size of the detection section is set to be as small as possible. Two edge portions of the detection section, which are located in the direction of extension of the gate electrode, are spaced apart from the device isolation region.

Abstract: A thin film field effect transistors and manufacturing method for the same are described. The channel region of the transistor is spoiled by an impurity such as oxygen, carbon, nitrogen. The photosensitivity of the channel region is reduced by the spoiling impurity and therefore the transistor is endowed with immunity to illumination incident thereupon which would otherwise impair the normal operation of the transistor. The spoiling impurity is not introduced into transistors which are located in order not to receive light rays.

Abstract: A vertical Schottky diode including an N-type silicon carbide layer of low doping level formed by epitaxy on a silicon carbide substrate of high doping level. The periphery of the active area of the diode is coated with a P-type epitaxial silicon carbide layer. A trench crosses the P-type epitaxial layer and penetrates into at least a portion of the height of the N-type epitaxial layer beyond the periphery of the active area. The doping level of the P-type epitaxial layer is chosen so that, for the maximum voltage that the diode is likely to be subjected to, the equipotential surfaces corresponding to approximately ¼ to ¾ of the maximum voltage extend up to the trench.

Abstract: An opto-electronic device has a diffusion area of one conductive type formed in a semiconductor substrate of another conductive type, an ohmic contact layer making contact with the diffusion area, and an electrode making contact with the ohmic contact layer. The diffusion area is formed by solid-phase diffusion. The same mask is used to define the patterns of both the diffusion source layer and the ohmic contact layer, so that the ohmic contact layer is self-aligned with the diffusion area.

Abstract: A high emission intensity group-III nitride semiconductor light-emitting device obtained by eliminating crystal lattice mismatch with substrate crystal and using a gallium nitride phosphide-based light emitting structure having excellent crystallinity. A gallium nitride phosphide-based multilayer light-emitting structure is formed on a substrate via a boron phosphide (BP)-based buffer layer. The boron phosphide-based buffer layer is preferably grown at a low temperature and rendered amorphous so as to eliminate the lattice mismatch with the substrate crystal. After the amorphous buffer layer is formed, it is gradually converted into a crystalline layer to fabricate a light-emitting device while keeping the lattice match with the gallium nitride phosphide-based light-emitting part.

Abstract: A heterojunction bipolar transistor comprises a collector layer, a base layer, and an emitter layer stacked sequentially. The base layer comprises a first base layer joined to the collector layer in an inward base area directly below the emitter layer and a second base layer joined to the collector layer in an outward base area adjacent to the inward base area. The second base layer is formed of a semiconductor with a wider energy band gap than the collector layer.

Abstract: A semiconductor memory device having self-aligned contacts, capable of preventing a short-circuit between contacts for bit lines and contacts for storage electrodes and improving a process margin, and a method of fabricating the same are provided.

Abstract: A semiconductor device and a method of laying out the same includes routing primary power and ground distributions in the second metallization layer, rather than the first metallization as is conventionally done. This improves routability in the first metallization layer while providing sufficient current handling ability in the power and ground distributions.

Abstract: A semiconductor integrated circuit includes a first wiring layer formed in a first direction, a second wiring layer formed in a second direction perpendicular to the first direction, and a third wiring layer formed in the second direction to sandwich the first wiring layer between the third wiring layer and the second wiring layer. The second and third wiring layers are shifted from each other by a predetermined distance in the first direction. An automatic layout method for a semiconductor integrated circuit, and a recording medium are also disclosed.

Abstract: In general, the output of a buried channel CCD is provided with a floating diffusion (4), which forms a storage site to determine the size of an electric charge. For this purpose, the floating diffusion may be connected to the input of an amplifier, such as a source follower (8). The charge is transferred to the floating zone from below an output gate OG to which a DC voltage is applied. To obtain a high sensitivity, i.e. a high voltage per electron, it is important to keep the capacitance of the floating zone as small as possible. The capacitance can be reduced by narrowing the channel at the output. This method of reducing C, however, is limited in known structures because this shape of the channel may induce an electric field in the channel which counteracts the transfer to the floating zone. To suppress this effect, the gate oxide (5) below the output gate is provided with a thicker part (5b) adjoining the floating diffusion (4).

Abstract: In the present invention, a charge transfer unit is arranged on a first-plane side of a thinly-formed semiconductor base. Charge accumulating units are arranged on a second-plane side, the opposite side. A depletion prevention layer is arranged closer to the second-plane side than the charge accumulating units. The depletion prevention layer prevents a depletion region around the charge accumulating units from reaching the second plane of the semiconductor base. The depletion prevention layer can suppress surface dark current going into the charge accumulating units. Meanwhile, an energy ray incident from the second-plane side pass through the depletion prevention layer to generate signal charges in the charge accumulating units (depletion regions). The charge accumulating units collect, on a pixel-by-pixel basis, the signal charges which are to be transported to the charge transfer unit under voltage control or the like, and then are read to exterior as image signals.

Abstract: A solid picture element that transfers charges completely from a photodiode portion to an amplifying transistor portion to substantially eliminate residual images and methods of its manufacture are disclosed. The solid picture element includes a buried photodiode and a transistor in communication with a transfer gate that is a selective transfer path for charges from the photodiode to the transistor. The charge accumulation region is located so that it is not in contact with the upper surface of the semiconductor substrate and so that a margin of the charge accumulation region is located 0.0 to 0.2 &mgr;m closer to the transistor than any portion of the depletion prevention region. Methods of manufacture of the picture element of the present invention include using the transfer gate as a mask and implanting ions into a semiconductor substrate at a first angle to form the charge accumulation region and at a second, steeper, angle to form the depletion prevention region.

Abstract: This invention obtains desired operating characteristics from an MISFET in which a p-type silicon gate electrode is used by preventing the leakage of boron into the channel region in the following way. N-type amorphous silicon 9n is formed by ion-implanting phosphorus into an amorphous silicon. Next, boron is ion-implanted in n-type amorphous silicon 9n to convert it into p-type amorphous silicon 9p. Amorphous silicon 9p is then crystallized. Finally, the gate electrode of the MISFET is constructed of the p-type polycrystalline silicon, which has been obtained in the above steps, and in which phosphorus and boron have been implanted.

Abstract: The invention relates to a solid-state pickup element that can achieve both improvement in the sensitivity and reduction of pixel size and a method for producing the same, wherein a solid-state pickup element 1 is constructed, which includes a first conductive type semiconductor area 21, which is formed at least so as to include the inside of the semiconductor substrate 2 upward of the overflow barrier area 3 inside the semiconductor substrate 2, and a charge accumulating area 6 at the position corresponding to the first conductive type semiconductor area 21 of the light receptive sensor part 5 in the epitaxial layer 4 on the semiconductor substrate 2.

Abstract: An integrated circuit contains a planar first transistor and a diode. The diode is connected between a first source/drain region of the first transistor and a gate electrode of the first transistor such that a charge is impeded from discharging from the gate electrode to the first source/drain region. A diode layer that is part of the diode is disposed on a portion of the first source/drain region. A conductive structure that is an additional part of the diode is disposed above a portion of the gate electrode and is disposed on the diode layer. The diode can be configured as a tunnel diode. The diode layer can be produced by thermal oxidation. Only one mask is required for producing the diode. A capacitor can be disposed above the diode. The first capacitor electrode of the capacitor is connected to the conductive structure.

Abstract: Integrated circuit capacitors in which the capacitor dielectric is a thin film of BST having a grain size smaller than 200 nanometers formed above a silicon germanium substrate. Typical grain sizes are 40 nm and less. The BST is formed by deposition of a liquid precursor by a spin-on process. The original liquid precursor includes an alkoxycarboxylate dissolved in 2-methoxyethanol and a xylene exchange is performed just prior to spinning. The precursor is dried in air at a temperature of about 400° C. and then furnace annealed in oxygen at a temperature of between 600° C. and 850° C.

Abstract: A memory device structure is provided in which the array oxide layer has a thickness that is greater than the thickness of the support oxide layer.

Abstract: A metal-insulator-metal (MIM) capacitor of a semiconductor device, and a manufacturing method thereof, includes a lower electrode formed of a refractory metal or a conductive compound including the refractory metal, a dielectric film formed of a high dielectric material, and an upper electrode formed of a platinum-family metal or a platinum-family metal oxide. Accordingly, the MIM capacitor satisfies the criteria of step coverage, electrical characteristics and manufacturing costs, as compared to a conventional MIM capacitor in which the upper and lower electrodes are formed of the same material such as a platinum-family metal, a refractory metal or a conductive compound including the refractory metal. The capacitor is especially suitable for mass production in semiconductor fabrication processes.

Abstract: A capacitor with sufficient capacity can be prepared without increasing the step between the memory cell portion and surrounding area to the extent that photolithography becomes difficult. A silicon dioxide film 128, silicon nitride film 130, and resist layer 130 are layered on an underlying layer 118. Openings (capacitor pattern) 134 and 135, which are the size of the photolithography resolution limit, are formed in the resist film and silicon nitride film using photolithography. The silicon nitride film with the openings acts as a mask and a pocket 138 with an aperture area greater than the capacitor pattern is formed in the silicon dioxide film with isotropic etching. A conductive polysilicon film 140 is formed on the wall surface of this pocket; the thickness of the polysilicon film is controlled. This film is patterned and a storage electrode 120 is formed.

Abstract: A semiconductor memory of this invention is composed of an MFMIS transistor including a first field effect transistor and a ferroelectric capacitor formed on or above the first field effect transistor with a gate electrode of the first field effect transistor working as or being electrically connected to a lower electrode of the ferroelectric capacitor, an upper electrode of the ferroelectric capacitor working as a control gate and the first field effect transistor having a first well region; and a second field effect transistor having a second well region that is isolated from the first well region of the first field effect transistor. The first well region of the first field effect transistor is electrically connected to the source region of the second field effect transistor, and the gate electrode of the first field effect transistor is electrically connected to the drain region of the second field effect transistor.

Abstract: The invention comprises capacitors having a capacitor dielectric layer comprising a metal oxide having multiple different metals bonded with oxygen. In one embodiment, a capacitor includes first and second conductive electrodes having a high k capacitor dielectric region positioned therebetween. The high k capacitor dielectric region includes a layer of metal oxide having multiple different metals bonded with oxygen. The layer has varying stoichiometry across its thickness. The layer includes an inner region, a middle region, and an outer region. The middle region has a different stoichiometry than both the inner and outer regions.

Abstract: Methods of forming a channel region between isolation regions of an integrated circuit substrate are disclosed. In particular, a mask can be formed on an isolation region that extends onto a portion of the substrate adjacent to the isolation region to provide a shielded portion of the substrate adjacent to the isolation region and an exposed portion of the substrate spaced apart from the isolation region having the shielded portion therebetween. A channel region can be formed in the exposed portion of the substrate. Related integrated circuits are also discussed.

Abstract: A memory cell array is provided at a non-volatile semiconductor storage apparatus. In a memory cell array, the unit cell includes a memory cell field effect transistor and a select field effect transistor. The memory cell field effect transistor has a floating gate and a control gate. The select field effect transistor has a drain connected to a source of the memory cell field effect transistor. The floating gate and control gate extends to a position above a gate of the select field effect transistor.

Abstract: A semiconductor memory device is provided, which makes it possible to increase the capacitance of capacitors in the capacitor section without degrading the withstand voltage of the capacitor dielectric. This device comprises a memory cell section including floating-gate type transistors and a capacitor section including capacitors. The memory cell section and the capacitor section are formed on a semiconductor substrate. Each of the transistors has a first gate dielectric, a floating gate, a second gate dielectric, and a control gate. Each of the capacitors has a lower electrode, a capacitor dielectric, and an upper electrode. A first part of the capacitors is/are designed to be applied with a first voltage and a second part thereof is/are applied with a second voltage on operation, where the first voltage is lower than the second voltage. Each of the first part of the capacitors has a recess formed on the lower electrode, thereby increasing its capacitance.

Abstract: A semiconductor memory device disclosed herein comprises a memory cell array in which memory cells are arranged in a matrix and a row decoder circuit for selecting a word line in this memory cell array and for applying a voltage to the selected word line. The decoder circuit includes a plurality of first transistors of a first conductivity type in which one end of each current path is directly connected to each of the word lines, and a second transistor of a second conductivity type opposite to the first conductivity type for applying a voltage to a gate of the first transistor connected to a selected word line at the time of the operation for applying a voltage to the selected word line. The application of a voltage to the selected word line is performed only by the first transistor of the first conductivity type.