Abstract: A controller has two shunt lines connected in parallel with safety relays. For testing their switching capability, the safety relays are reversed to their idle positions and the change in voltage is monitored on their idle contacts. If voltage is missing, an error signal is issued. During the test, the parallel shunt line is closed so that the safety power line is not interrupted. Switching amplifiers having a response and action time which is a fraction of the preset response time of the safety relays control the safety relays. For testing the electrical control, the drives of the safety relays are switched to currentless and the change in voltage is monitored on the drives. If the change in voltage is inadequate, an error signal is issued. The safety relays remain in their operating positions during the test.

Abstract: In an electrostatic protection circuit of the present invention, a trigger voltage for causing snapback operation in MOSFET is reduced and circuit elements with low breakdown voltages can be protected. A protection nMOSFET having a drain connected to an input/output terminal and a source and a substrate that are grounded is provided. A diode array, composed of at least one diode, is connected in series in a forward direction between the gate of the protection nMOSFET and the input/output terminal. Finally, a resistor is connected between the gate of the protection nMOSFET and ground.

Abstract: To shorten the recovery time of a line driver (1) after an overvoltage on its output terminal (3), a current generating device (5) senses a voltage difference between the output voltage of the line driver (1) and its supply voltage (UB) plus a threshold voltage (UT′), and supplies a current (I) that is proportional to the sensed voltage difference up to a maximum current to the output (3) of the line driver (1) to raise its potential to thereby shorten its recovery time.

Abstract: A circuit arrangement provides a way of protecting a differential pair of bipolar transistors by diverting the current into an n-channel MOSFET which is driven into conduction during an ESD event and allows a larger swing of input voltage than the anti-parallel diode pair. No extra processing steps are required and the MOSFET is driven on, rather than relying on parasitic bipolar npn transistor triggering into snap-back as in the grounded gate NMOS transistor that is commonly used for ESD protection in CMOS integrated circuits. An ESD protection circuit is provided for protecting a differential pair of transistors having two input terminals.

Abstract: A transmission control circuit 10 which is adapted for use with an electronically controlled transmission having several transmission control solenoids 12, 14 and 16 and a selectively positionable gear selector 18. Circuit 10 includes a conventional controller 20, electrical switches 22, 24 and 26, a transmission range sensor 28, and vehicle sensors 32. Transmission range sensor 28 is ganged with switches 22, 24 and 26 and is further communicatively coupled to controller 20. Switches 22, 24 and 26 are operatively coupled to gear selector 18 and are respectively and operatively disposed between a battery 30 and solenoids 12, 14 and 16. Switches 22, 24 and 26 are effective to selectively connect and disconnect solenoids 12, 14 and 16 to/from battery 30, thereby selectively enabling and disabling solenoids 12, 14 and 16.

Abstract: A room ionization system includes a plurality of emitter modules, each including an electrical ionizer. The emitter modules are spaced around the room and are connected in a daisy-chain manner to a system controller. Each emitter module has an individual address for allowing the system controller or a remote control transmitter to individually address and control each emitter module. Electrical lines containing both power and communication lines connect the plurality of emitter modules with the system controller. Each emitter module stores a balance reference value and an ion output current reference value for use by automatic balance control and automatic ion output current control circuitry.

Abstract: One aspect of the present invention elates to a method of reducing electrostatic charges on a patterned photoresist to improve evaluation of the developed photoresist, involving the steps of evaluating the patterned photoresist to determine if electrostatic charges exist thereon; positioning an ionizer near the patterned photoresist, the ionizer generating ions thereby reducing the electrostatic charges on the patterned photoresist; and evaluating the patterned photoresist with an electron beam.

Abstract: A capacitive device includes a substrate (110), a first electrode (130, 140, 1220) located over the substrate and a second electrode (170, 1070, 1071, 1250) located over the first electrode, movable relative to the first electrode, and capacitively coupled to the first electrode. The device further includes a first control electrode (120, 150, 1210) located over the substrate and a second control electrode (160, 180, 1060, 1061, 1080, 1081, 1240) located over the first control electrode, movable relative to the first control electrode, and capacitively coupled to the first control electrode. The first and second control electrodes actuate the second electrode toward the first electrode.

Abstract: A method for configuring a bypass capacitor for use in conjunction with an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes selecting mechanical dimensions for the bypass capacitor, the mechanical dimensions causing the bypass capacitor to exhibit electrical losses at a clock frequency of the integrated circuit device. The bypass capacitor preferably includes a ferroelectric dielectric material. In addition, the selection of mechanical dimensions for the bypass capacitor determines a mechanical resonance frequency for the bypass capacitor, with the mechanical resonance frequency corresponding to the clock frequency.

Abstract: An electrical capacitor is discloses which includes a mixture of electrically conductive and non-conductive particles. The particles are intimately mixed so as to provide a random distribution, and the mixture is placed between two parallel conductive plates to which electrical leads are attached and pressure is applied.

Abstract: It is an object of the present invention to provide a device having a crystalline oxide layer of complex compound which can form a crystalline thin film with high orientation. The lower electrode 13 comprises tantalum layer 11, titanate layer 12 and platinum layer 6, and PZT thin film 8 is formed on the lower electrode 13. Since titanate layer 12 is formed on the lower electrode 13, crystallinity of the PZT thin film can be improved. Therefore, the “lift-off” method can be used with to no thermal treatment needed when forming the platinum layer 6.

Abstract: An electric double-layer capacitor (EDLC) has a laminated overcoat encapsulating a stacked body including a plurality of basic cells and a pair of terminals sandwiching therebetween the stacked body. The innermost film of the laminated overcoat is thermally fused onto the exposed surfaces of the terminal plates and the stacked body substantially without a gap. The fusing step is conducted by an equal-pressure pressing using a hot water while the internal of the laminated overcoat is evacuated.

Abstract: An electric double layer capacitor of the present invention having a capacitor element and an electrolyte arranged in a case sealed with a sealer, and further includes in the case a solid buffer for suppressing fluctuation in pH of the electrolyte. The solid buffer includes a compound selected from an oxide and a hydroxide. An element contained in the compound is at least one selected from the group consisting of Be, Al, Si, Sc, V, Cr, Fe, Ni, Cu, Zn, Ga, Ge, Y, Zr, Mo, Ag, Cd, In, Te, La, Ce, Pr, Nd, Pm, Gd, Dy, Ho, Er, Tm, Lu, W and Pb.

Abstract: The electronic component of the present invention includes a case having an opening, an electronic component element and electrolytic solution disposed in the case, and a sealing member disposed so as to seal the opening. The sealing member has elasticity and is formed of a cross-linked structure of compound. The compound contains butyl rubber polymer as main component, phenol-based additive, and silane-based additive. Accordingly, the sealing member is improved in air-tightness, and the volatilization of the electrolytic solution becomes lessened. Further, an electronic component having such sealing member ensures excellent mounting ability. As a result, it is possible to obtain an electronic component capable of assuring excellent reliability for a long period of time even in a high temperature atmosphere and under high-temperature high humidity conditions.

Abstract: There is provided a structure for mounting an electronic part, including (a) an electronic part in the form of a chip, (b) a resin block entirely covering the electronic part therewith, and (c) a pair of electrodes electrically connected to the electronic part and extending outwardly of the resin block, the electronic part being deviated in position in a direction relative to a center of the structure, the resin block being formed with a raised portion extending downwardly from a bottom surface of the resin block, the resin block having a tapered portion between a top surface of the raised portion and the bottom surface of the resin block in the direction.

Abstract: In order to provide a keyboard device in which a pad used as a palmrest can be stored in the main body, a lock member and an operating segment are integrally formed by a resin resilient member. An engaging segment is formed at the extremity end of a resilient piece constituting a part of the resilient member, the engaging segment is inserted into an engaging hole formed at the pad and it is locked with the pad stored in a notch. Releasing of the locked state is performed such that the resilient member is resiliently deformed while the operating segment is pressed and then the engaged state between the engaging segment and the engaging hole is released.

Abstract: The present invention provides a display device and information terminal device wherein the installation of the display module is simple and the number of parts reduced, and that exhibits strength towards shocks. A projection 11 projecting towards a back cover 5 is provided on a front cover 6, a hole 12 into which the projection 11 is inserted is provided in a liquid crystal module 4, and at the same time, a hook 13 is provided that, while pressing the projection 1 inserted into the hole 12, deforms towards the back cover 5 due to the insertion of the projection 12, and a recess 14 is provided that engages the hook 13 that has been deformed by the insertion of the projection 11.

Abstract: An improved hinge mechanism for use with a portable computing device is disclosed. The present invention relates to a hinge mechanism that is suitable for use in a portable computing device. According to one aspect of the present invention, a hinge mechanism that is used with a door in a portable computing device includes a spring coil, a stopper, and a pivot arm. The spring coil has a compressive state, e.g., the spring coil may be compressed or decompressed. The pivot arm is coupled to the stopper, and includes a first section as well as a second section. The first section is arranged to be positioned substantially within the spring coil, and the second section is arranged to be coupled to the door. Translational motion of the pivot arm causes the stopper to cause the compressive state of the spring coil to change. In one embodiment, the translational motion of the pivot arm causes the stopper to cause the spring coil to compress.

Abstract: The present invention is an improvement on the functionality of garments of personal protection. The design is a portable computer system with all of the system components incorporated into an item of personal wear, for example into a garment such as a vest, that is shielded by a layer of armor. The armored garment will protect the user and completely house the processing unit, input device, and any peripheral attached to the processing unit.

Abstract: A computing system includes a frame and a drive mounting structure for mounting one or more drive units within the computing system, with the drive mounting structure being pivotally and removably mounted on the frame to move between an operating position, in which an internal end of a drive unit mounted within the drive mounting structure is held within the computing system, and a service position, in which the internal end of the drive unit extends outward from the computing system. In the service position, access is provided to an open end of the drive mounting structure, into which the drive unit can be installed, to the internal end of the drive unit, for attachment of a cable, and to a side of the drive mounting structure, through which fasteners are driven to mount the drive unit within the drive mounting structure.

Abstract: A computer which possesses a bottom keyboard housing having a rear edge hingedly connected with the lower edge of an openable display assembly, and wherein heat-generating computer electronics contained in the housing has heat removed therefrom through the intermediary of heat pipes which are hingedly connected with at least one heat dissipator located in the display assembly. In essence, the computer incorporates an inexpensive construction of heat pipe hinges employed in the thermal interconnection of the bottom keyboard housing of the portable personal computer containing the keyboard and electronics with the display assembly, wherein the heat pipes are protected from bending stresses prior to assembling the major portions of the portable personal computer, such as the keyboard housing and the display assembly.

Abstract: A toggle heat sink clip assembly includes a support base having a first end and a second end opposite the first end. A spring member has a first end and a second end, the first end of the spring member being pivotally attached to the first end of the support base. A rigid handle has a first end and a second end, the first end of the handle being pivotally attached to the second end of the support base. A rigid pivot member has a first end and a second end, the first end of the pivot member being pivotally attached to the second end of the spring member, and the second end of the pivot member being pivotally attached to a mid portion of the handle. The clip is movable to a locked position whereby a heat sink is retained in secured engagement with a microprocessor in a computer chassis.

Abstract: A heat pipe hinge structure for an electronic device comprises a heat pipe hinge member and a hinge portion. The heat pipe hinge member is made of a high heat-conductive material disposed at a coupling portion in which a pair of housing portions to be opened and closed are coupled. The heat pipe hinge member comprises a heat pipe hinge main body to receive a heat from a heat generating component disposed in one of the pair of housing portions, and a heat pipe holding portion provided in a vicinity of the heat pipe hinge main body to pivotably hold by an elastic member at least a part of a first heat pipe disposed in other of the pair of housing portion. The hinge portion is made of a low heat-conductive material to fix the heat pipe hinge member on at least one housing portion of the pair of housing portions.

Abstract: A pull/latch type fixing device for head-radiating fin body, including a heat-radiating fin body and two fastener units. Two sides of top end of the heat-radiating fin body are respectively formed with two latch grooves. Each fastener unit is inserted in the latch groove, including a locating frame, a latch frame and a pull lever. Two lateral walls downward extend from two ends of the locating frame. The latch frame is bridged between the latch groove and the locating frame. Two latch arms respectively downward extend from two ends of the latch frame. The pull lever is pivotally mounted on the latch frame and has a pair of cam plates. By means of turning the pull lever, the latch arms of the latch frame are biased inward by the lateral walls of the locating frame to tightly hook the latch seat beside the chip.

Abstract: An assembly comprising an integrated cooling system/liquid containment system/EMI shield/pump housing/heat sink is built atop a multi-chip module. The attached devices are cooled by a spray of fluid, effecting a phase change from liquid to gas at the point of evaporation. Condensing liquid accumulates at the base of the fins and is collected by a pump for redistribution. The pump is coupled to a fan blade, which in turn is operated by a motor. A seal is formed between the multi-chip module and the integrated housing. The assembly is designed such that this seal need not be broken to service the motor, thus minimizing the amount of vapors from the working fluid lost into the atmosphere. Case fins and fan blades are arranged for improved efficiency.

Abstract: The present invention relates to a heat dissipation structure for a notebook type computer, capable of effectively dissipating heat generated from a high temperature element (such as a CPU). The heat dissipation structure comprises a main body, a display device and a hinge shaft for coupling the main body with the display device, wherein the hinge shaft is arranged above the main body at a distance therefrom, and a heat dissipation means is provided in the main body.

Abstract: An electronic equipment enclosure (10) for housing electronic equipment (11), and broadly comprising a pivot bracket (22); a plurality of sleeves (24), each being associated with a transmit terminal (26), a receive terminal (28), protective circuitry (30), and test circuitry (32); a spreader plate (38); and a heat sink (40). The pivot bracket (22) allows for tilting an outer housing (12) up to 30° relative to a mounting surface. The separate and distinct transmit and receive terminals (26,28) maintain minimum cross-talk and interference levels. The protective and the test circuitries (30,32) are located on daughter boards adjacent each sleeve (24) so as to be easily accessible. The spreader plate (38) is operable to force the sleeves (24) into direct contact with the interior surface of the outer housing (18). The heat sink (40) is operable to facilitate conductive heat transfer between the sleeves (24) and the lid (18).

Abstract: An apparatus for use with data processing systems. In one embodiment, the apparatus includes but is not limited to at least one conductive member having a first end electrically coupled to a first conductive structure which partially forms a moat and a second end electrically coupled to a second conductive structure which substantially spans the moat, with the second conductive structure having at least a part overhanging a third conductive structure which partially forms the moat.

Abstract: A dual-sided circuit board module designed for an operating position that is not perpendicular to a system motherboard will be coupled to the motherboard by leads having at least two different lengths. Because leads of differing lengths have differing associated inductance, the operating characteristics of the leads and therefore the devices coupled to the leads will differ. In order to improve the operating characteristics of the module, integrated circuit packages are selected based on the inductive (and possibly other) qualities of the leads to which the respective packages are coupled. In one embodiment, leads having a larger inductance are coupled to integrated circuit (IC) packages having a smaller inductance and vice versa, which allows the inductive characteristics of the various components of the module to have more closely matching inductive characteristics than would otherwise be possible.

Abstract: An interposer adapted to be used between a mounting board and a semiconductor chip which is to be mounted on the mounting board. The interposer having a heat-resistant insulator having first and second surfaces, the insulator being provided with a plurality of through-holes opened at the first and second surfaces; wiring patterns formed on the first and second surfaces of the insulator electrically connected to each other by means of a conductor provided on an inner wall of at least one of the through-holes; and a capacitor. The capacitor has first electrode formed on the insulator and having a connecting portion formed on an inner wall of at least one of the other through-holes, a dielectric layer formed on the first electrode, and a second electrode formed on the dielectric layer.

Abstract: The invention relates to a multiple-component unit in which at least two passive components have been realized one above the other. A multiple-component unit thus comprises at least one resistor and at least one capacitor, or at least two capacitors. This space-saving construction allows for a miniaturization of circuits. A further miniaturization can be achieved in that the multiple-component units are not manufactured as discrete components, but are integrated into ICs.

Abstract: A microprocessor EMI shield is configured for isolating EMI emissions from the microprocessor, and grounding any electric potential caused by EMI emissions detected by the microprocessor heat sink. The microprocessor EMI shield includes a low-impedance conductive surface sufficient for conducting electric potential induced based on EMI emissions from the microprocessor. The microprocessor EMI shield also includes an array of apertures for accommodating the respective microprocessor pins. The array of apertures includes a first group of apertures for accommodating the microprocessor non-ground pins, each having a spaced diameter for avoiding contact with the corresponding non-ground microprocessor pin, and a second group of apertures for accommodating the microprocessor ground pins.

Abstract: A ring-free zero-voltage switching technique for use in a switching power converter having a zero-voltage switching circuit to achieve high-performance and high-density zero-voltage switching and a transformer to produce an oscillatory L-C circuit at the primary side thereof during zero-voltage switching of the switching power converter, the technique includes the step of short-circuiting the current at inductance means of the L-C circuit upon the occurrence of ringing, and to suppress the voltage at capacitor means of the L-C circuit, so as to eliminate parasitic ringing produced by the zero-voltage switching circuit, to effectively reduce power loss and lower the reverse voltage rating requirement to the secondary side rectification component, to greatly increase the working frequency and power density, to eliminate EMI noises, to minimize the size of the heat sink required for dissipating heat energy from the power MOSFETS, and to let the switching power converters meet the requirements of international EM

Abstract: Single, multistage, and distributed magnetic switched and tank resonant power conversion systems use a non saturating magnetic element (NSME). The NSME provide superior protection to conducted lightning transients, superior thermal operating bandwidth, higher magnetizing efficiency, greater flux/power density potential and form factor flexibility when implemented with the disclosed circuit strategies. Output voltage is maintained substantially constant and ripple free in the presence of line and load variations by the action of various feedback strategies. These mechanisms combine to produce compensations by controlling the duration and/or frequency of a switch or switches. A novel function generator implementation supplies a signal which is a function of magnetic flux tracking, AC line phasing, and output voltage feedback to provide output regulation, active ripple rejection, and power factor correction to the AC line.

Abstract: The invention has a first series circuit consisting of a capacitor and a diode and a second series circuit consisting of a coil and a diode, the first series circuit is connected in parallel to the commutating diode in a state that the capacitor is connected to a choke coil side in the commutating diode, and the second series circuit is connected between a connecting portion of the capacitor and the diode in the first series circuit and a commutating diode non-connecting side in the choke coil.

Abstract: An apparatus for converting direct voltage into alternating voltage and conversely comprises a VSC-converter (8) having a direct voltage intermediate link (9) and at least one phase leg (12, 13). Each current valve (14-17) of the phase legs has at least one semiconductor device of turn-off type and a rectifying member connected in anti-parallel therewith. A transformer (19) has two opposite ends of a first winding (20) thereof connected to an output (21, 22) each of the VSC-converter and a second winding (23) connected to a direct converter having at least one phase leg. Each of the current valves of the direct converter being able to conduct current and block voltage in both directions and to turn on by gate control. A midpoint (27) of the phase leg of the direct converter is provided with a phase output for forming a terminal for the alternating phase voltage between this output and a further phase output (28).

Abstract: A DC/DC converter converts a voltage of a DC power supply to another DC voltage by switching on and off a switching element, which determines an oscillating period and a forced stop period of the switching element based on a comparison signal obtained by comparing an output of an output-voltage detecting and adjusting circuit, which controls the output of the DC/DC converter at a certain voltage, and an output of a triangular-wave generating circuit in a second comparator. The DC/DC converter facilitates confining the pulsation of the output voltage of the DC/DC converter caused by the maximum load in the state of light load including the state of no load, within an allowable range.

Abstract: In a power conversion device comprising an AC filter 2 for harmonic current suppression having a combination of at least some of a reactor, capacitor and resistance and a power conversion circuit 3 that converts AC power into DC power or DC power into AC power and is connected to an AC power source 1 through AC filter 2, by providing: voltage reference calculation means (unit) 5 that calculates and outputs a voltage reference corresponding to the voltage that is to be output by the power conversion device main unit; current detection means (unit) 4 that detects and outputs current flowing through a prescribed location between AC power source 1 and power conversion circuit 3; and voltage reference correction means (unit) 8 that uses the output from current detection means (unit) 4 as a voltage reference correction signal to correct the voltage reference that is output from voltage reference calculation means (unit) 5, resonance of the AC filter for harmonic current suppression is suppressed without employing a

Abstract: The invention is designed for vehicles having two electrical power supply systems and corresponding differentiated voltage level charges and two batteries operating at a first and a second voltage level. A bidirectional voltage converter cooperates with both systems whose input and output stages are galvanically insulated and include a switch. The batteries are connected to said input and output at a first and a second voltage level so that said bidirectional converter can provide a first reduced voltage mode and a second increased voltage mode. The passive components, e.g. the magnetic components and capacitances, of said stages have been chosen to provide an identical transitional behavior in both modes when a disruption occurs in the regulating system either in the charge or the input voltage.

Abstract: A DC power supply device comprises an AC/DC converter 1, a DC/DC converter 2, and a DC converter 3 converting DC power from a battery 4 to DC voltage for connecting to output terminals of the AC/DC converter. The DC power supply device is provided with a controlling circuit 100 which observes a charging control level and a load sharing level, impresses a charging command on a UPS controlling part controlling the DC converter, and simultaneously provides a PFC controlling part controlling the AC/DC converter with a current command when a voltage level is less than the charging control level, stops only the charging command when the voltage level is more than the charging level and less than the load sharing level, and provides the UPS controlling part and the PFC controlling part with current commands when the voltage level is more than the load sharing level.

Abstract: A semiconductor memory device comprises a memory cell array, a block select circuit, a plurality of word-line-driving-signal lines, and a plurality of transfer transistors. The memory cell array includes a plurality of blocks, each of the blocks including memory cells arranged in rows and columns. The block select circuit selects one of the blocks of the memory cell array. The word-line-driving-signal lines receive voltages to be applied to a plurality of word lines in each block. The transfer transistors are connected between the word-line-driving-signal lines and the word lines of the memory cell array, and are controlled by outputs from the block select circuit. Any two of the transfer transistors, which correspond to each pair of adjacent ones of the word lines, are separate from each other lengthwise and widthwise, and one or more transfer transistors corresponding to another word line or other word lines are interposed therebetween.

Abstract: High device reliability, a reduction in power consumption, and a high operation speed are achieved. When a predetermined bias voltage is applied between a source 1 and a drain 2 to change a gate voltage, a current discretely flows between the source 1 and the drain 2 in accordance with quantized electrostatic energy levels in an island electrode 3. The switching ON/OFF of the current between the source 1 and the drain 2 in this case is enabled by applying ½-electron charge to a gate. When the gate voltage induces polarization in a ferroelectric layer 6, its electric field is applied to the island electrode 3. The current between the source 1 and the drain 2 in this case can be measured with high sensitivity. Charge holding is carried out by the polarization in the ferroelectric layer 6, and stored data can be held even if power supply is cut off.

Abstract: A memory cell array is constructed by a plurality of sub-arrays which include a plurality of sub-word lines, a plurality of bit lines, a plurality of plate lines and a plurality of memory cell blocks, plural ones of the sub-arrays being arranged in the sub-word line direction, a plurality of sub-row decoders provided between the plurality of respective sub-arrays, for driving the sub-word lines, a main row decoder disposed on one-end side of the plurality of sub-arrays in the sub-word line direction, and a plurality of main-block selecting lines for respectively supplying outputs of the main row decoder to the sub-row decoders. The main-block selecting lines for connecting the main row decoder to the sub-row decoders are formed of the same interconnection layer as the plate lines and metal interconnections used between the memory cells in the cell block.

Abstract: Addition of capacitance to the storage nodes of static random access memory cells and other types of integrated circuits substantially increases Qcrit and substantially eliminates soft errors due to alpha particles; susceptibility to which would otherwise increase as integrated circuits are scaled to smaller sizes and manufactured at increased integration densities. Formation of the added capacitance as deep trench capacitors avoids any constraint on circuit or memory cell layout. Degradation of performance is avoided and performance potentially improved by permitting alteration of proportions of pull-down and pass gate transistors in view of the increased stability imparted by the added capacitors. One of the capacitor electrodes is preferably shorted to the supply voltage through an impurity well. Thus, the memory cell size can be reduced while greatly reducing susceptibility to soft errors; contrary to the effects of scaling at current and foreseeable feature size regimes.

Abstract: A circuit configuration and a method for accelerating aging in an MRAM, in which additional circuit are provided in order to feed a higher current into a control line of a memory cell which is located nearer the soft-magnetic layer. A second transistor is inserted in parallel with the driver transistors, which form a first control unit. The second transistor supplies a current through the control line located nearer the soft-magnetic layer. The second transistor can drive a higher current through the control line and can be activated in a test mode.

Abstract: A device having a magneto-resistive element, a first conductor proximate to the magneto-resistive element, and a second conductor proximate to the magneto-resistive element. The magneto-resistive element is exposed to a magnetic field generated by a first electrical pulse carried by the first conductor. The magneto-resistive element is also exposed to a magnetic field generated by a second electrical pulse carried by the second conductor. The second electrical pulse is delayed relative to the first electrical pulse.

Abstract: An integrated circuit chip suitable for use in either a single chip packaged configuration or a multi-chip packaged configuration is disclosed. The chip has a conventional memory circuit portion and a control circuit portion. In operation as a single chip packaged configuration, the control circuit portion is inactive. In a multi-chip packaged configuration, the control circuit serves to prolong the activation of the currently addressed memory chip, while delaying the activation of the memory chip which is to be addressed in the next memory address cycle.

Abstract: First transistor rows are arranged, each including two transistors connected in series for selectively connecting any of memory cell rows to an input/output circuit. A switching transistor operates as a switch and a short transistor(s) each having a source and a drain shorted to each other function(s) as wiring. The first transistor rows are provided with a plurality of transistors in advance. Since there is no need to selectively form only such a transistor that is to be operated as a switch, there is no need to form ion-implanted regions for making a source and a drain per transistor. As a result, the spacing with which the transistors are arranged can be set without considering the layout rule of the diffusion layer regions. Since the transistors can be arranged closely, the layout area can be decreased and the chip size of the semiconductor memory can be reduced.

Abstract: A low-cost, novel electrically erasable programmable read only memory cell embedded on core complementary metal oxide silicon for analog applications. The EEPROM memory cell includes a first well of P-type conductivity. An N-well coupler region is formed within the first well of P-type conductivity. An N-well window region is formed within the first well of P-type conductivity and spaced apart from the N-well coupler region. A first P+type region formed within the N-well window region. A second P+type region formed within the N-well window region and spaced apart from the first P+type region. A first contact is used to couple a first bit line to the first P+type region. A second contact which is used to couple a second bit line to the second P+type region. A single polysilicon layer is disposed over the N-well coupler region and the N-well window region. This single polysilicon layer defines a floating gate of the electrically erasable programmable read only memory cell.

Abstract: A circuit structure for programming data in reference cells of an electrically programmable/erasable integrated non-volatile memory device includes a matrix of multi-level memory cells and a corresponding reference cell provided for comparison with a respective memory cell during the read phase. The reference cell is incorporated, along with other cells of the same type, in a reference cell sub-matrix which is structurally independent of the memory cell matrix and directly accessed from outside in the DMA mode. The bit lines of the sub-matrix branch off to a series of switches which are individually operated by respective control signals REF(i) issued from a logic circuit with the purpose of selectively connecting the bit lines to a single external I/O terminal through a single addressing line of the access DMA mode.