Abstract: A power supply apparatus for use in electroplating includes an input-side rectifier (32). A rectifier output is converted into high-frequency signals in inverters (38a, 38b), which are transformed in transformers (48a, 48b). When the transformed high-frequency signals from the transformers are of positive polarity, they are rectified by a diode (50a or 50b) to cause a positive current to be supplied to a load (60). When the transformed high-frequency signals are of negative polarity, they are rectified by a diode (50c or 50d) to thereby cause a negative current to flow through the load. A first IGBT (54a) is connected in series with each of the diodes (50a, 50b) and is rendered conductive and nonconductive at a frequency lower than the high-frequency signal. Also, a second IGBT (54b) is connected in series with each of the diodes (50c and 50d) and is rendered nonconductive when the IGBT and nonconductive at the lower frequency.

Abstract: An insulating-type switching electric power source device has an input voltage Vin of a primary side that is converted at an input/output ratio determined by switching operations of a switching device, and then is output. Voltage subjected to rectifying and smoothing by a primary-side rectification smoothing circuit is used as detecting signals of the output voltage, to control the time ratio of the switching device. A load regulation correcting circuit outputs load regulation correcting signals correlated with the amount of output current. A temperature compensating circuit corrects the load regulation correcting signals according to the ambient temperature. The load regulation correcting signals correct the output voltage detecting signals according to the fluctuations of the output voltage according to fluctuations in the output current and fluctuations in the ambient temperature.

Abstract: A switching power supply suitable for driving a load whose load current may fluctuate abruptly comprises a main circuit unit including a switching circuit for converting a DC input voltage to an AC voltage and an output circuit for rectifying the AC voltage to produce a DC output voltage, and a control circuit for controlling the operation of the main circuit unit, the transfer function of the control circuit assuming a first value when the load current supplied by the main circuit unit changes at a rate not exceeding a prescribed rate and assuming a second value exceeding the first value when the load current changes at a rate exceeding the prescribed rate. The switching power supply therefore exhibits markedly improved transient response when the load current changes at a rate exceeding the prescribed rate because the transfer function of the control circuit is increased relative to that under normal condition.

Abstract: A control system (20) for a power converter (22) designed to convert DC power from a source (30) such as a battery, flywheel or fuel cell into AC power. The control system includes an impedance current regulator (106) for providing an impedance current signal to a summing unit (110) where it may be combined with real and reactive current command signals provided from respective sources (62, 64). The resultant current signal provided by the summing unit is provided to a voltage correction unit (112) that uses the resultant current signal in developing a correction voltage signal provided to the power converter. The correction voltage signal contains information used by the power converter in adjusting the real and reactive currents in its output AC power based on the ability of the AC power network to accept changes in current.

Abstract: A rectifier/inverter power supply for use with induction heating or melting apparatus includes a tuning capacitor connected across the output of the rectifier and input of the inverter. The tuning capacitor forms a resonant circuit with an inductive load coil at the operating frequency of the inverter. Additionally, the load coil may comprise an active load coil connected to the output of the inverter and a passive load coil, in parallel with a resonant tuning capacitor, for an improved efficiency circuit.

Abstract: An apparatus for reducing power supply noise in the power supply system of a clock driver has been developed. The apparatus includes a clock driver with a power supply system connected to the clock driver and a shunting resistor connected across the power supply system in parallel with the clock driver.

Abstract: The present invention provides for an apparatus and corresponding method for controlling inrush current in an AC-DC power converter by providing a control circuit to limit inrush current efficiently during cold startup, warm startup, and power line disturbance conditions. The present invention controls inrush current without the need for an extra series lossy dissipative device and without causing undesirable voltage surges at the input of the DC-DC converter stage. The preferred embodiment includes use of the present invention for AC-DC converters having active power factor correction.

Abstract: The present invention utilizes a buffer to isolate a stack of memory devices, thereby taking advantage of the increased memory density available from stacked memory devices while reducing capacitive loading. A memory module in accordance with the present invention may include a stack of memory devices and a buffer coupled to the first and second memory devices and arranged to capacitively isolate the first and second memory devices from a bus. In a memory system in accordance with the present invention, multiple buffered stacks of memory devices are preferably coupled in a point-to-point arrangement, thereby further reducing capacitive loading.

Abstract: The method of forming a ferroelectric memory device includes forming capacitor patterns over a substrate, each capacitor pattern having an adhesive assistant pattern, a lower electrode, a ferroelectric pattern, and an upper electrode. An oxygen barrier layer is formed over the substrate and is etched to expose a sidewall of the ferroelectric pattern but not a sidewall of the adhesive assistant pattern. Then, a thermal process for curing ferroelectricity of the ferroelectric pattern in performed.

Abstract: A microelectronic programmable structure and methods of forming and programming the structure are disclosed. The programmable structure generally include an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying a bias across the electrodes, and thus information may be stored using the structure.

Abstract: A microelectronic programmable structure suitable for storing information and a method of forming and programming the structure are disclosed. The programmable structure generally includes an ion conductor and a plurality of electrodes. Electrical properties of the structure may be altered by applying energy to the structure, and thus information may be stored using the structure.

Abstract: A NAND cell unit comprising a plurality of memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in the erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of any selected one of the memory cells, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

Abstract: At the data programming time, data of a plurality of bits are transformed by a data transforming logic circuit into data (multi-value data) according to the combination of the bits, and the transformed data are sequentially transferred to a latch circuit connected to the bit lines of a memory array. A program pulse is generated according to the data latched in the latch circuit and is applied to a memory element of a selected state correspondingly to the multi-value data. At the data reading operation, the states of the memory elements are read out by changing the read voltage to intermediate values of the individual threshold values and are transferred to and latched in a register for storing the multi-value data, so that the original data may be restored by a data inverse transforming logic circuit on the basis of the multi-value data stored in the register.

Abstract: At the data programming time, data of a plurality of bits are transformed by a data transforming logic circuit into data (multi-value data) according to the combination of the bits, and the transformed data are sequentially transferred to a latch circuit connected to the bit lines of a memory array. A program pulse is generated according to the data latched in the latch circuit and is applied to a memory element of a selected state correspondingly to the multi-value data. At the data reading operation, the states of the memory elements are read out by changing the read voltage to intermediate values of the individual threshold values and are transferred to and latched in a register for storing the multi-value data, so that the original data may be restored by a data inverse transforming logic circuit on the basis of the multi-value data stored in the register.

Abstract: Memory devices having multiple bit line column redundancy are suited for high-performance memory devices, with particular reference to synchronous non-volatile memory devices. Such memory devices include blocks of memory cells arranged in columns with each column of memory cells coupled to a local bit line. Such memory devices further include global bit lines having multiple local bit lines selectively coupled to each global bit line, with each global bit line extending to local bit lines in each memory block of a memory sector. Repair of one or more defective columns of memory cells within a sector is effected by providing a redundant grouping of memory cells having a redundant sense amplifier, global bit lines and local bit lines. Each grouping of memory cells contains four or more columns of memory cells. A defect in one column of memory cells results in replacement of four or more columns of memory cells.

Abstract: An internal data processing apparatus and method in a mobile station. A NOR flash memory is replaced with a NAND flash memory as a memory for storing internal data, and a modem is interfaced with the NAND flash memory.

Abstract: A source biasing circuit for providing a negative biasing voltage to an electrically-erasable, programmable read-only memory (EEPROM) circuit during a read or programming operation. The negative biasing voltage helps overcome the source line resistance that would otherwise require a larger number of metal lines. The smaller number of metal lines required when using the source biasing circuit allows the EEPROM to be made smaller.

Abstract: A Flash memory that stores data, code, and parameters and performs parallel operations employs uniform-size blocks in array planes. The Flash memory includes separate internal read and write paths connected to multiple array planes to permit a read in one array plane during a write in another array plane, further a third array plane can erase a block during the read and write operations. The uniform size, which permits a symmetric layout, is selected for efficient storage of parameters to provide maximum flexibility in allocation of storage. A redundancy system for the Flash memory uses a CAM and a RAM for address comparison and substitution when replacing addresses corresponding to defective memory elements. The uniform block size allows block replacement where spare blocks in the array planes replace defective blocks.

Abstract: A data write circuit is interposed between a CPU and memory, both of which operate based on the same number of bits (e.g., thirty-two bits). The CPU produces address data for designating a specific address in the memory, and access mode designation data for designating one of a byte access mode, half-word access mode, and word access mode. The data write circuit comprises a decoder for decoding the access mode designation data, a logic circuit for generating selection signals, and four selectors, each of which deals with 8-bit data consisting of eight prescribed bits of the original thirty-two bits. Each selector selects either first data read from the memory or second data output from the CPU. Therefore, each selector is capable of selecting the second data, which are substituted for the first data in the memory. Thus, it is possible to perform write operations in desired units in the memory.

Abstract: A semiconductor memory device has a memory cell array including memory cells; a reference current generating circuit which generates a reference current; a reference voltage generating circuit which generates a reference voltage in a reference node on the basis of the reference current generated by the reference current generating circuit; a first sense circuit which generates an output current on the basis of a cell current of the selected memory cell and which generates a data potential in a sense node on the basis of the output current and the reference current; and a second sense circuit which detects the data held in the selected memory cell by comparing the data potential in the sense node with the reference voltage in the reference node.

Abstract: An internal voltage generator for memory bank peripheral circuitry, a semiconductor memory device having the internal voltage generator, and a method for generating an internal voltage are provided. A switchable internal voltage generating circuit according to the present invention includes a control section and an internal voltage generating circuit. The control section generates a control signal in response to a bank activation command and a bank activation signal for enabling memory banks. The internal voltage generating circuit receives a reference voltage, and responds to the control signal to output an internal voltage equal to the reference voltage. The control signal is enabled when the bank activation command and the bank activation signal are concurrently enabled. The bank activation signal is generated in response to a bank address.

Abstract: A signal generator for generating a kickb signal used to reset a boost signal used to operate a memory device. The signal generator includes an address detector that receives one or more address lines and a clock signal to produce a detector output. A switch circuit is also included that receives the detector output, the clock signal and a feedback signal to produce a switch output. A delay circuit is coupled to receive the switch output to produce a delayed switch output, and an output circuit is coupled to receive the switch output and the delayed switch output to produce the kickb signal, where the kickb signal forms the feedback signal.

Abstract: A method is provided for generating a data strobe signal in order to transmit the latter through a signal line with tristate behavior from/to a semiconductor memory module for writing/reading data to/from the semiconductor module. The data strobe signal, in response to the outputting or the reception of a read/write command, proceeding from the tristate state, is clocked with a predetermined clock frequency after a short preamble period. The data strobe signal is occupied, in the preamble period, by one or more pulses corresponding to the clock frequency. In very fast memory systems, this avoids a temporal offset between a system clock and data acceptance controlled by data strobe signal pulses. A semiconductor circuit configuration having a semiconductor circuit module with a circuit for generating such a data strobe signal, is also provided.

Abstract: A DRAM includes a test mode circuit. Test mode circuit generates respective test mode signals of an L level and an H level by detecting first and second power supply voltages in response to first and second test mode shift signals, respectively. A control circuit controls peripheral circuits to input and output data for executing a special test to and from a plurality of memory cells in response to receiving of the test mode signals of an L level and an H level. Consequently, a semiconductor memory device can enter the test mode in a module.

Abstract: An electrically programmable and erasable memory includes memory cells, with each memory cell including a floating gate transistor and an access transistor. The floating gate transistor has a first terminal connected to the access transistor. The memory includes circuitry for respectively applying during an erasing phase a first signal, and a second signal on the control gate and on a second terminal of the floating gate transistors of the memory cells to be erased. The circuitry also applies to the gates of the corresponding access transistors of the memory cells to be erased a signal having a voltage that is different from a voltage of the first signal and has a low or zero potential difference with respect to a voltage of the second signal. The memory is protected against the effects from a breakdown of the gate oxide of an access transistor.

Abstract: The cancellation of a redundant element of an integrated circuit with a cancel bank is disclosed. In one embodiment, a fuse or antifuse bank is coupled to the redundant element and permanently programmed to respond to the address of a defective primary element. If the redundant element is found to be defective, the fuse or antifuse bank is canceled, and a result the redundant element is also canceled. A cancel line of the fuse or antifuse bank, along with the cancel line of each of a plurality of other fuse or antifuse banks, is coupled to a cancel bank. The cancel bank comprises a multiplexer and a plurality of cancel antifuses less in number than the number of fuse or antifuse banks. The cancel antifuses are selectively enabled such that the fuse or antifuse bank coupled to the defective redundant element may be canceled.

Abstract: A memory cell comprising an inverting stage, an access transistor coupled between a data line and an input of the inverting stage, the access transistor being responsive to a control signal for selectively coupling the data line and the inverting stage input, a feedback transistor coupled to the inverting stage input and being responsive to an output of the inverting stage for latching the inerting stage in a first logic state and whereby the cell is maintained in a second logic state by a leakage current flowing through the access transistor which is greater than a current flowing through the feedback transistor.

Abstract: Ortho-sulfonamido aryl hydroxamic acids are provided which are useful, inter alia, for the inhibition of matrix metalloproteinases and the treatment of conditions associated with overexpression of MMPs.

Abstract: An integrated circuit that is capable of being burn-in tested with an AC stress and a testing method using the same are provided. The integrated circuit includes an address transforming means and a data generating means. The address transforming means transforms the addresses of the memory device selected and generates an address signal responsive to a clock signal. The data generating means generates a data signal that alternates between a first state and a second state responsive to the clock signal and provides the data signal to the selected memory device. The integrated circuit includes a switch for coupling the test supply line to the normal supply line during testing and intercepting the test supply line from the normal supply line during normal operations responsive to a control signal. The integrated circuit of the present invention allows a wafer burn-in test by sequentially and repeatedly applying the AC stress to all the memory devices.

Abstract: A sense amplifier adapted to sense an input signal on global bitlines, having an amplifier offset cancellation network and an offset equalization network. The amplifier offset cancellation network mitigates an inherent offset signal value, a dynamic offset signal value, or both, yet produces a residual offset signal value, which is substantially eliminated by the offset equalization network. The sense amplifier also can include an isolation circuit to isolate the sense amplifier from the corresponding global bitlines when the sense amplifier is unused. Also, a charge-sharing circuit is used to share charge between the bitlines when the sense amplifier is activated, thus producing a limited voltage swing on the bit lines. The sense amplifier uses an amplifier offset cancellation network having multiple precharge-and-balance transistors, and an offset equalization network having at least one balancing transistor.

Abstract: In an FCRAM having a late write function, when a first command signal indicates “write active”, whether a write operation or an auto-refresh operation is to be performed is determined on the basis of a second command signal. For example, when the second command signal indicates “write”, a write operation for a memory cell is performed by a late write scheme. When the second command signal indicates “auto-refresh”, an auto-refresh operation is performed. In the last write cycle of a write operation immediately preceding this auto-refresh operation, addresses for selecting a memory cell as an object of auto-refresh are predetermined. After data write to a memory cell is completed in the last write cycle, row precharge for auto-refresh is performed. After that, an auto-refresh operation (i.e., a data read operation and a data restore operation) is performed for the selected memory cell.

Abstract: A decoder providing asynchronous reset, redundancy, or both. an asynchronously-resettable decoder with redundancy. The decoder has a synchronous portion, responsive to a clocked signal; an asynchronous portion coupled with an asynchronous circuit; a feedback-resetting portion, which substantially isolates the synchronous portion from the asynchronous portion coupled with, and interposed between the synchronous portion in response to a asynchronous reset signal; a signal input; a first memory output coupled with a first memory cell group; a second memory output coupled with a second memory cell group; and a selector coupled between the signal input, the first memory output, and the second memory output. This decoder can be memory row-oriented, and thus provide an asynchronously-resettable row decoder with row redundancy, or an asynchronously-resettable column decoder with column redundancy.

Abstract: The present invention provides a read-only memory array having a flat-type structure. The read-only memory array comprises at least two memory banks having a plurality of memory cells. At least two inter-bank transistors are coupled to the two memory banks and shared by the two memory banks. Each inter-bank transistor is used for enabling to select the memory cells of the two memory banks. At least a contact commonly is coupled to the two memory banks through the two inter-bank transistors.

Abstract: A memory device comprises an array of memory elements (15) overlying driver cells (3). Vias (21) connect the driver cells (3) to the memory elements (15). The vias are distributed over the area of the array to connect the driver cells (3) to the row and column conductors (9, 13) of the memory array.

Abstract: An N-bit wide synchronous, burst-oriented Static Random Access Memory (SRAM) reads out a full N bits simultaneously from its array in accordance with an address A0 into N latched sense amplifiers, which then sequentially output N/X bit words in X burst cycles. Because the SRAM's array reads out the full N bits simultaneously, the array's address bus is freed up to latch in the next sequential address A1 so data output continues uninterrupted, in contrast to certain conventional SRAMs. The SRAM also writes in a full N bits simultaneously after sequentially latching in N/X bit words in X burst cycles into N write drivers. This simultaneous write frees up the array's address bus to begin latching in the next sequential address A1 so data input continues uninterrupted, again in contrast to certain conventional SRAMs.

Abstract: A livestock mixer and feeder apparatus operates efficiently to minimize the time and facilities necessary to service a modest feedlot. The large mixing chamber utilizes a vertical auger operating at high speed to quickly perform the mixing procedure and is run by a high power hydraulic motor. A moveable base, such as a pickup, supplies the need power-take-off capability and produces efficient feedlot operation, since the apparatus can be quickly loaded and unloaded. Prudent sized inlet and outlet augers complete the apparatus and are also powered by hydraulic motors.

Abstract: An impeller assembly is mountable onto a rotatable shaft that has a flange extending radially from the shaft and rotating with the shaft. The impeller has at least one blade pair member having two opposed blades and central hub portion having a hole therethrough with an inner diameter at least as large as the outer diameter of the shaft, a plurality of corresponding mounting holes provided in each of the flange and the blade pairs, and a plurality of bolts for fastening the blade pair to the flange via the mounting hole.

Abstract: A system is provided having a transmitting transducer for transmitting a burst of energy in response to an electrical drive waveform. The system includes a receiving transducer for generating an electrical signal in response to arrival of the transmitted burst of energy.

Abstract: The invention provides a microphone/sensor, including a housing defining a chamber and having an opening; at least one pair of optical waveguides, each having a input end portion and an output end portion, the input end portion of a first waveguide being optically coupled to a source of light and the output end portion of a second waveguide being optically coupled to a light intensity detector; a membrane having two opposite surfaces extending across the opening to form a sealed-off chamber inside the housing; a head, including the input end portion of the second optical waveguide and the output end portion of the first optical waveguide, affixedly located at least in proximity to each other, each of the output end portion of the first waveguide and input end portion of the second waveguide having an optical axis and an output face, the output face being cut at an angle &thgr; with respect to the axis, the axes forming an angle &agr; between them, wherein, upon operation, the light emerging from the output en

Abstract: There is provided a fiber-optic hydrophone having a compliant sensing mandrel coaxial with and adjacent to a rigid reference mandrel. A first optical fiber is wound around the compliant sensing mandrel and a second optical fiber is wound around the reference mandrel. The first and second optical fibers comprise different arms of an interferometer. Flexible sealing members, such as O-rings, seal the compliant sensing mandrel to the hydrophone. One O-ring is disposed near each end of the sensing mandrel. A cylindrical support member is disposed inside the sensing mandrel. At least a portion of the support member is spaced from the sensing mandrel so as to provide a sealed cavity between the sensing mandrel and the support member. The sealed cavity is filled with air or similar compliant substance.

Abstract: A combination clock and art set apparatus, including a clock face having a plurality of elements arranged to mark at least one time interval, and clock hands arranged for movement relative to the elements and one another to indicate a time. At least one element or at least one hand includes an artist's implement. In an embodiment, at least one element or at least one hand can be removably secured to the face. In another embodiment, the apparatus includes a pair of adjustable straps that can be used to secure the apparatus to a back of a person.

Abstract: An alarm clock is shaped as a miniature slot machine. The alarm is set by pulling the handle forward, just as one activates a real slot machine. When the alarm goes off, the wheels spin and stop one at a time on a jackpot combination, accompanied by the sound one would hear from a real slot machine. A light on top of the machine flashes, accompanied by sound that mimics the sounds of a jackpot on a real slot machine. The snooze alarm is set by pushing the handle to the rear.

Abstract: To provide a case, a strap and a timepiece for preventing rotation of the strap. A roof rear face recessed portion is formed at a roof rear face of a strap attaching portion of a timepiece case. A strap is formed with a rotation stop projection at a rotation stop face of the strap opposed to the roof rear face recessed portion. The case, the strap and the timepiece having a strap rotation stop structure by respectively engaging the recessed portion and the projected portion.

Abstract: A magneto-optical disk recording and reproducing device, which carries out recording and reproducing for a magnetic super-resolution magneto-optical disk including a recording layer and reproducing layer, has a recording data processing circuit which records long recording marks at different positions between adjacent tracks in a radius direction, each of the long recording marks being larger in diameter than an aperture formed on the reproducing layer by projecting thereon the light beam. According to this arrangement, it is possible to continuously reproduce a data recording area with high accuracy and optimum reproducing power without being affected by adjacent tracks.

Abstract: There is disclosed apparatus for moving an optical element in an opto-mechanical system, comprising at least one circularly symmetric flexure surrounding said optical element, and means for moving said optical element along an axis perpendicular to and extending through the centre of said at least one flexure. A number of flexures may be provided in a stack with spacers therebetween, and the optical element may be mounted in a tubular member support by two paced apart stacks. Means are also provided for damping end of movement vibrations.

Abstract: An optical pickup device includes an irradiating optical system for converging a light beam to form a spot on a recording surface via a light-transmitting layer of an optical recording medium, and a photodetection optical system for converging return light reflected and returned from the spot on a photodetector. The device detects wave aberration and focal error of the light beam. A diffractive optical element is disposed on the optical axis of return light in the photodetection optical system and provided with an annulus. The diffractive optical element annularly extracts, from return light, ray components in the vicinity of a predetermined radius on a pupil on the emitting pupil surface of the irradiating optical system, which is affected by the wave aberration generated in the optical system.

Abstract: The invention provides a method of adjusting a tracking location in an optical storage device. The method is illustrated as follows. Firstly, the optical pickup head reaches the first tracking location according to a tracking error (TE) signal. Secondly, the optical pickup head is finely moved to an adjusted tracking location where the value of the amplitude of RFRP signal is maximum. The method can avoid wrong tracking location by simply based on the TE signal, then enable the optical pickup head to reach the correct track center and improve the quality of data reading.

Abstract: An optical disc system includes a photo detector circuit of an optical disc drive and a signal processing system. The photo detector circuit is configured to generate at least one information-carrying signal from an optical disc assembly. The signal processing system is coupled to the photo detector circuit to obtain from the at least one information-carrying signal both operational information used to operate the optical disc system and data indicative of presence and/or characteristics of an investigational feature associated with the optical disc assembly. Methods and discs for imaging a biological or medical investigational feature are also provided.

Abstract: In the data recording method for an optical recorder/player, data and start address information for recording the data are received, and an optimum power control (OPC) is performed in a data recording region of an optical recording medium corresponding to the start address. A laser recording power suitable for recording the received data in the data recording region corresponding to the start address is set based on the OPC, and the received data is recorded in the data recording region corresponding to the start address using the set laser recording power.

Abstract: In an optical recording/reproducing method and apparatus of the present invention, a modulation parameter is calculated for each of reproduced data signals, each modulation parameter corresponding to one of respective recording powers. An optimum recording power is determined based on a relationship between the modulation parameters and the recording powers, wherein a sequence of pairs of the modulation parameter and the recording power is selected, a gamma, which defines a ratio of a change of the modulation parameter to a change of the recording power, is calculated for each of the selected pairs, and a target recording power corresponding to the optimum recording power is found based on a function derived from a relationship between the calculated gammas and the respective recording powers, the target recording power causing a value of the function to be equal to zero.