Abstract: Disclosed are a system and method of selectively awaking processes in response to an interrupt condition. A processing system may host a plurality of processes where each process is associated with an event causing an interrupt condition at a device. When a process transitions to a sleeping state, an identifier of the process may be associated with an address in a data structure. In response to an event at the device causing an interrupt condition, an interrupt service routine may associate data received from the device with the identifier in the data structure to locate the sleeping process. The located process may then be awakened while maintaining other sleeping processes associated with other events in a sleeping state.

Abstract: An apparatus and method for extending a bus to support at least one auxiliary function. A filter may intercept and route a signal issued over the bus. The filter may comprise control logic for reading the intercepted signal and for determining a destination therefor. The filter may also comprise a multiplexer operatively associated with the control logic for reissuing the intercepted signal to the destination. When the intercepted signal is designated as function-specific, the multiplexer reissues the intercepted signal to one of the at least one auxiliary function. When the intercepted signal is designated as device-specific, the multiplexer reissues the intercepted signal over the bus to a peripheral device.

Abstract: A module is provided for installation in a drive bay of a computer and is adapted to accommodate expansion circuitry rather than the electromechanical devices conventionally installed in drive bays. A system interface board is provided for insertion into an expansion socket on the computer's motherboard and is connected to the module, thus interfacing the expansion circuitry to the computer. The expansion circuitry can be greater in volume and is more accessible and more easily cooled than expansion circuitry installed in expansion sockets on the motherboard.

Abstract: A high-density system includes a plurality of system units. Each system unit includes a backplane and a plurality of central processing unit (CPU) cards plugged into the backplane. Each backplane has a servicing input/output (I/O) bus for carrying servicing I/O data. Each central processing unit (CPU) card is plugged into the corresponding backplane and capable of accepting data from the servicing I/O bus or sending data to the servicing I/O bus. The high-density system further includes at least one cable for connecting the servicing I/O busses of the system units so as to transfer the servicing I/O data, and a servicing control system. The servicing control system includes a switching system for selectively connecting only one of the CPU cards in the high-density system to the servicing I/O bus, and an I/O interface module electrically connected to the servicing I/O bus. The I/O interface module has at least a port to which an external device may be plugged.

Abstract: A silicon disk drive with few slots for plural disks capable of being built in or externally connected with a main frame of a computer or any digital product, it satisfies the requirements of consumers of various groups of people by the function of reading and writing silicon disks (portable memory cards). The silicon disk drive provides a slot to suit insertion of SM, MM, MS and SD cards, and provides another slot to suit insertion of Type I, Type II or Type I CF card, or Type II or Type III PCMCIA card, in this way, data in the files of any of the above silicon disks can be read and written. And it can be assisted with provision of the design of the IDE/ATAPE, USB or 1934 delivery unit, in order that the silicon disk drive having a single slot or two slots not only for reading and writing on and for insertion of the now available silicon disks, but also for solving the long pending problems of confusing, misleading and being subjected to damage of the conventional techniques with more than three slots.

Abstract: Methods and apparatus are provided for hot swapping a hard disk drive. A gateway is connected between the disk drive and the bus leading to the host adapter. The gateway can isolate the disk drive from the bus prior to a disk drive being removed and can signal to the host adapter when a new drive has been installed. The gateway can de-isolate the newly installed disk drive from the bus to allow the host adapter to communicate with the newly installed disk drive. Additionally, the gateway can remove system power from a disk drive being removed and ramp up power to a newly installed disk drive while system power is uninterrupted for other components of the computer system. An adapter may be provided to connect a disk drive to the gateway, and the gateway and the adapter engage and/or disengage during the hot-swapping of the disk drive.

Abstract: Methods and apparatus are provided for suspending communications with a hard disk drive in order to transfer data relating to the hard disk drive between the host and an intermediate communications gateway, thereby isolating the hard disk drive from the bus while this data is transferred. The data transferred between the host and the intermediate communications gateway may include control signals transferred from the host to the intermediate communications gateway and status signals transferred from the intermediate communications gateway to the host. In one embodiment, normal communications with an IDE hard disk drive are suspended upon the assertion of the RESET line of the AT bus. As such, the state of the RESET line may be controlled such that the RESET line is no longer merely utilized as a system reset but, instead, is used to define the state of communications between the host and the hard disk drive.

Abstract: Systems are provided for the offloading of protocol control and conversion information within microprocessor-based systems. A converter controller comprises a first interface and protocol, as well as a second interface and protocol. An intermediate protocol and interface is interconnected to both the first protocol and the second protocol, and forwards or offloads protocol information to the system CPU, which comprises device driver information for protocol conversion and/or control. The CPU acts upon the received protocol information, performs protocol conversion as necessary, and forwards the converted protocol information back to the converter controller through the intermediate interface. Some embodiments of the offloading protocol conversion system comprise a SDIO controller within a USB-based device.

Abstract: A novel method and interface is provided for conducting read data transfers between an initiator device on a single-transaction bus and a target device on a split-transaction bus. Embodiments of the present invention permit the initiator device to “post” a read request for a specified amount of data from a specified address on the split-transaction bus to an interface that resides between the single-transaction bus and the split-transaction bus. The requested read data is then retrieved over the split-transaction bus and presented in a high-speed memory within the interface for direct access by the initiator device over the single-transaction bus. Latency is avoided because the initiator device is not required to wait for the emergence of the requested read data from the split-transaction bus but, instead, may continue to perform other activities on the single-transaction bus and then obtain the requested read data at a later time.

Abstract: A mechanism for initiating and completing one or more I/O transactions using channel and memory semantic messages is disclosed. Channel semantic messages are messages that are simply packetized and transmitted. Memory semantic messages are transmitted by means of a remote direct memory access (RDMA) operation; they are more akin to a memory copy than the simple transmission of a message.

Abstract: A circuit comprising a storage circuit and a control circuit. The storage circuit may be configured to store one or more message frames received from a first bus and a second bus in one or more memory locations in response to one or more signals. The control circuit may be configured to store and access the one or more signals, wherein the signals are presented to the storage circuit through the first or the second bus such that management overhead of the first or second bus is reduced.

Abstract: A method and system are provided for determining the identity of computer peripheral devices that are coupled to a computer or network communication system in a daisy chain configuration. The computer includes a first switch. Each of the plurality of computer peripheral devices includes a bypass board having a second switch thereon. The method includes: (a) opening the first switch and the second switches; (b) closing the first switch; (c) detecting a short circuit formed between the computer and each one of the plurality of computer devices; and (d) identifying one of the peripheral computer devices which detects the short circuit as the first identified peripheral computer device. A method and system is also provided for sharing resources in a computer system, which includes a computer and peripheral computer devices.

Abstract: In a computer or microprocessor-based system having a plurality of resources making memory requests of a plurality of banks of memory, a switch-based interconnect system allows multiple simultaneous connections between resources and memory banks, maximizing memory throughput and bandwidth concurrency. The invention is particularly useful in devices having embedded banks of memory, where there are no external constraints requiring use of a bus architecture, but can be used with discrete devices as well.

Abstract: It is the object of the invention to supply an integrated circuit that contains a processor and at least one module and provides registers required for the modules as well as access to these registers. By concentrating the required registers according to the invention in a central register bank, which like the processor and the modules is connected to a fast AMBA-AHB bus, several advantages are achieved: for one, faster access is possible to each register. For another, the placement of the registers and the routing for the registers is simplified. This in particular allows chip area to be saved, which leads to cost savings in manufacture and enables higher component density. Furthermore, a slow AMBA-APB bus has now become optional.

Abstract: The present invention provides a data storage system, method and computer program product having an active data store and a data communication mechanism comprising a unified container layer for validating both externally-generated data and data generated within the active data store, wherein the unified container layer transmits and receives data using the data communication mechanism. In a preferred embodiment, the active data store is an entity-relationship-attribute data store which comprises a relational database. The unified container layer may validate data using a syntax checker and a semantics checker, which may comprise a rules engine. Preferably, the data communication mechanism is one of a publish/subscribe system, a synchronous communication system, and an asynchronous communication system.

Abstract: In order to preclude unauthorized access to a memory, for example after testing, two EEPROM cells are programmed and their outputs are subjected to a logic operation, the result being stored in a memory element and being evaluated. The cells are arranged in such a manner that they are programmed together in anti-parallel. A well-defined initial condition before a test is established by changing the control gate voltage, which causes both cells to be set to an initial state with similar output signals. The initial state is stored in the storage element and is evaluated. It is not until the initial condition has been established that the EEPROM cells are programmed and the correct programming is tested.

Abstract: A memory system that reduces the number of memory cells programmed in a memory array is provided. A logic comparator determines whether more than half of the bits of a write data word require a program operation. If so, the logic comparator provides a status signal having a first state. A status signal having the first state causes the inverse of the write data word to be written to the memory array, along with the status signal. If the status signal does not have the first state, the write data word is written to the memory array, along with the status signal. During a read operation, a data word and corresponding status signal are read from the array. If the status signal has the first state, the inverse of the data word is provided as a read data word. Otherwise, the data word is provided as the read data word.

Abstract: The described technique emulates a disk drive on flash memory, and avoids storing allocation data structure on flash memory. A device driver is provided for a flash memory device, and the device driver maintains a linked list of sector caches. The use of a list of sector caches enables one to minimize erases and thus flash memory life, as well as speed up write operations to the flash memory device. Heuristics are used to detect the sectors that hold critical meta-data information and give preferential treatment to the corresponding cached sectors. The number of sector caches available to the device driver is configured depending on the memory available in the system.

Abstract: Bit inversions occurring in memory systems and apparatus are provided. Data is acquired from a source destined for a target. As the data is acquired from the source, the set bits associated with data are tabulated. If the total number of set bits exceeds more than half of the total bits, then an inversion flag is set. When the data is transferred to the target, the bits are inverted during the transfer if the inversion flag is set.

Abstract: A system and method for enabling flash memory systems to support flash devices with pages that are larger than operating system data sector sizes, while not violating the device's specifications, and also optimizing performance. According to the present invention, the writing logic of a flash memory system must take into account the PPP limitations and page size of the device during sector write operations. The PPP influences the decision when to simply write the new data, and when to allocate a new page and copy previously existing data to the new page. According to the present invention, when a page contains more than one sector, the software makes the standard translation into physical address, but after finding the address, it examines the page containing that address, and counts the number of other sectors within the same page already containing data.

Abstract: A processing system allows data downloads from a non-volatile memory to volatile memory. The non-volatile memory device includes a decompression engine to decompress the data prior to storing in the volatile memory. This built-in decompression circuit allows an increased amount of data to be stored in the flash. The compression operation is performed prior to initial storage in the flash memory.

Abstract: A processing system allows direct data downloads from a non-volatile memory to a volatile memory. During a power-up operation, the volatile memory requests a direct transfer of data from the non-volatile memory. Bypassing a communication bus to a processor, the direct transfer allows for a faster transfer to the volatile memory. Power and capacitive bus loading are also reduced. Once the volatile memory is loaded, a system reset signal is provided from the volatile memory to indicate that the memory is ready.

Abstract: A method and apparatus for refreshing data in a flash memory device is disclosed. A counter is maintained for each memory block. When a memory block is erased, the counter for that erase block is set to zero while the remaining counters are incremented. When a memory block counter reaches a predetermined threshold value, the associated memory block is refreshed.

Abstract: A lookup mechanism provides an input value to a datapath element disposed in an execution datapath of a processor and causes the datapath element to compare the input value to stored identifier values. The lookup mechanism receives from the datapath element a result based on the comparison.

Abstract: When only one type of a memory having an access rate necessary for high-speed data processing is equipped with a subsystem so as to accommodate the entire amount of storage required for the subsystem, a considerable rise in costs occurs. Therefore, in order to keep the rise in cost to a minimum, high-speed memory of a storage capacity required for the high-speed processing and low-speed memory of a storage capacity that can be safely employed for low-speed processing are both equipped with the disk memory system. With this arrangement, the rise in costs can be kept to a minimum, and access time to the memory can be reduced. The performance of the disk memory system can be thereby improved.

Abstract: A storage array comprised of a number of storage drives is provided with a controller to control zero initialization of the storage drives. The zero initialization involves writing zeros to all the storage drives in the array before user data or other information is written thereto. Each storage drive has a priority associated with accessing and using a bus subsystem that provides the communication link between the array of storage drives and the controller. A number of write operations are conducted during the zero initialization process to each storage drive in the array. A first write operation is performed by each storage drive before a second write operation is performed. Substantially equal usage ofthe bus subsystem by all the storage drives in the array is achieved in order to fully utilize the available bandwidth of the bus subsystem and reduce the time required to complete the zero initialization.

Abstract: In a storage system, a plurality of logical disks are constituted by combining a plurality of physical disks. A logical disk management unit converts input/output (I/O) requests addressed to the logical disks into I/O requests addressed to corresponding physical disks, and outputs the converted I/O requests. A physical disk management unit accesses the corresponding physical disks in accordance with the I/O requests which are output from the logical disk management unit and addressed to the physical disks. A logical disk relocation control unit relocates the logical disks so as to set the busy rates of the physical disks within a range between the first state in which the ratio of the busy rates of the physical disks is equal to the ratio of the I/O processing performance values of the physical disks, and the second state in which the busy rates of the physical disks are leveled. A data relocation method is also disclosed.

Abstract: There is provided a memory system on a chip. The memory system includes a configurable memory having a first mode of operation wherein the configurable memory is configured as a cache and a second mode of operation wherein the configurable memory is configured as a local, non-cache memory. A selection of any of the first mode of operation and the second mode of operation is capable of being overridden by an other selection of an other of the first mode of operation and the second mode of operation. The configurable memory may be configured at manufacture time, at burn-in time, and/or during program execution. Moreover, an access mode of the configurable memory may be determined from an address corresponding to a memory access instruction.

Abstract: An apparatus and method to de-allocate data in a cache memory is disclosed. Using a clock that has a predetermined number of periods, the invention provides a usage timeframe information to approximate the usage information. The de-allocation decisions can then be made based on the usage timeframe information.

Abstract: Method and apparatus for conditioning program control flow on the presence of requested data in a cache memory. In a data processing system that includes a cache memory and a system memory coupled to a processor, in various embodiments program control flow is conditionally changed based on whether the data referenced in an instruction are present in the cache memory. When an instruction that includes a data reference and an alternate control path is executed, the control flow of the program is changed in accordance with the alternate control path if the referenced data are not present in the cache memory. The alternate control path is either explicitly specified or implicit in the instruction.

Abstract: A streamlined cache coherency protocol system and method for a multiple processor single chip device. There are three primary memory unit (e.g., a cache line) states ( modified, shared, and invalid) and three intermediate memory unit pending states. The pending states are used by the present invention to prevent race conditions that may develop during the completion of a transaction. The pending states “lock out” the memory unit (e.g., prevent access by other agents to a cache line) whose state is in transition between two primary states, thus ensuring coherency protocol correctness. Transitions between states are governed by a series of request and reply or acknowledgment messages. The memory unit is placed in a pending state while appropriate measures are taken to ensure access takes place at an appropriate time. For example, a modification occurs only when other agents can not access the particular memory unit (e.g., a cache line).

Abstract: Shared memory provides buffering and switching for all frames that flow through a fiber channel switch. Received frames are written to shared memory by the receiving port then read from shared memory by the transmitting port. Shared memory provides for data to be written to a buffer at one rate, and read from a buffer at a different rate, or vice versa.

Abstract: A method and apparatus for recovering data from a failed disk drive in a disk drive array. The method and apparatus includes storing data on an array of disk drives by dividing extents of data into data segments and defining a parity group including at least one data segment from a plurality of data segments from different extents. Parity segments are generated from the data segments in the parity group and stored in the parity group. Furthermore, a second parity segment is generated from the parity segments and storied with the parity group. The method and apparatus then outputs data in realtime to users in a normal disk access mode from parity groups without the failed disk drive, and outputs recovered data in realtime to the users in a parity correction mode from the parity group containing the failed disk drive.

Abstract: A hierarchical memory access control distinguishes between blocks of data that are known to be sequentially accessed, and the contents of each block, which may or may not be sequentially accessed. If the contents of a block are provided in a sequential manner within the block, but the sequence does not correspond to a higher-level sequence, due to a non-zero offset in the start of the sequence within the block, the memory access control is configured to optimize the use of available memory by signaling when the within-block sequence corresponds to the higher-level sequence. While the within-block sequence differs from the higher-level sequence, access to the buffer is limited to the higher-level partitioning of the buffer. When the within-block sequence corresponds to the higher-level sequence, access to the buffer is provided at the within-block partitioning of the buffer.

Abstract: A computing system having a processor with a data/control bus interface. A data/control bus implements one or more device communication channels. A data memory is coupled to the processor and a mass storage device having an interface for communicating mass storage transactions is provided. A controller having a memory interface is coupled to the data memory and a mass storage interface coupled to the mass storage device's interface and operable to conduct mass storage transactions between the data memory and the mass storage device.

Abstract: New techniques for generating entries in a content addressable memory (CAM) capable of comparison operations such as “greater than” and “less than” decisions are described. The techniques can be used with binary or ternary CAMs. The number of CAM entries needed to implement such decisions is drastically reduced for both binary and ternary CAMs. In the case of binary CAMs, one or multiple searches are needed to perform the comparisons, while in the case of ternary CAMs a tradeoff between the number of CAM entries and the number of searches can be found. As an example, a method of classifying data networking packets is implemented using the new techniques. A packet classifier based on subfields of a packet header is also described.

Abstract: A method of interleaving a first bank of memory with a second bank of memory. The method is executed by a computer system having a memory controller that is coupled to a first plurality of memory devices that contains the first bank and a second plurality of memory devices that contains the second bank. The method includes: configuring the memory controller so that the memory controller is operable to read even and odd bytes of data from and write even and odd bytes of data to the first bank; storing even and odd bytes of data in the first bank; transferring the odd bytes of data from the first bank; and then reconfiguring the memory controller so that the memory controller is operable to read only even bytes of data from and write only even bytes of data to the first bank and the memory controller is operable to read only odd bytes of data from and write only odd bytes of data to the second bank.

Abstract: This invention is intended to make it unnecessary to introduce a backup-dedicated unit by utilizing a storage area provided in an existing computer (a POS unit, in particular), to compact, distribute and store backup data by introducing an encoder and a decoder to compact and expand data, and to also introduce a restore mechanism. After a content of a memory M1 of a POS unit (POS1) is compacted by an encoder C1, the content is split, distributed to and backed up in memories M2 to M5 of POS units (POS2 to POS5). If a fault occurs to the memory M1 of the POS unit (POS1), the respective pieces of data backed up in the POS units (POS2 to POS5) are combined, decoded by the decoder D1 and restored in the memory M1.

Abstract: The present invention discloses a method for saving data including system status data stored in a memory to a backup server via a data communication network if the remaining capacity of the battery is not sufficient, by confirming continuously the remaining capacity of the battery, in a suspend mode in a computer system. Accordingly, the present invention previously prevents important data from losing although the system-down is occurred abruptly by the perfect discharge of the battery.

Abstract: A person who would like to cancel read-protection of ROM data inputs an “address,” an “information length,” and an “input information part.” The input information part should be a part of a data file stored in the ROM. The input address corresponds to the starting address of the information part in the ROM. The input information length is the length of the input information part. A ROM-data read-control circuit reads a stored information part with the input information length from an area or areas in the ROM with the input starting address. Next, the ROM-data read-control circuit compares the stored information part with the input information part. The ROM-data read-control circuit cancels the read-protection when the input information part coincides with the stored information part.

Abstract: An apparatus and method for swapping out real memory by inhibiting input/output (I/O) operations to a memory region are provided. The apparatus and method provide a mechanism in which a quiesce indicator is provided in a field containing the current outstanding I/O count associated with the memory region whose real memory is to be swapped out. The current I/O field and the quiesce indicator are used as a means for communicating between a shared resource arbitrator and a guest consumer. When the quiesce indicator is set, the guest consumer is informed that it should not send any further I/O operations to that memory region. When the number of pending I/O operations against the memory region is zero, a valid bit in a protection table is set to invalid, and the real memory associated with the memory region may be swapped out.

Abstract: The invention relates to a method of controlling access by a function to a collective resource. Said method imposes that the function waits for a minimum number of clock cycles CLK called latency [LAT] between two successive accesses of the function and imposes a number of cycles called penalty [PEN] which is higher than the latency between two successive accesses when a given number of successive accesses separated around and having at least the value of the latency has taken place beforehand.

Abstract: Systems and methods for selecting pin functionality in memory controllers are provided. These memory controllers have pins that can be used to drive different types of signals, depending on the type of memory coupled to the memory controller. For example, pins can be used to drive clock signals or chip select signals. Accordingly, because different types of memory require different numbers of clock and chip select signals, the same memory controller can be advantageously used with different types of memory. Moreover, memory controller pins that would ordinarily go unused with some types of memory can now be used to increase the number of such memories that can be coupled to the memory controller.

Abstract: System and methods for addressing unique locations in an matrix are discloses. According to some embodiments, the system includes In another embodiment, a system consisting of a plurality of uniquely addressable locations is disclosed. These embodiments includes a plurality of virtual columns that include a plurality of serially connected switch elements. The plurality of switch elements may be one of a plurality of responsive types and responsive to at least one of a plurality of possible switching signal types.

Abstract: A method for decoding a memory array address for an embedded DRAM (eDRAM) device is disclosed, the eDRAM device being configured for operation with an SDRAM memory manager. In an exemplary embodiment of the invention, the method includes receiving a set of row address bits from the memory manager at a first time. A set of initial column address bits is then subsequently from the memory manager at a later time. The set of initial column address bits are translated to a set of translated column address bits, and the set of row address bits and the set of translated column address bits are simultaneously used to access a desired memory location in the eDRAM device. The desired memory location in the eDRAM device has a row address corresponding to the value of the set of row address bits and a column address corresponding to the value of the set of translated column address bits.

Abstract: A soft cache system compares tag bits of a virtual address with tag fields of a plurality of soft cache register entries, each entry associated with an index to a corresponding cache line in virtual memory. A cache line size for the cache line is programmable. When the tag bits of the virtual address match the tag field of one of the soft cache entries, the index from that entry is selected for generating a physical address. The physical address is generated using the selected index as an offset to a corresponding soft cache space in memory.

Abstract: A multiprocessor-scalable streaming data server arrangement in a multiprocessor data server having N processors, N being an integer greater than or equal to 2, includes implementing N NICs (Network Interface Cards), a first one of the N NICs being dedicated to receiving an incoming data stream. An interrupt from the first one of the N NICs is bound to a first one of the N processors and an interrupt for an nth NIC is bound to an nth processor, 0<n<=N. A DPC (Deferred Procedure Call) for the nth NIC is bound to the nth processor. M client connections may be tightly coupled to the nth processor via the nth NIC, M being a positive integer. P server threads may be bound to specific ones of a second through N processors. L1 (Level 1) and L2 (Level 2) caches may be defined for each of the N processors, instructions and temporal data being stored in L2 caches of the N processors and non-temporal data being stored in L1 caches of the N processors, bypassing the L2 caches.

Abstract: Input information including processor group division information that is used to divide processors, which will be used in parallel calculation, into groups each of which will form a rectangular shape on a network and that is specified by information other than logical processor numbers is input to the processors of a parallel computer system. Each processor checks the received processor group division information to determine the logical processor numbers belonging to the groups. Communication among the determined possessors is done in a plurality of stages: intra-group communication processing and inter-group communication processing. Because the processors forming a group are arranged in a rectangular shape on the network, intra-group communication processing may be executed with no network conflict.

Abstract: An arrayed processor has a plurality of processing elements each having a plurality of types of arithmetic logic units for processing data having different numbers of bits from one another. The arrayed processor divides a series of processing data of various numbers of bits supplied from an external circuit into data of more bits and data of fewer bits. These data are processed in parallel by the arithmetic logic units of the processing elements. The efficiency of arrayed processor can be increased, since small-scale processing operations are individually performed by the processing elements and connections between the processing elements are made according to object codes.

Abstract: A single-chip microcomputer comprising: a first bus having a central processing unit and a cache memory connected therewith; a second bus having a dynamic memory access control circuit and an external bus interface connected therewith; a break controller for connecting the first bus and the second bus selectively; a third bus having a peripheral module connected therewith and having a lower-speed bus cycle than the bus cycles of the first and second buses; and a bus state controller for effecting a data transfer and a synchronization between the second bus and the third bus. The single-chip microcomputer has the three divided internal buses to reduce the load capacity upon the signal transmission paths so that the signal transmission can be accomplished at a high speed. Moreover, the peripheral module required to have no operation speed is isolated so that the power dissipation can be reduced.