Patents Issued in March 6, 2003
  • Publication number: 20030046615
    Abstract: Exemplary embodiments of the invention provide methods and systems for performing reliability balancing, based on past distributed programming network component history, which balances computing resources and their processing components for the purpose of improving the availability and reliability of these resources.
    Type: Application
    Filed: December 22, 2000
    Publication date: March 6, 2003
    Inventor: Alan Stone
  • Publication number: 20030046616
    Abstract: A system and method for configuring a plurality of monitors, which are contained within a complex circuit, to monitor a valid combination of events within the complex circuit. Each monitor of the complex circuit is only able to monitor a subset of the total set of events which may be monitored. The present invention allows a user to select valid associations between events and monitors, and then processes those selected associations for configuration of the complex circuit. The selected associations may be stored and reused in the future.
    Type: Application
    Filed: August 29, 2001
    Publication date: March 6, 2003
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Cheng A. Feng, Jason D. Hibbeler, Theodore G. Hoover, Judith K. Ingles, Jhy-Chun Wang
  • Publication number: 20030046617
    Abstract: Generating a modified mesh by simplifying an original mesh representing a scene or object is achieved by collapsing edges of the original mesh in an order defined by an error metric to produce the modified mesh. Determining the error metric includes selecting an edge of the mesh, performing an edge collapse operation for the selected edge, computing at least one distance from a plane of each updated face of the mesh to a position of a vertex removed during the edge collapse operation, selecting a maximum distance of the computed distances as the error metric for the edge collapse operation for the selected edge, and restoring the collapsed edge to the mesh.
    Type: Application
    Filed: August 30, 2001
    Publication date: March 6, 2003
    Inventor: Mike B. MacPherson
  • Publication number: 20030046618
    Abstract: A system performs a two-step skew compensation procedure by first correcting for any phase error alignment between a parallel link clock and data signal edges of each data channel, thereby allowing the received data bits to be correctly sampled. Then, a second step is performed to “word-align” the bits into the original format, which is accomplished with a Skew Synchronizing Marker (SSM) byte in a data FIFO of each data channel. The SSM byte is transmitted on each data channel and terminates the skew compensation procedure. When the SSM byte is detected by logic in the data FIFO of each data channel, the data FIFO employs the SSM byte to initialize the read and write pointers to properly align the output data.
    Type: Application
    Filed: August 29, 2001
    Publication date: March 6, 2003
    Inventor: Hansel A. Collins
  • Publication number: 20030046619
    Abstract: The present invention provides an access control device and a testing method that can simplify the software operations in an access control operation such as a JTAG control operation, and enable the hardware to perform a high-speed control operation. The access control device conducts a test or diagnosis on an object by accessing a serial interface based on a command and data that specify a testing or diagnosing route. Under the control of a processor, a control circuit in the access control device executes an access sequence in accordance with a command string and an input data string stored in a memory, and stores the data outputted from the object to be tested or diagnosed in the memory as an output data string. The control circuit sets a state transition route for each objective state in advance, so that a transition route can be readily determined for an objective state specified by the command string.
    Type: Application
    Filed: March 25, 2002
    Publication date: March 6, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Keiji Sato, Toshiro Nakazuru, Shigeaki Okutani, Noboru Morita
  • Publication number: 20030046620
    Abstract: A method of testing cache memory is proposed, which is designed for use on a memory system having a primary memory unit and a cache memory unit for testing the cache memory unit to check if the cache memory unit is normal in read/write operations. The proposed method comprises the steps of writing a block of test data into the cache memory unit; converting the test data through a first encoding process into a first block of encoded data; writing the first block of encoded data into the primary memory unlit; fetching data from the primary memory unit; converting the fetched data from the primary memory unit through a second encoding process into a second block of encoded data; and storing the second block of encoded data into the cache memory unit; and finally comparing either the first block of encoded data or the second block of encoded data against a predetermined block of reference data to check whether the read/write operation to the cache memory unit is normal.
    Type: Application
    Filed: August 30, 2001
    Publication date: March 6, 2003
    Inventor: Ching-Jer Liang
  • Publication number: 20030046621
    Abstract: A method and system for generating memory array bitmaps is disclosed that uses the memory binary address and failing memory data bits collected during test of a chip as input and translates this input directly to physical location in the GDSII and/or GL1 physical design formats which uses memory and a logical to physical server in an electronic computer aided design system.
    Type: Application
    Filed: August 31, 2001
    Publication date: March 6, 2003
    Inventors: Ulrich A. Finkler, Gary W. Maier, Kevin C. Quandt, Robert E. Shearer
  • Publication number: 20030046622
    Abstract: An integrated circuit (100) includes functional input and output signal leads (101,111), input and output circuits (102,112) connected to the functional input and output signal leads, core circuitry (120, 122, 124), and interconnect wires and circuits (103) connecting the input and output circuits and the core circuitry. The integrated circuit further includes an addressable test port (105, 115, 135) for each core industry. Each test port is connected to its respective core circuitry and to the interconnect wires and circuits. External test signal leads (106) connected to each test port.
    Type: Application
    Filed: October 25, 2002
    Publication date: March 6, 2003
    Inventor: Lee D. Whetsel
  • Publication number: 20030046623
    Abstract: An integrated circuit, including a configurable scan architecture used for an integrated circuit test procedure and quality control. The configurable scan chain architecture has the capability of being reconfigured to one of a variety scan chain architectures based on the constraints of the integrated circuit and the testing device. The present invention minimizes the integrated circuit test time by reconfiguring the scan architecture depending on certain constraints such as the latching frequency, the predetermined I/O frequency, the number of available integrated circuit I/O pins, the number of pins required for a proposed scan architecture, and the number of available pins on the testing device. The configurable scan architecture receives configuration signals which indicate which scan chain architecture should be configured on the integrated circuit that is being tested.
    Type: Application
    Filed: September 4, 2001
    Publication date: March 6, 2003
    Inventors: Ajay Khoche, Jochen Rivoir, David H. Armstrong
  • Publication number: 20030046624
    Abstract: A set of levels generating circuits, such as a set of digital-to-analog converters, is designed into an integrated circuit on-die. The levels generating circuits apply direct current (DC) voltage levels to on-die sense amplifiers to test sense amplifier trip points for “input low voltage” (VIL) and “input high voltage” (VIH). The levels generating circuits are controlled by a set of configuration bits, which may be accessible through the boundary-scan register or the input/output (I/O) loop back pattern generator. The levels generating circuitry allows testing of one number of integrated circuit input pins using a smaller number of input pins.
    Type: Application
    Filed: August 28, 2001
    Publication date: March 6, 2003
    Inventor: Ali Muhtaroglu
  • Publication number: 20030046625
    Abstract: A system to select a first and second test access port controller in response to a mode of operation.
    Type: Application
    Filed: August 30, 2001
    Publication date: March 6, 2003
    Inventors: Sankaran M. Menon, Eduardo J. Rodriguez, Terry R. Altmayer
  • Publication number: 20030046626
    Abstract: A method is disclosed for testing applications that include non-deterministic behavior. The presently disclosed method generates test code for testing deterministic behavior of an application. When instances of non-deterministic behavior of the application being tested are encountered, the method provides acceptable alternate behaviors, such that the non-deterministic behavior can be effectively tested. The method may be implemented as a software test tool that utilizes a graphical programming interface to make the test generation simple and easy to use.
    Type: Application
    Filed: August 30, 2001
    Publication date: March 6, 2003
    Inventors: Wesley C. Hand, Mark Trumpler, Eric Noorda, Albert Seeley, Kathy Campbell, Nathan W. David, Peter Savage
  • Publication number: 20030046627
    Abstract: A method and circuit periodically pseudo-randomly select a sample of digital event pulses comprising a logic data signal. A first timer times a first time interval. A second timer times a second time interval within the first time interval. A delay timer, coupled between the first and second timers, pseudo-randomly delays initiation of the second timer from the start of the first time interval. In one embodiment, the first timer is an (N+1)-bit binary counter. The delay timer includes an N-bit round robin latch and seeded by a pseudo-random number generator having fewer than N bits, the round robin latch shifting its contents to form an N-bit pseudo-random number. The second timer is initiated when the value of the first timer is equivalent to the round robin latch. A coincidence circuit passes digital event pulses during the second time interval. A count is accumulated of the sampled digital event pulses.
    Type: Application
    Filed: August 22, 2001
    Publication date: March 6, 2003
    Inventor: Joseph Weiyeh Ku
  • Publication number: 20030046628
    Abstract: Error methods, systems, and medium may comprise processing error conditions associated with transactions in a manner that may enable error source identification.
    Type: Application
    Filed: September 6, 2001
    Publication date: March 6, 2003
    Inventors: Linda J. Rankin, David J. O'Shea
  • Publication number: 20030046629
    Abstract: A block coding algorithm uses an original block group having n+1 original blocks of m-bit message, which a first original block of m-bit message is encoded as a reference block of n-bit codeword and n original blocks of m-bit message placed after the first original block of m-bit message are encoded as n weighted blocks of n-bit codeword, based on a bit sequence of the reference block. A block decoding algorithm decodes n weighted blocks to generate corresponding original blocks of m-bit message and reconstructs the first original block of m-bit message from a sequence of reference bits, wherein each reference bit implies whether each of n weighted blocks is an A type weighted block or a B type weighted block.
    Type: Application
    Filed: February 25, 2002
    Publication date: March 6, 2003
    Inventors: Jae-Woo Roh, Euiseok Hwang
  • Publication number: 20030046630
    Abstract: A memory that corrects storage errors during those periods in which the memory is not servicing read/write instructions from an external system. The memory reads and writes data words that are stored in a storage block that includes a plurality of storage words. Each storage word stores a data entry specifying one of the data words. The data entry is encoded with error-correcting information sufficient to correct a one-bit error in the data word. The storage words are connected to the error-correcting circuit during idle periods or during the conventional refresh operations in the case of DRAM-like memories. The controller also causes each corrected storage word to be re-written to the storage block in place of the storage word from which the corrected storage word was generated if an error is detected by the error-correcting circuitry.
    Type: Application
    Filed: September 5, 2001
    Publication date: March 6, 2003
    Inventor: Mark Hilbert
  • Publication number: 20030046631
    Abstract: A system (70) comprising a microprocessor (74), a data bus (75) for writing data into a Flash memory device (71) and a data bus (75) for reading data from the Flash memory device (71). The Flash memory device (71) comprises an error correction encoder (72), a Flash memory (71), an error correction decoder (73), and a Flash data bus (75) for interconnecting the error correction encoder (72), the Flash memory (71), and the error correction decoder (73). The data, when being processed by the error correction encoder (72) are converted into a word that comprises a status word (51), a data word (52), and a redundancy word (53). This approach enables error correction with single-bit alterability.
    Type: Application
    Filed: April 22, 2002
    Publication date: March 6, 2003
    Inventors: Steffen Gappisch, Constant Paul Marie Jozef Baggen, Andre Guilliaume Joseph Slenter, Hans-Joachim Gelke
  • Publication number: 20030046632
    Abstract: When to a memory cell array 21 a read/write operation is performed of the 7-bit data in which parity bits of 3 bits are added to data of 4 bits, an error correction is carried out in concern to each of the 7-bit data. The memory cell array is divided into memory units 31 to 37 each of which has four bits which are arranged along a direction of a word line. On writing the 7-bit data in the memory cell array, bits of the 7-bit data that are different from one another are written as written bit data along the direction of the word line in the memory units 31 to 37, respectively. In the 7-bit data, the written bit data has an interval off our bits. Error correcting circuits performs an error correction of the 7-bit data in each of the 7-bit data.
    Type: Application
    Filed: July 12, 2002
    Publication date: March 6, 2003
    Inventors: Makoto Hatakenaka, Koji Nii, Atsuo Mangyo, Takeshi Fujino
  • Publication number: 20030046633
    Abstract: In an aspect, a method and a system are provided to improve data transmission. In an aspect, the transmitted data is broadcasted. Data is compiled on reported factors that cause data transmission errors and predictions are compiled on unreported factors that cause data transmission errors. In an aspect, the data transmission error factors include regional factors including terrain, environmental factors including weather, atmospheric conditions, sunspot activity and season, radio frequency propagation including Keplerian elements, and retransmission factors. In an aspect, data error correction is employed based on the reported factors and on the predicted factors.
    Type: Application
    Filed: August 28, 2001
    Publication date: March 6, 2003
    Inventor: Curtis E. Jutzi
  • Publication number: 20030046634
    Abstract: An output coding apparatus includes a coder for coding an inputted bitstream to an error correction and/or detection code composed of information bits and check bits; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream, arranging the information bits at any desired positions of the bitstream, and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream. Therefore, when the coding apparatus is combined with a resynchronization method using both an error correction and/or detection code and a synchronization code, it is possible to solve a problem caused by pseudo-synchronization or synchronization-loss pull-out or step-out due to erroneous detection of the synchronization code.
    Type: Application
    Filed: October 24, 2002
    Publication date: March 6, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Yoshihiro Kikuchi, Toshiaki Watanabe, Kenshi Dachiku, Takeshi Chujoh, Takeshi Nagai
  • Publication number: 20030046635
    Abstract: A method for determining r error detection bits that can be associated with a word of m bits to be coded, including the step of calculating the product of a vector with m components representative of the word of m bits to be coded and of a parity control matrix of dimension r×m. The parity control matrix is such that each column of matrix includes an odd number of “1s” greater than or equal to three. The present invention also relates to a method for determining a syndrome.
    Type: Application
    Filed: April 2, 2002
    Publication date: March 6, 2003
    Applicant: STMicroelectronics S.A.
    Inventors: Laurent Murillo, Francois Ricodeau
  • Publication number: 20030046636
    Abstract: An error detector at a receiver comprises a feedback shift register. A shift direction in the feedback shift register is opposite to a shift direction at a transmitter in generating a transmission bit string by using a specified generator polynomial. A reception bit string is inputted to the feedback shift register in reverse order to the transmission bit string was generated at the transmitter so that errors in the reception bit string is detected by obtaining the remainder. Another error detector at a receiver comprises first and second feedback shift registers. Respective shift directions in the first and second feedback shift registers are the same as and opposite to a shift direction at a transmitter in generating a transmission bit string.
    Type: Application
    Filed: August 20, 2002
    Publication date: March 6, 2003
    Applicant: Fujitsu Limited
    Inventors: Masami Kanasugi, Shoji Taniguchi, Koichi Kuroiwa, Mahiro Hikita
  • Publication number: 20030046637
    Abstract: A software implementation of a Reed-Solomon decoder placing a constant load on the processor of a computer. A Berlekamp-Massey Algorithm is used to calculate the coefficients of the error locator polynomial, a Chien Search is used to determine the roots of the error locator polynomial, and a Forney Algorithm is used to determine the magnitude of the errors in the received digital code word. Each step is divided into m small tasks where m is the number of computational blocks it takes to read in a code word and the processor can pipeline or parallel process one task from each step each time a block is read.
    Type: Application
    Filed: August 21, 2001
    Publication date: March 6, 2003
    Applicant: Equator Technologies, Inc.
    Inventor: Jian Zhang
  • Publication number: 20030046638
    Abstract: In accordance with a preferred embodiment of the instant invention, there is provided a method and apparatus for enhancing the value of prerecorded works such as movies and music, as well as computer games, by randomly choosing alternative content segments at different points within the work, thereby potentially offering the user a different experience each time the work is played. This invention is suitable for use with specially prepared music, movies, videos, computer games and the like, wherein a plurality of interchangeable parallel or sequential content segments are specified. At each time point where such content segments are specified, the instant method selects randomly from them for presentation to the user.
    Type: Application
    Filed: August 31, 2001
    Publication date: March 6, 2003
    Inventor: Kerry A. Thompson
  • Publication number: 20030046639
    Abstract: Techniques for integrating software systems, application tools, and business modules into a unified platform and open framework for building, deploying, and maintaining business applications of different types and varying nature in a heterogeneous computing environment. This is achieved by configuring the semantics of business entities, the presentation of structured and semi-structured information, the processing rules and logics among business modules, and the relationships of the participating users and organizations with other business entities. Integration of the software systems, application tools and business modules is achieved through integration of the key elements, which are business semantics, presentation logics, business rules, user entities and system models.
    Type: Application
    Filed: May 9, 2002
    Publication date: March 6, 2003
    Applicant: Core IPR Limited
    Inventors: Hung Ka Fai, Lam Wing Bavflynn, Tai Jin Yen
  • Publication number: 20030046640
    Abstract: A technique to generate a logic design for use in designing an integrated circuit (IC). The technique includes embedding a combinatorial one-dimensional logic block within a two-dimensional schematic presentation to form a unified database. The technique also includes following a set of design capture rules, importing the combinatorial one-dimensional logic block, and notifying a designer when importing the combinatorial data block violates the set of design capture rules.
    Type: Application
    Filed: August 29, 2001
    Publication date: March 6, 2003
    Inventors: William R. Wheeler, Matthew J. Adiletta
  • Publication number: 20030046641
    Abstract: A chip simulation technique includes describing a representation of a first simulation model to a graphical user interface using hardware descriptions stored in a database then receiving responses of the first simulation model to a first signal applied to the model. A second simulation model is subsequently described to the same graphical user interface.
    Type: Application
    Filed: January 7, 2002
    Publication date: March 6, 2003
    Inventors: Timothy J. Fennell, William R. Wheeler
  • Publication number: 20030046642
    Abstract: Representing a logic device generally includes creating a model of a logic device, where the model represents a collection of variants of the logic device. A representation of the model may be used in a logic design and a particular variant of the logic device may be selected automatically based on connections made to the representation. Connection errors may be detected automatically and a first indication may be displayed automatically when the connection errors are detected. A second indication that differs from the first indication may be displayed automatically when the connection errors are corrected.
    Type: Application
    Filed: December 18, 2001
    Publication date: March 6, 2003
    Inventors: William R. Wheeler, Timothy J. Fennell, Matthew J. Adiletta
  • Publication number: 20030046643
    Abstract: Elements of a combinational circuit are divided into plural groups. The output from a terminal Q is fixed at shifted timing in flip-flop circuits belonging to each of groups X, Y and Z resulting from this grouping. With the outputs from the terminals Q of the flip-flop circuits thus fixed, an operation of a shift mode is carried out. When the operation of the shift mode is completed, a hold releasing operation and a capture operation are carried out with respect to each of the groups of the flip-flop circuits. For example, the hold releasing operation is carried out when one clock is at a high level with the capture operation carried out when the clock is at a low level, or the hold releasing operation is successively carried out with respect to each of the groups and then the capture operation for capturing a data signal is carried out with respect to each of the groups.
    Type: Application
    Filed: October 28, 2002
    Publication date: March 6, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Mitsuyasu Ohta, Sadami Takeoka
  • Publication number: 20030046644
    Abstract: A method comprising monitoring a design environment to detect the addition of a circuitry component to a circuit being designed by a circuit designer. The method accesses a connection parameter definition file that specifies a set of connection parameters for that added circuitry component. The method compares the connection parameters defined in the connection parameter definition file with the actual connections of the added circuitry component. The method provides the circuit designer with feedback concerning the validity of the actual connections of the added circuitry component.
    Type: Application
    Filed: August 29, 2001
    Publication date: March 6, 2003
    Inventors: William R. Wheeler, Matthew J. Adiletta
  • Publication number: 20030046645
    Abstract: The monitor manager manages the execution of monitors during the simulation of a digital design. The monitor manager (20) includes an instance generator (32) that creates executable instances (38) of monitors that may be time-dependent monitors, an activation manager (34) that assigns instances to be active or inactive, and an execution unit (36) that executes active instances and receives returned status values passed, failed, active, or error. Executable instances of time-dependent monitors are software state machines having a state variable, one or more time-dependent variables, and at least two state-driven code blocks, at least one of which might be either a cycle-dependent code block that tests for a specific cycle-dependent condition, or an event-dependent code block that tests for a specific event-dependent condition. In either case, the state-driven code block increments the time-dependent variable, and, when the condition has been satisfied, increments the state variable.
    Type: Application
    Filed: June 21, 2002
    Publication date: March 6, 2003
    Inventor: Fritz A. Boehm
  • Publication number: 20030046646
    Abstract: An integrated circuit design apparatus includes a block placement processing unit which performs processing of creation of a lower-rank mounting block in a higher-rank mounting block, and performs processing of creation of virtual placement regions in each of the lower-rank mounting block and the higher-rank mounting block. A functional block assignment processing unit performs processing of assignment of functional blocks to each of the virtual placement regions provided by the block placement processing unit. An evaluation processing unit provides a display of a condition of the functional blocks assigned to each of the virtual placement regions of both the lower-rank mounting block and the higher-rank mounting block, in order to evaluate the condition of the assigned functional blocks.
    Type: Application
    Filed: March 25, 2002
    Publication date: March 6, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Yasuo Amano, Hiroshi Seki, Yukio Makino, Yumiko Yamanishi, Yoshiko Nakanishi, Yoichiro Ishikawa
  • Publication number: 20030046647
    Abstract: First, stripe wirings A and B are set virtually intersect each other. A width of a strand of each of the stripe wirings A and B is set equal to/lower than a maximum line width decided by constraints imposed on a manufacturing process. Then, lengths of the strands in intersection portion of the stripe wirings A and B are compared with each other, and a longer strand is set as a strand to be changed for position. However, it is only a part of the strand in the intersection portion that is changed for position. Subsequently, an intersection point of center lines X and Y of the stripe wirings A and B is set as a reference position, and the strand to be changed for position is moved in a direction away from the reference position to a position where an occupancy rate of a wiring becomes equal to/smaller than a maximum occupancy rate of a wiring decided by constraints imposed on the manufacturing process.
    Type: Application
    Filed: March 15, 2002
    Publication date: March 6, 2003
    Applicant: Fujitsu Limited
    Inventor: Tetsuya Anazawa
  • Publication number: 20030046648
    Abstract: Displaying information relating to a logic design includes generating a first display that relates to the logic design, the first display being associated with other information not included in the first display, retrieving the other information in response to a user input, and generating a second display that relates to the logic design based on the other information.
    Type: Application
    Filed: August 29, 2001
    Publication date: March 6, 2003
    Inventors: William R. Wheeler, Matthew J. Adiletta
  • Publication number: 20030046649
    Abstract: A technique for designing a logic circuit includes specifying a model. The model including combinatorial blocks, state elements and graphical library elements. The technique maintains a data structure representative of the model, and generates an architectural model and an implementation model from the data structure. The data structure represents a descriptive net list of the model. The architectural model includes C++ code and the implementation model includes Verilog.
    Type: Application
    Filed: August 28, 2001
    Publication date: March 6, 2003
    Inventors: William R. Wheeler, Matthew J. Adiletta, Christopher Clark, Timothy J. Fennel
  • Publication number: 20030046650
    Abstract: Distinguishing information that differentiates one portion with a port located on a boundary of a logic layer on a net crossing the logic layer as the boundary from another portion is added to each of the portions (step ST2). Each time a cell forming a specific region of a logic circuit is laid out, a layout of the logic circuit in that region is analyzed, a logic optimization is executed to rewrite the net list of the logic circuit in that region so as not to alter the number of ports located on the boundary of the logic layer by using the distinguishing information, and the layout of the logic circuit in that region is modified on the basis of the rewritten net list (step ST3).
    Type: Application
    Filed: July 12, 2002
    Publication date: March 6, 2003
    Inventor: Genichi Tanaka
  • Publication number: 20030046651
    Abstract: In a printed circuit board design support apparatus for supporting design of a printed circuit board by calculating a radiation amount of electromagnetic radiation caused by an interconnection on the basis of design information related to each of the printed circuit board having a ground plane, interconnections formed on the printed circuit board, and components to be mounted on the printed circuit board, an arithmetic unit calculates a common mode (CM) radiation amount of the interconnection on the basis of a CM radiation amount ratio that indicates a ratio of a common mode (CM) radiation amount of electromagnetic radiation caused by the ground plane in correspondence with the interconnection to a differential mode (DM) radiation amount of electromagnetic radiation caused by the interconnection. A printed circuit board design support method and program are also disclosed.
    Type: Application
    Filed: June 18, 2002
    Publication date: March 6, 2003
    Applicant: NEC CORPORATION
    Inventors: Hideki Sasaki, Takahiro Yaguchi, Akira Wakui, Seishi Eya, Takashi Harada, Toshihide Kuriyama
  • Publication number: 20030046652
    Abstract: A method comprising maintaining a circuit design parameter file for a circuit being designed by a circuit designer. The circuit design parameter file specifies a physical characteristic of the circuit. The method monitors a design environment to detect the addition of a circuitry component to the circuit and accesses a component design parameter file that specifies at least one design parameter for that added circuitry component. The method updates the circuit design parameter file based on the at least one design parameter included in the component design parameter file.
    Type: Application
    Filed: August 29, 2001
    Publication date: March 6, 2003
    Inventors: William R. Wheeler, Matthew J. Adiletta
  • Publication number: 20030046653
    Abstract: A method and apparatus for providing correction for microloading effects is described. Hybrid proximity correction techniques are used to make the problem computationally more feasible. More specifically, feature edges in a layout can be grouped into those edges, or edge segments, with a large edge separation (group B), e.g. greater than n, and those having less than that separation (group A). The group B features can then be corrected for microloading effects rapidly using rules based correction. Then both groups of edges can be corrected using model based optical proximity correction using the output of the rule based correction as the ideal, or reference, layout.
    Type: Application
    Filed: August 31, 2001
    Publication date: March 6, 2003
    Applicant: Numerical Technologies, Inc.
    Inventor: Hua-Yu Liu
  • Publication number: 20030046654
    Abstract: A method of producing a layout for a mask for use in semiconductor production includes a two-stage, iterative optimization of the position of scatter bars in relation to main structures being carried out. In a first stage, following first production of scatter bars and carrying out an OPC, scatter bars are again generated based on the corrected main structures. A renewed OPC is then carried out, followed by the renewed formation of scatter bars. This is repeated until the layout has been optimized sufficiently. Then, in the second stage, defocused exposure of the layout is simulated and, if required, further adaptation of the scatter bars is carried out. The first and second iterative stages can also be employed independently of each other. The common factor in the iterations is that the scatter bar positions are varied with each iteration and is therefore optimized.
    Type: Application
    Filed: September 3, 2002
    Publication date: March 6, 2003
    Inventors: Christof Tilmann Bodendorf, Jorg Thiele
  • Publication number: 20030046655
    Abstract: A data processing apparatus comprises a grid pattern area calculation section (24) for calculating the minimum grid and the present area of a circuit element for each layer of circuit patterns given by CAD data (1); an overlap area calculation section (25) for calculating an overlap area of present areas; and a composition/division optimization judgment section (26) for judging by a criterion whether the layers including the overlap area should be processed according to a single common grid or different grids. Each layer can be assigned the grid with the minimum accuracy required for the layer. A grid with more minute accuracy than it requires may not be used. Operation load in making reticle mask data and processing load in actually performing exposure or the like are thereby considerably relieved.
    Type: Application
    Filed: October 29, 2002
    Publication date: March 6, 2003
    Applicant: Fujistu Limited
    Inventor: Shigeru Kimura
  • Publication number: 20030046656
    Abstract: A method is disclosed comprising providing a plurality of information technology hubs, each information technology hub located at one of a plurality of geographic locations, each information technology hub located at a geographic location different from the other information technology hubs. Each of the information technology hubs provides computer system support to a plurality of clients within a geographic area. Each of the information technology hubs may provide twenty-four hours a day and seven days a week of computer systems support for each of its plurality of clients.
    Type: Application
    Filed: August 29, 2002
    Publication date: March 6, 2003
    Inventor: Asha Saxena
  • Publication number: 20030046657
    Abstract: A system and method for creating a graphical program operable to configure one or more switch devices. A first node may be displayed in the graphical program, wherein the first node is operable to use route information to control or configure one or more of switch devices in a switching system. The first node may be configured with route information. For example, the route information may comprise information specifying one or more routes previously configured and stored. Also, the route information may comprise information specifying two endpoints of a route, as in the case of run-time auto-routing, or may comprise information explicitly specifying a complete route. The first node may be operable to perform various types of operations to control or configure the one or more switch devices, such as a connect operation to connect specified routes.
    Type: Application
    Filed: March 29, 2002
    Publication date: March 6, 2003
    Inventor: Jason White
  • Publication number: 20030046658
    Abstract: A computer system receives a description of a finite state machine including a temporal logic condition and generates code for emulating the described finite state machine.
    Type: Application
    Filed: May 2, 2001
    Publication date: March 6, 2003
    Inventors: Vijaya Raghavan, Ebrahim Mehran Mestchian
  • Publication number: 20030046659
    Abstract: Briefly, in one example of the present invention, a code generator automatically produces Viterbi algorithm code for the architecture of a general-purpose processor. Upon input of version parameters such as, but not limited to, the generator polynomials, the constraint length and the rate, the code generator produces versions of Viterbi algorithm code for use in the processor. In another example, a code generator produces a description of a Viterbi accelerator. The processor may be a digital signal processor.
    Type: Application
    Filed: June 18, 2002
    Publication date: March 6, 2003
    Inventor: Shimon Samoocha
  • Publication number: 20030046660
    Abstract: An action table that describes an action for each state is generated by extracting cells that describe the action to be executed by a system from a state transition matrix. A transition table that describes a state of the transition destination for each state is generated by extracting only cells that describe actions of transition destinations from the generated matrix. An event table that describes an event that exists in each state is generated. A program code is generated by confirming existence of an event under each state by referring to the event table when an event has occurred, and by executing an action of an event that has occurred in the current state by referring to the action table and the transition table.
    Type: Application
    Filed: August 28, 2002
    Publication date: March 6, 2003
    Applicant: CATS CO., LTD.
    Inventor: Masahiko Watanabe
  • Publication number: 20030046661
    Abstract: A system and method for the development of multiple cross-vertical application software packages each pertaining to given variant industries. The system and method employ a process for discovering and identifying common business functions from a database of industries and associated existing vertical application software listings. Once discovered and identified, applied market analyses and metrics determine a specific set of target industries and associated common business functions between them for application development. A broadly functional technology platform is developed in light of identified common business functions from the target industries. Business data and business logic relating to target industries are acquired from subject matter experts and business content providers.
    Type: Application
    Filed: July 3, 2002
    Publication date: March 6, 2003
    Inventors: Mark Farber, Richard Schramm, Stuart Shirai
  • Publication number: 20030046662
    Abstract: A data reproduction apparatus which reproduces data based on script data, in which a script execution location specifying section modifies the execution location held in a table when output data from an output section that outputs an input code, time code or clock data coincides with an input code, time code or clock data held in a table; and a script analysis and execution section executes processing that corresponds to the commands of the script data, and, it further controls reproduction of data according to reproduction instructions specified at the execution location that is modified by the script execution location specifying section when the output data coincides with the input code, time code or clock data held in the table.
    Type: Application
    Filed: March 5, 2002
    Publication date: March 6, 2003
    Applicant: DENON, LTD.
    Inventor: Keishi Matsunaga
  • Publication number: 20030046663
    Abstract: A system and method for implementing a debugging graphical program in a main graphical program. A user can associate a debugging graphical program with a wire in a data flow diagram in order to debug and/or analyze the main graphical program. This association does not change or require recompilation of the main graphical program. The debugging graphical program, or smart probe, receives the data from the main graphical program, analyzes this data, and can perform one of several actions. The debugging graphical program can display the data in the wire, generate statistics based on received data, log statistics or data to a file, or perform other analysis functions. The debugging graphical program can also cause the main graphical program into halting execution, entering single stepping mode, etc. The user may choose a debugging graphical program already present, or create one using graphical programming techniques.
    Type: Application
    Filed: August 28, 2001
    Publication date: March 6, 2003
    Inventors: Steven W. Rogers, Jeffrey L. Kodosky
  • Publication number: 20030046664
    Abstract: A method and system for debugging a computer program are described. In one embodiment, information pertaining to a first function executed within the computer program is presented in a first sub-window of a stack window. Further, information pertaining to a second function executed within the computer program is presented in a second sub-window of the stack window. The second sub-window is positioned next to the first sub-window to provide a horizontal arrangement of the sub-windows within the stack window.
    Type: Application
    Filed: September 4, 2001
    Publication date: March 6, 2003
    Inventor: James Pangburn