Abstract: A read-only nonvolatile memory in which the leakage current of unselected memory cell transistors is suppressed. Adjacent memory cell transistors are commonly connected to drain lines, and adjacent memory cell transistors on the other side are commonly connected to source lines. Gates within a same row are commonly connected to a word line. An offset structure is formed on the drain side of each memory cell transistor, and a non-offset structure is formed on the source side. Accordingly, in each memory cell transistor a depletion layer is generated between the drain region and channel region when a drain line is activated, but the depletion layer directly under a drain region does not reach the channel region when the drain line is in a state of high impedance. Therefore, there is no leakage current from the drain to the source in unselected memory cell transistors. Since there is no leakage current flowing from unselected memory cell transistors to source lines, the read margin is enhanced.

Abstract: In a floating gate type nonvolatile semiconductor memory having a memory cell array constituted of a plurality of memory cells arrayed in a matrix pattern, word lines and bit lines, with the word lines connected to a row of gate electrodes of memory cells with one cell drain voltage exclusively connected to drain electrodes of either even-numbered memory cells or odd-numbered memory cells among the memory cells through select lines in units of individual rows, another cell drain voltage is connected to the bit lines sequentially via a data write circuit and a multiplexer circuit, the bit lines are each connected to a row of source electrodes of the memory cells and at least two sets each constituted of an data write circuit and a multiplexer circuit are provided with at least one set connected to the ends of the plurality of bit lines on each side.

Abstract: A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

Abstract: A non-volatile semiconductor memory device having divided bit lines. A main bit line is controlled by at least one bit line selection device to transfer its potential to a selected sub bit line, such that memory cells in a selected sector work and overloading of the bit line generated by a parasitic capacitance can be prevented. The memory cells and the bit line selection device are arranged in parallel in a P-well and a N-well, respectively, thereby preventing disturbances during programming or erasing the bit line.

Abstract: A global input/output precharge apparatus includes a latch for cross-coupling and latching a global input/output line and a complementary global input/output line; a global input/output line delay for delaying the global input/output line and the complementary global input/output line by a predetermined time delay; a global input/output line precharge logic for pre-charging the global input/output line feed-backed from the global input/output line delay; a first precharge logic for applying a power voltage to the global input/output line when a first logic state is feed-backed on the output of the global input/output line precharge logic and applying a ground voltage to the global input/output line when a second logic state is feed-backed on the output of the global input/output line precharge logic; and a second precharge logic for applying the power voltage to the complementary global input/output line when the first logic state is feed-backed on the output of the global input/output line precharge logic an

Abstract: A voltage reference circuit is provided in the periphery of a memory array. Each subarray of the memory array is associated with a respective voltage driver circuit responsible for generating the cell plate and equilibrate reference voltage for the memory cells in the subarray. The voltage reference circuit is connected to and controls each voltage driver so that each driver generates the proper reference voltage. The distributed circuitry substantially reduces the amount of space used within the memory array while mitigating the problems of prior art voltage generator circuits.

Abstract: Embodiments of the invention provide a command decoder and related circuitry for use in a semiconductor memory device that can operate both as a double rate synchronous dynamic random access random access memory device, and a fast cycle random access memory device.

Abstract: An information recording medium for reproducing information by irradiation with a laser beam condensed by an objective lens with a numerical aperture NA includes a disk-shaped substrate and a recording layer disposed on the substrate. On the surface of the substrate, a plurality of prepit regions (110) and a plurality of data regions (120) are disposed alternately along spiral or concentric virtual track centers. Each prepit region includes a pair of wobble pits (113) for tracking servo. and a length L (&mgr;m) of the wobble pit along the virtual track center, a wavelength &lgr; (&mgr;m) of the laser beam, and a numerical aperture NA satisfy a relationship: 0.3≦L.NA/&lgr;≦0.

Abstract: The invention relates to a network with a first plurality of logic channels with which is associated a second plurality of transport channels,

Abstract: The present invention prevents production of residue which causes short-circuit between word lines. A memory cell comprises a channel formation region CH, charge storage films CSF each comprised of a plurality of stacked dielectric films, two storages comprised of regions of the charge storage films CSF overlapping the two ends of the channel formation region CH, a single-layer dielectric film DF2 contacting the channel formation region CH between the storages, auxiliary layers (for example, bit lines BL1 and BL2) formed on two impurity regions S/D, two first control electrodes CG1 and CG2 formed on the auxiliary layers with dielectric film interposed and positioned on the storages, and a second control electrode WL buried in a state insulated from the first control electrodes CG1 and CG2 in a space between them and contacting the single-layer dielectric film DF2.

Abstract: To manufacture FeRAM memories in a particularly space-saving fashion and, thus, increase the storage density, a manufacturing method forms at least some of the multiplicity of capacitor devices used as storage elements with a multiplicity of individual capacitors that are connected in parallel with one another. The individual capacitors have ferroelectric or paraelectric dielectric regions with different coercitive voltages such that there is a resulting multiplicity of storage states for each of the individual capacitors.

Abstract: A self aligned method of forming a semiconductor memory array of floating gate memory cells in a semiconductor substrate, along with strap regions interlaced within the array. The array includes word lines and source lines that connect together control gates and source regions from memory cells contained in row within the array. The strap regions include word line strap cells through which the word lines traverse, wherein the word lines completely traverse across the strap regions, and source line strap cells in which the source lines terminate without completely traversing across the strap region. The control gate polysilicon is formed over the substrate, and protected by a layer of protective material, before the formation of other polysilicon elements associated with the memory array, to ensure the proper remove of residual polysilicon stringers.

Abstract: A flash memory array architecture. In one embodiment, a flash memory device comprises a first and second bank. Each bank has a pair of quadrants of memory cells. Each quadrant has a redundant fuse circuit to store operating parameters. Moreover, each redundant fuse circuit is coupled within an associated quadrant to reduce routing of signal lines. Each quadrant further has a sense amplifier circuit to read the memory cells.

Abstract: A memory device includes a plurality of memory cells arranged as a matrix. Each memory cell includes a transistor and a capacitor connected in series. Each memory cell is linked to a bit line that connects the memory cells of a column. Each memory cell is also linked to a word line and to a third line. A gate of the transistor of a memory cell is linked to the word line, with each word line being linked to the gates of the transistors in a respective column. A third line is linked to the sources of the transistors of a row of memory cells. A bit line is linked to the capacitors of the transistors of a column. The voltage between the gate and the source of a transistor can thus be controlled via the word column and the third line.

Abstract: A memory storage and retrieval device, comprising:

Abstract: The present invention provides a ferroelectric memory device and a manufacturing method forming the same capable of preventing characteristic deterioration of a ferroelectric layer due to an plasma. The ferroelectric memory device divided into a first area including a plurality of ferroelectric capacitor and a second area not including the ferroelectric capacitor, includes a semiconductor substrate; a first insulating layer formed on the semiconductor substrate; and a bottom electrode of the ferroelectric capacitor formed in the first insulating layer, wherein a top surface of the bottom electrode is planarized with the first insulating layer; a ferroelectric layer of the ferroelectric capacitor covering not only the bottom electrode but also all the first area; and a top electrode of the ferroelectric capacitor formed on the ferroelectric layer and overlapped with the bottom electrode.

Abstract: An optical device includes: a complex photonic crystal in which a plurality of materials with different refractive indices are placed periodically, whereby a plurality of photonic crystals with a periodic refractive index distribution are arranged in a column in a direction of a common primitive lattice vector; an ingoing optical waveguide for allowing light to be incident upon the complex photonic crystal; and an outgoing optical waveguide for receiving light output from the complex photonic crystal.

Abstract: In order to be able to carry out the testing of integrated semiconductor memory devices particularly rapidly, it is proposed that the test result data of the respective memory area which are obtained in the area of the semiconductor memory device are formed, transmitted and/or stored externally in each case as a plurality of blockwise test result lists.

Abstract: An additional test mode is introduced in a semiconductor memory. A multiplicity of word lines are simultaneously activated by a word line decoder in the test mode. After a potential equalization of complementary bit lines, a logic “0” or a logic “1” is applied to an equalization circuit via a voltage generator. It is thus possible for the entire memory cell array to be preallocated an identical data value or, in strip form, alternating data values. Test time is thereby saved.

Abstract: An electrochromic molecular colorant and a plurality of uses as an erasably writeable medium. Multitudinous types of substrates, such as paper, are adaptable for receiving a coating of the colorant. Electrical fringe field or through fields are used to transform targeted pixel molecules between a first, high color state and transparent state, providing information content having resolution and viewability at least equal to hard copy document print. The scope of the invention includes both the liquid coating and the combination of coating on substrate.

Abstract: A non-volatile memory and a method of non-volatile memory programming reduced in the frequency of fault occurrence and improved in the convenience of use while realizing stable write operations and shortening the substantial length of time required for writing is provided.

Abstract: A memory cell array is constructed by a plurality of sub-arrays which include a plurality of sub-word lines, a plurality of bit lines, a plurality of plate lines and a plurality of memory cell blocks, plural ones of the sub-arrays being arranged in the sub-word line direction, a plurality of sub-row decoders provided between the plurality of respective sub-arrays, for driving the sub-word lines, a main row decoder disposed on one-end side of the plurality of sub-arrays in the sub-word line direction, and a plurality of main-block selecting lines for respectively supplying outputs of the main row decoder to the sub-row decoders. The main-block selecting lines for connecting the main row decoder to the sub-row decoders are formed of the same interconnection layer as the plate lines and metal interconnections used between the memory cells in the cell block.

Abstract: A packaged component includes a pattern generator for generating successive random data patterns. The component further includes a programmable constraint correction module, coupled to the pattern generator, to replace undesirable random data patterns with desirable bit sequences to overcome bus contention problems in the generated random data patterns. The component further includes an integrated circuit device to be functionally tested. The device receives the constrained random data patterns from the constraint correction module and outputs a test result. The device further includes a programmable X-masking module coupled to the device receives and masks the test result by replacing unpredictable bit values in the received test result with predictable bit values. A signature analyzer coupled to the X-masking module receives the masked test result and compresses the test result into a signature.

Abstract: A wafer burn-in test and a wafer test circuit for a semiconductor memory device which can cut down packaging expenses and improve F/T yield by performing a wafer burn-in test by using a pad for contact in a probe test of a wafer state.

Abstract: A semiconductor memory device that enables data buses to operate at high speed by reducing wiring capacitance and interference noise between data bus lines is provided.

Abstract: A memory refresh system and method. The inventive system includes a mechanism for selectively refreshing elements of a memory array in response to signals from a conventional memory management system. In the illustrative application, the memory is dynamic random access memory and the inventive system is adapted to provide for selective refresh of those DRAM memory elements to which data has been or will be stored. This allows for the use of advantageous DRAM memory elements while minimizing the power consumption thereof. Consequently, the utility of DRAM memory elements is extended to a variety of power sensitive applications including cellular telephony and mobile computing.

Abstract: A synchronous semiconductor memory device has a memory section which includes a memory cell array having a plurality of memory cells and which is capable of a read operation of reading information from the memory cells according to a read command and a write operation of writing information into the memory cells according to a write command. The synchronous semiconductor memory device further has a command sensing circuit which senses whether a first command inputted in synchronization with an external clock signal is the read command or the write command. The synchronous semiconductor memory device further has a bank timer circuit which, when the command sensing circuit has sensed either the read command or the write command, sets the end time of the restore operation of a row address strobe (RAS) and the start time of the precharge operation of the RAS according to the external clock signal.

Abstract: A semiconductor integrated circuit comprises an internal potential generation circuit for a memory, a current flow pass interruption circuit connected to the internal potential generation circuit, and an input terminal, connected to the current flow pass interruption circuit, for providing a stand-by setting signal controlling the current flow pass interruption circuit, wherein a potential is supplied to the internal potential generation circuit during the operation of the memory, and it is interrupted during the stand-by of the memory to supply the potential to the internal potential generation circuit.

Abstract: A semiconductor memory device using a protocol transmission method, having an improved packet structure comprises a plurality of banks having N subregions which are simultaneously accessed by activation of one row, and a memory control unit capable of accessing a predetermined subregion of the N subregions according to a predetermined field value of packet.

Abstract: Disclosed is an address input apparatus of a semiconductor memory device having a unit cell including a capacitor, comprising an internal clock generator for generating and outputting an internal clock signal at a fixed period and a buffering and sampling unit for buffering an inputted address and sampling the address in the fixed period in response to the internal clock signal.

Abstract: A circuit for generating an internal address in a semiconductor memory device which can reduce power consumption in a self-refresh operation, by generating an internal refresh address to refresh a partial array selected according to an external command includes: a counter unit having a plurality of binary counters for generating internal address signals for wholly or partially refreshing word lines of a bank according to a setup value of a memory; and a control unit for receiving a most significant signal and a second most significant signal of the counter unit, a first select signal and a second select signal for deciding a word line region of the bank to be activated, and a self-refresh signal and a refresh signal, and generating a signal for controlling the operation of the counter unit, a most significant internal address signal, and a second most significant internal address signal.

Abstract: An apparatus and method is disclosed for selecting data in a FIFO memory array made up of a plurality of memory cells arranged in rows and columns, where each row of cells has an associated number of word lines selectively addressable by an associated row address, and each column of cells has an associated bit line that provides access to the memory cells of the associated column as enabled by the respective word lines; and the memory array includes an address decoder having an address input for receiving an input address for selecting word lines in accordance with the input address, and a programmable-width vertical pointer for providing read and write input addresses to the address input of the address decoder during associated read and write operations of the memory array, where the programmable-width vertical pointer modifies the read and write addresses during operations of the memory array and provides a FIFO memory functionality.

Abstract: A spiral-type kneading machine for the preparation of flour-based mixtures comprises a non-rotating circular bowl and a spiral-shaped kneading tool rotatable inside the bowl. The spiral-shaped kneading tool has its axis substantially coincident with the axis of the bowl and occupies substantially the entire space contained within the bowl. The tool cooperates with a fixed member projecting upwardly from the bottom of the bowl and spaced from the central axis thereof.

Abstract: A deflector-mixing head for a reaction molding machine, comprises a mixing chamber with a control piston for regulation of component inflow, an overflow chamber is arranged downstream from the mixing chamber in a perpendicular position thereto and provided with a cleaning piston which controls the opening and closing of the mixing chamber side of the inlet of the overflow chamber, wherein an improved mixing quality is obtained by arranging a connection chamber substantially parallel to the axis of the overflow chamber, between the mixing and overflow chambers and provided with deflector elements positioned in the flow path between the inlet and the outlet side of the connecting chamber, and by arranging a displacement piston parallel to the cleaning piston for emptying the connection chamber.

Abstract: To solve a problem of a height at a time of stirring a laminated tube solder by a conventional apparatus, makes it easy to keep balance at a time of rotating, and improve a stirring efficiency, a pair of circular supporting plates (7, 7) are fixed to portions near both end portions of a rotation driving shaft (2) which is horizontally supported to a stand (1), the rotation driving shaft (2) is rotated by a drive motor (3), four rotary tubes (8, 8) with opening and closing lids are supported between a pair of circular supporting plates (7, 7), and the rotary tubes (8, 8) are revolved around the rotation driving shaft (2) in a vertical direction while being made rotate around their own axes respectively.

Abstract: The magnetic stirring apparatus (1p ) comprises an agitator (1a), at least one permanent magnet (1d, 1e) and a float body (1f), which are connected to one another.

Abstract: A process for mixing or dispersing liquids is provided that includes introducing liquids to be mixed or dispersed into a mixing device having a cylindrical support. The cylindrical support includes an inlet nozzle having a bore which is in fluid communication through a turbulence chamber with a bore of an outlet nozzle, wherein the bores of the nozzles are axially spaced apart relative to one another. The liquids are then allowed to enter the turbulence chamber through the bore of the inlet nozzle where the liquids are mixed or dispersed. The mixed or dispersed liquid is then recovered from the outlet nozzle. Various devices for mixing or dispersing liquids are also provided.

Abstract: A method and system for underwater detection of fully or partially buried objects such as sea mines and underwater cables, consisting of a mobile underwater platform configured with a real-time, three dimensional acoustical camera with a downward directed field of view used as an imaging interferometer, coordinated with a high-intensity, low frequency acoustical transmitter directed as to disturb the loose particulate or elastic matter comprising the seafloor within the field of view of the camera. The images recorded by the camera display the relative motion of the seafloor material before and after an acoustical pulse, in contrast to the lesser or no motion of submerged solid objects. Distinguishing man-made from natural objects is aided by recognizing geometric shapes apparent within the varying image density, not common in nature.

Abstract: A relative speed of an object is determined by monitoring random reflective surfaces in water. The system includes a first and second transmitter-receiver pair for producing echo signals of a monitored region. The monitoring pair of transducers are preferably positioned along an axis of motion of the object such that sampled data from the first and second transmitter-receiver pair are substantially similar but shifted in time due to a separation of transducers. Echo signal data from the transducers are then used to generate a time difference correlation function that is used to determine a time difference between the first and second signals. Based on the time difference between the time-shifted echo signals, a speed of a vessel is determined.

Abstract: A plurality of actuators are provided at predetermined intervals on the reverse surface of a predetermined side wall of a swimming pool. When an electric signal corresponding to a sound to be propagated in the water is given to the actuators, the electric signal is converted by the actuators into a mechanical vibration signal to cause vibrations. The actuators are secured directly to the reverse surface of the predetermined side wall by an adhesive or otherwise, and thus the vibrations of the actuators are radiated as a sound in the water of the pool through the side wall.

Abstract: An electronic timekeeping and broadcasting device for use near a user's ear while resting includes a cover portion with a speaker inside the cover, a digital voice synthesizer connected to the speaker, and an electronic clock connected to the synthesizer, and a switch connected to the synthesizer, and includes a power supply. Upon turning on the switch and activating the synthesizer, the time is broadcast from the speaker. The device enables a resting user to learn the time with the least possible effort, not even having to move his or her head or open his or her eyes.

Abstract: The present invention provides a time-temperature integrating indicator having an amorphous material in operable contact with a porous matrix, wherein the amorphous material only migrates into the porous matrix at or above a predetermined temperature. Use of the invention simplifies monitoring of the cumulative temperature exposure of the product because no additional actuation step is required. The indicator is especially useful in monitoring the cumulative time-temperature exposure of a perishable product for a short period of time at an abusive temperature.

Abstract: A wireless digital audio to AM/FM decoder and modulator capable of communicating with a radio receiver includes a short-range wireless networking transceiver using a standardized digital communications protocol to receive digital data representing audible information. A controller converts the digital data into intermediate format digital data that may be stored in a memory device. A digital to analog converter converts the intermediate format digital data into an audio frequency signal, which is transmitted by a radio frequency transmitter at very low power to the radio receiver. In an alternative embodiment, the controller converts the digital data representing audible information into a digital representation of a radio frequency signal modulated with the audible information. A radio frequency amplifier transmits the radio frequency signal at very low power to the radio receiver. In one application, the AM/FM decoder and modulator may be connected directly or wirelessly to an automobile radio antenna.

Abstract: In a preferably disc-like scannable record carrier (3) which contains at least one subcode channel, strange data not related to the disc-like record carrier (3) are stored in the at least one subcode channel. A playback device (1) for scanning such a disc-like record carrier (3) includes playback device data processing means (5, 10) which are arranged for processing strange data formed by update data, which update data are transferred to non-volatile memory means (13) for updating a routine of a function unit (12).

Abstract: An information playback apparatus which can perform scan playback capable of being performed with finer settings. When a unit cycle B and a playback time A within the unit cycle B are specified and the start of the scan playback of playback data recorded in a DVD is specified, playback control data having address information and information of the playback order appended to each piece of data in the smallest basic units of the playback data is read out from the DVD, whereby the scan playback of the playback data is performed by managing the playback time A in every unit cycle B. Also, when access-inhibited data is present within the playback data, the scan playback of playback data is performed except the access-inhibited data.

Abstract: A driving apparatus (100, 200, 300, 400, 506) for driving an actuator (507) with electric current is provided with: a current monitor device for generating a voltage corresponding to an electric current that passes through the actuator and that includes the counter electromotive force component generated according to the movement of the actuator; and a feedback device for giving negative of the generated voltage. The feedback device makes it difficult for the actuator to move by giving the negative feedback with a large gain in presence of a defect, in accessing, in a stop condition, and the like.

Abstract: In an optical disk reproducing device for reproducing the video/audio information recorded on an optical disk wherein a setup menu is displayed for setting various kinds of functions of the optical disk reproducing device and a function is selected from the displayed setup menu, assuming that an instantaneous reproduction has been selected by the selecting means, when the optical disk is loaded in the optical disk reproducing device to reproduce the video/audio information, without an opening screen and a menu screen set for the optical disk being displayed, the video/audio information is reproduced from a first chapter included in a first title of the video/audio information recorded on the optical disk.

Abstract: In a focus control for following a focus position of light beam to be radiated to an optical disk to an optical disk surface, the technique is for shorten the memory length in the learning controller. The learning controller is provided to a focus feedback control system and updates the memory comprised of N numbers of memory cells with a shorter sample period than a time obtained by dividing the time required for one rotation of the disk by N numbers and outputs the learning results in the memory with the shorter sample period.

Abstract: A signal processing circuit, which extracts a signal superimposed on a reference signal and having a peak level higher than a level of the reference signal by a value greater than a given value, includes a first pulse generation part generating a first binary signal by binarizing a composite signal of the reference signal and the superimposed signal by using a given slice level, a noise elimination part eliminating noise from the first binary signal by using a cumulative length of time of each of polarities of the first binary signal, a second pulse generation part generating a second binary signal by binarizing the composite signal by using a slice level higher than the level of the reference signal by a value smaller than or equal to the given value, and a gate part outputting the second binary signal based on a signal output from said noise elimination part.

Abstract: An optical disk apparatus for driving an optical disk on which a groove wobble corresponding to a signal acquired from frequency modulation of biphase modulated address information, and a mark for representing phase information placed inside the wobble are preformatted, and having the biphase bit count “a” (“a” is a natural number) between two of the adjacent marks, and the channel bit count “n” (“n” is a natural number) between two of the adjacent marks. The apparatus includes first clock signal production means for generating a first clock signal utilizing an “n” frequency multiple of the reproduction signal of the clock mark, wobble signal reproduction means for reproducing from the optical disk a wobble signal corresponding to the groove wobble, and frequency demodulation means for acquiring the address information by frequency demodulation of the wobble signal.