Abstract: A system and a method for acquiring and transmitting environmental information recorded around a vehicle comprising of including at least one camera. The output from the camera is encoded and stored in a storage device. The encoded signal is also transmitted wirelessly to a remote location or a server for subsequent analysis. The stored signal may also be decoded and displayed on a video display unit.

Abstract: The present invention is related to video encoding. In an embodiment, a sequence of frames is received. For each frame in at least a portion of the sequence of frames, a corresponding mean of absolute differences value weighted by a temporal parameter between frames bracketing said each frame is calculated. At least partly based on the corresponding mean of absolute differences value weighted by a temporal parameter, a first frame in the sequence of frames is skipped.

Abstract: The present invention is related to video encoding. In an embodiment, a first root mean squared (RMS) value is calculated for a first frame relative to a second frame, and a second frame relative to a third frame. A second temporal derivative RMS value is calculated. Based at least in part on the second derivative value, the second frame is designated as a scene change frame.

Abstract: A region data describing method for describing, over a plurality of frames, region data about the region of an arbitrary object in a video, the method specifying the object region in the video with at least either of an approximate figure approximating the region or characteristic points of the region, approximating a trajectory obtained by arranging position data of the representative points or the characteristic point in a direction in which frames proceed with a predetermined function and describing the parameter of the function as region data. Thus, the region of a predetermined object in the video can be described with a small quantity of data. Moreover, creation and handling of data can easily be performed.

Abstract: MPEG coded video data includes groups of pictures (GOPs). Each group of pictures includes one or more I-frames and a plurality of B- or P-frames. To produce an MPEG slow-forward coded video stream, the coding type of each frame in the MPEG coded video data is identified, and freeze frames are inserted as a predefined function of the identified coding type and as a predefined function of a desired slow down factor. In a preferred implementation, for a slow-down factor of n, for each original I- or P-frame, (n−1) backward-predicted freeze frames are inserted, and for each original B-frame, (n−1) copies of the original B-frames are added, and a selected amount of padding is added to each copy of each original B-frame in order to obtain a normal play bit rate and avoid video buffer overflow or underflow.

Abstract: Adjacent regions are identified in an image. Coding parameters for the adjacent regions are identified. Selective filtering is performed at the region between the identified adjacent regions.

Abstract: In a motion estimation method for use in encoding a moving picture, a full-pixel motion vector is estimated by stochastically sampling a pixel to be processed in a predetermined-sized block of a previous frame or a next frame as a reference frame for each of a plurality of equal-sized blocks in a current frame. Then, a half-pixel motion vector is estimated based on the full-pixel motion vector. Accordingly, both the calculation amount and the calculation time required for the motion estimation are effectively reduced. Further, it can be prevented that the hardware becomes complicated.

Abstract: The present invention provides an improved motion estimation encoder for digital video encoding applications. In one example embodiment, the improved encoder receives a raw image in the form of a current frame and estimates the macroblock motion vector with respect to a reference frame. The encoder then performs an initial local search around an initial motion vector candidate derived from spatio-temporal neighboring macroblock parameters. The encoder then compares the user-defined complexity scalable sum of absolute difference between the original and the associated reference macroblock against an adaptive threshold value for motion estimation convergence. The encoder introduces a global full search around a candidate from a coarser level, in case an initial local search fails.

Abstract: A method and apparatus for performing motion estimation under a motion estimation mode suitable for an amount of motion within each E-block detects a motion vector with a small amount of computation. A block division section 102 divides a frame to be encoded into E-blocks of a predetermined pixel size. For each target E-block, a motion estimation mode detection section 105 relies on a past motion vector of a predetermined block to predict an amount of motion, and determines a motion estimation mode defining a search area that enables detection of the predicted amount of motion among a plurality of predefined motion estimation modes. If the predicted amount of motion is small, a mode defining a narrow search area and a fine search resolution is selected. If the predicted amount of motion is large, a mode defining a broad search area and a coarse search resolution is selected.

Abstract: A motion estimation system for a video coder is disclosed. The system comprises an input for a video image (6) to be coded. It also comprises a series of motion estimators (2, 3) of varying complexity, for estimating a motion vector field between the received image (6) and a reference image (5). The subsequent motion estimator in the series is selected by a control means (4) if a prediction error associated with the motion vector field estimated by the currently selected motion estimator exceeds a predetermined threshold.

Abstract: The disclosed invention is a method to detect candidate errors within the picture start code, picture header, and picture timestamp. Upon detection, these errors may be confirmed and the impacts mitigated. An error within the timestamp bit field is adaptively detected by the use of a threshold comparison, and a mechanism for concealing the timestamp information leaves only a small timestamp anomaly. An error within the picture start code (PSC) is determined by adaptively analyzing the number of bits and the macro-block location of the next slice or GOB. If a PSC is suspected to have been overrun due to an error, this method allows for data beyond the first GOB or slice to be recovered in the frame. Depending on the extent of use of slices and GOBs, the method can recover a majority of the frame that otherwise would have been completely lost.

Abstract: In a serial interface unit (10) for the transmission and reception of data under the control of clock signals, the data are output from a data source to a data output (24) via an output driver (22). A transmit monitor (52) compares the data supplied by the data source with the data received at the data output (24) via the output driver (22). The transmit monitor outputs an error signal when the data so compared do not coincide.

Abstract: A system for transmitting, receiving, recovering, and reproducing digitized samples of analog signals while concealing unrecoverable digitized samples of analog signals to maintain a level of fidelity in reproducing the analog signals. The digitized samples of the analog signals are burst transmitted such that the probability of interference with the transmission and thus corruption of the digitized samples of the analog signals is minimized. The digitized samples are received without synchronizing a receiving clock with a transmitting clock to capture the digitized samples of the analog signals. The digitized samples are converted from various sampling rates to digitized samples of the analog signals having a rate. Any large groups of digitized samples that are in error or corrupted in transmission are softly muted to avoid annoying clicks.

Abstract: Channel quality estimating section 104 estimates the channel quality from the reception signal quality and outputs the result to transmission method determining section 105 and control signal dividing section 108. Transmission method determining section 105 determines a transmission method of a signal transmitted to communication partner from channel conditions and outputs the result to switch 106, switch 107 and control signal dividing section 108. Control signal dividing section 108 divides the transmission method information into high-speed control signal which is transmitted periodically and low-speed control signal which is transmitted on demand rather than periodically. Moreover, control signal dividing section 108 determines the combinations of low-speed control signal and high-speed control signal outputted from a tendency of communication quality, and outputs the result to modulator 114.

Abstract: The system for recovering symbol timing offset and carrier frequency error from an orthogonal frequency division multiplexed (OFDM) signal includes a receiver circuit for receiving an OFDM modulated signal representing a series of OFDM symbols, and providing a received signal to an output thereof. A peak development circuit is included for developing a signal having a plurality of signal peaks representing symbol boundary positions for each received OFDM symbol, where each of the signal peaks is developed responsive to an amplitude and phase correspondence produced between the leading and trailing portions of each of the received OFDM symbols. The system includes a circuit for enhancing the signal peak detectability, which includes a circuit for additively superimposing and then filtering the signal peaks, to produce an enhanced signal peak having an improved signal-to-noise ratio.

Abstract: A method and apparatus for re-modulating an RF carrier modulated signal using a Nyquist folding frequency modulation technique. The method modulates a digitized RF carrier modulated signal with a digital sequence of {1, −1, 1, −1, . . . }, where the center frequency of the RF carrier modulated signal is at a first frequency and the sample rate of the modulating signal is at a second frequency. When the second frequency is four times the first frequency, the output of the digital modulation process is a spectrum-inverted copy of the source RF carrier modulated signal. For all other frequencies, the remodulated RF carrier modulated signal has a center frequency equal to the carrier frequency minus one-half the sample rate of the modulating signal. A spectrum inversion is then performed to recreate the spectrum of the source RF carrier modulated signal, which is now located at a different center frequency. The apparatus comprises a modulating signal source and a digital modulator.

Abstract: A distortion compensator for compensating for distortion produced in an amplifier that amplifies a signal includes a signal level detection means for detecting a level of a signal to be amplified and distortion compensation means for conducting distortion compensation based on the detection result separately for each frequency band signal of multiple frequency band signals contained in the signal to be amplified. The distortion compensator improves distortion compensation performance by reducing the effect of frequency characteristics that restrict the distortion compensation performance limit.

Abstract: A subscriber unit has a processor. The processor provides an output phase signal corresponding to a selected output digital frequency. A tuning register buffers the phase signal. A lookup table has two sets of predefined stored values pertaining to the amplitude of a signal for a single quadrant. The predefined stored values comprise coarse angle approximations and fine angle approximations. A sine and cosine generator receives the phase signal and generates sine and cosine waveforms utilizing amplitude values obtained from the lookup table. The phase signal includes phase data and specifies the quadrant and the algebraic sign of the phase data. The sine and cosine generator accessing the lookup table differently depending upon the quadrant and sine of the phase data, such that the lookup table provides an amplitude value from the sets of predefined stored values based on the phase data.

Abstract: An ultra wide bandwidth, high speed, spread spectrum communications system uses short wavelets of electromagnetic energy to transmit information through objects such as walls or earth. The communication system uses baseband codes formed from time shifted and inverted wavelets to encode data on a RF signal. Typical wavelet pulse durations are on the order of 100 to 1000 picoseconds with a bandwidth of approximately 8 GHz to 1 GHz, respectively. The combination of short duration wavelets and encoding techniques are used to spread the signal energy over an ultra wide frequency band such that the energy is not concentrated in any particular narrow band (e.g. VHF: 30-300 MHz or UHF: 300-1000 MHz) and is not detected by conventional narrow band receivers so it does not interfere with those communication systems.

Abstract: An ultra wide bandwidth, high speed, spread spectrum communications system uses short wavelets of electromagnetic energy to transmit information through objects such as walls or earth. The communication system uses baseband codes formed from time shifted and inverted wavelets to encode data on a RF signal. Typical wavelet pulse durations are on the order of 100 to 1000 picoseconds with a bandwidth of approximately 8 GHz to 1 GHz, respectively. The combination of short duration wavelets and encoding techniques are used to spread the signal energy over an ultra wide frequency band such that the energy is not concentrated in any particular narrow band (e.g. VHF: 30-300 MHz or UHF: 300-1000 MHz) and is not detected by conventional narrow band receivers so it does not interfere with those communication systems.

Abstract: Canceling images in a quadrature modulator includes frequency shifting the baseband signal and images; filtering the frequency shifted baseband signal and images; phase and frequency shifting the baseband signal and images; filtering the phase and frequency shifted baseband signal and images; combining the filtered frequency shifted baseband signal and images with the filtered phase and frequency shifted baseband signal and images to suppress the negative frequency images and isolate the modulated baseband signal.

Abstract: A concatenated coding scheme, using an outer coder, interleaver, and the inner coder inherent in an FQPSK signal to form a coded FQPSK signal. The inner coder is modified to enable interative decoding of the outer code.

Abstract: A digital down converter is provided. The digital down converter includes an input adapted to receive an input signal, a mixer circuit coupled to the input to down convert the input signal, and a decimation circuit, coupled to the mixer. The decimation circuit is adapted to decimate the down converted signal by a factor selected based on a characteristic of the input signal. The digital down converter further includes a signal conditioning circuit, coupled to the output of the decimation circuit, that conditions the decimated signal, an interpolator, coupled to the decimation circuit, that increases the number of samples in the conditioned signal, and a second mixer circuit, coupled to the interpolator, the second mixer circuit adapted to modulate a carrier with the conditioned signal.

Abstract: A frequency offset estimation based on state-based differential accumulation and the device thereof are disclosed. The concept of the sate-based operation is introduced by mathematical derivations. The knowledge of received data symbols and timing is utilized. Then the detailed operations are also given by both equations and conceptual descriptions. It is unnecessary to estimate the channel jointly or concurrently, while the differential operation over the received samples of the same state is performed. Such operation is obviously much simpler and easier to implement in VLSI than all the other techniques.

Abstract: This apparatus comprises a receiver called Rake receiver comprising delay lines (L1 to LN) for processing data transmitted in symbols along a plurality of paths (T1 to TN), a symbol processing circuit (40) which produces the information from said delay circuits, followed by an alignment module (30). The processing circuit (40) processes the symbol that is predominantly found in delay circuits. In this way its value is estimated better.

Abstract: A method of tuning a station is disclosed, wherein a first pilot signal is applied on a circuit of the station and the resulting output power of the signal circuit is subsequently detected. A second pilot signal is then applied to the circuit and the resulting output power of the circuit is detected. The offset of the circuit is then tuned based on information of the resulting output power detected for the first and second signals. A station that is adapted to implement the method may be tuned by the manufacturer thereof or later after having already been taken into use. The tuning may occur automatically as response to a predefined event.

Abstract: The component, fully integrated onto a monolithic substrate, includes a tuner, a demodulator, and a channel decoder. The overall filtering is carried out in two parts, a baseband analog filtering and a digital Nyquist filtering removing the information of adjacent channels. It outputs a stream of MPEG data.

Abstract: The present invention offers a low cost, reliable, on chip implementation that takes advantage of circuitry already present in receivers to calibrate and correct for gain and phase errors in a transciever device. The present invention employs a digital signal processor along with multiple phase shifters and all pass networks to ensure proper levels of quadrature signals within the transciever. An internally generated double sideband suppressed carrier signal is created to produce the calibration signals used by the digital signal processor.

Abstract: Digital communication signals that encode information in the phase may be susceptible to phase error from many sources. The invention corrects for carrier and sampling phase errors, as well as additive phase noise. A digital phase locked loop simultaneously tracks the carrier phase error and the sampling phase error, and corrects the signal in the frequency domain. The invention may use the sampling phase error to advance or delay the sampling window used to convert the signal from the time domain to the frequency domain.

Abstract: A multi-channel serializing/deserializing (“serdes”) receiver, a method of operating the receiver and an integrated circuit configured as a serdes receiver. In one embodiment, the receiver includes: (1) a PLL-based central frequency synthesizer and (2) a plurality of channel-specific receivers coupled to the central frequency synthesizer, each of the plurality including a clock recovery system having a phase detector and a phase interpolator, the clock recovery system coupling the phase detector and the central frequency synthesizer.

Abstract: A method and an apparatus for determining the log-likelihood ratio of a received signal. The log-likelihood ratio is determined by calculating distance between the received symbol and closest constellation point matching a bit and the distance between the received symbol and the closest constellation point not matching the bit.

Abstract: A power control circuit comprises a first SIR measurement section which obtains separate SIR measurement values for a plurality de-spread signals, a combining section which combines the plurality of de-spread signals, a second SIR measurement section which obtains an SIR measurement value for the signal combined in the combining section, an observation section which observes fluctuations in the separate SIR measurement values and the SIR measurement value; and a control section which controls transmitting power of the de-spread signal based on observation results from the observation section.

Abstract: A decoder rescales state metric values to avoid overflow by resetting a bit in state metric registers that store the state metric values for each state. For example, the decoder may monitor a most significant bit (MSB) of the state metric registers to determine when the state metric values for all of the states exceed a threshold value. Upon exceeding the threshold value, the decoder may rescale the state metric values to avoid overflow. For instance, when the state metric values exceed the threshold value, the MSBs of the state metric registers may be reset. Resetting the MSBs is equivalent to subtracting half of the maximum value of the state metric register. The resealing technique can prevent state metric value overflow while offering reduced complexity and reduced latency.

Abstract: A receiver and a method for a receiver is disclosed. The receiver comprises a signal processing path for receiving a first signal modulated by a first modulation method and having a first bandwidth and a second signal modulated by a second modulation method and having a second bandwidth. A common gain control function is provided for processing said first and second signals. A common DC offset cancellation is also provided for said first and second signals. In a preferred embodiment the gain control and the DC offset cancellation a provided by a single circuit.

Abstract: Logic apparatus filters noise signals on a signal line to a digital circuit. An edge detector determines one or more edges of the noise signals relative to a fast clock. Signals indicative of the edges asynchronously reset a timer; the timer clocks the latch of the signal line when the signal line is stable, and without noise signals detected by the edge detector, for a period defined by a slow clock. The slow clock is slower than the fast clock by several orders of magnitude. The edge detector may be constructed by one flip-flop and an XOR gate. A second flip flop couples to the signal line and the output of the timer to pass through the latched value of the signal line to the digital circuit when clocked by the timer.

Abstract: A method for initializing an equalizer in an Orthogonal Frequency Division Multiplexing (“OFDM”) receiver includes generating a desired equalizer tap setting based on an adaptive algorithm. An initial setting for the adaptive algorithm corresponds to an approximate inverse of a channel estimate, and the desired tap setting corresponds to an ideal inverse of the channel estimate. In an alternative embodiment, a method includes generating a channel estimate, generating an equalizer tap setting based on a complex conjugate of the estimate and a quantized magnitude squared of the estimate, and repeatedly generating subsequent tap settings until an error falls within limits.

Abstract: A system and method of implementing precision time delays that provides important and novel improvements over prior techniques of implementing time delays by utilizing a new strategy for selecting the values in the sine and cosine lookup tables. Sine and cosine values which result in non-uniform amplitudes enable increased overall accuracy with fewer bits communicated from the look-up tables to the analogue portion of the system. Further, herein is provided the addition of a variable amplitude threshold crossing capability following the combining of the sine and cosine signals The time delay accuracy of the resulting phase and amplitude hybrid system can be improved either by increasing the number of bits in the sine/cosine phase management section or by increasing the number of bits in the amplitude section. There is provided herein an optimum strategy for choosing the number of bits used in the phase and amplitude sections for the best overall delay accuracy with the fewest overall control bits.

Abstract: A microcontroller has a central processing unit coupled with a control unit for controlling a transmission bus. The transmission bus has at least one data and one clock signal with recessive and dominant states. The system comprises a bus controller for controlling a data and a clock line, a stretch control unit coupled with the clock line of the bus receiving a stretch activation signal, and a delay unit for delaying the stretch activation signal until a transition from a recessive to a dominant state on the clock line takes place. The bus can be an I2C-bus.

Abstract: A method for sampling a data stream (22) includes receiving a segment of the data stream containing a sequence of known data, together with a source-synchronous clock signal (20), and generating a series of trial sampling clocks (60) by applying a corresponding series of different trial delays to the received clock signal The received segment of the data stream is sampled using each of the trial sampling clocks in turn to generate sampled data. The known data are compared to the sampled data to find comparison results for each of the trial sampling clocks. Responsive to the comparison results, a final delay is set, to be applied to the received clock signal so as to generate a final sampling clock for use in sampling the data stream subsequent to the segment.

Abstract: The invention relates to a circuit arrangement for a receiver for receiving bursts of a non-continuous signal, with a device for tuning to the current parameters of the signal required for evaluating a burst, in which the device for tuning is controlled in such a way that the parameters achieved at the end of a burst are extrapolated to the start of the next burst and used to evaluate it and as the starting point for further tuning, and also a transceiver for subscriber-side connection to a local wireless access network for the worldwide telecommunications network, the receiving part of which contains a circuit arrangement of this kind.

Abstract: Methods and apparatus for recovering a clock and data from a data signal. A method provides for receiving a clock signal having a first clock frequency and alternating between a first level and a second level, and receiving a data signal having a first data rate, the first data rate equal to the first clock frequency. The method also includes providing a first signal by storing the data signal when the clock signal alternates from the first level to the second level, and providing a second signal by passing the first signal when the clock signal is at the first level, and storing the first signal when the clock signal is at the second level. A third signal is provided by delaying the data signal an amount of time. An error signal is provided by combining the first signal and the third signal, and a reference signal is provided by combining the first signal and the second signal.

Abstract: A delay locked loop of the present invention which synthesizes data and a clock inputted from outside has: voltage control delay loops having a plurality of delay circuit parts sequentially delaying the clock; a slot selector selecting a slot outputted from the delay circuit parts of the voltage control delay loops; a clock tree part creating a plurality of clocks with the same timing by an output of the slot selector; a phase control part phase-controlling the plurality of delay circuit parts corresponding to the output clock delay variation of the clock tree part; and sensing means on-off controlling all or part of the plurality of delay circuit parts and the slot selector.

Abstract: An electronic apparatus for receiving source synchronous signals is provided. The receiver continuously monitors the phase relationship between each data signal and the source synchronous clock signal. In this manner, the electronic apparatus can compensate for phase discrepancies that occur over time without having to interrupt any data operations.

Abstract: This invention is a reactor and system with a method for containing and controlling a deuterium nuclear fusion reaction in a palladium host metal lattice, now generally referred to as ‘solid state fusion’. The reactor is designed for high temperature operation at moderate deuterium gas pressures and is operable over a temperature range of 400° C. to more than 1400° C. The solid state fusion reaction is enabled and controlled by providing specific combinations of reactor temperatures and deuterium gas pressures. The invention is capable of generating heat densities that are suitable for commercial applications. The highest heat densities are produced at higher temperatures and moderate pressures where the system is most efficient and cost effective.

Abstract: Processes for modeling photons, electrons, protons, neutrons and atomic nuclei and processes for analyzing light and other radiation, subatomic particles, atoms, molecules and the entire universe and its evolution. The present invention describes two new “things” that are offered as the basic building blocks of everything in the universe. These things are called “trons”. There are two types of trons, a plus tron and a minus tron. Trons have no mass but they have a charge equal to the electron charge of about +1.6×10−19 Coulomb for the plus tron and about −1.6×10−19 Coulomb for the minus tron. Six trons (such as the trons making up three photons [each photon comprised of a plus tron and a minus tron] combine to produce a single positron and a single negatron. The positron is modeled as a minus tron orbited by two plus trons and a negatron (the negative electron) is modeled as a single plus tron orbited by two minus trons.

Abstract: A control rod for a BWR according to the present invention comprises a first unit composed of a tie rod, a handle mounted on an axially upper portion of the tie rod and a lower support member or falling speed limiter mounted on a axially lower portion of the tie rod; and a second unit composed of a sheath containing therein reactivity control material, an upper end plate mounted on an axially upper portion of the sheath and a lower end plate mounted on an axially lower portion of the sheath, wherein an upper portion of the upper end plate is fixed to the handle, a lower portion of the lower end plate is fixed to the lower support member or falling speed limiter, whereby the control rod is constructed as a joined body of the first unit and the second unit.

Abstract: A fuel channel box manufacturing method processes a fuel channel box of a zirconium-base alloy by a beta-quench treatment that heats the fuel channel box by a heating coil. The distance between the heating coil and the opposite walls of the fuel channel box is controlled so that temperature differences between the opposite walls of the fuel channel box are reduced. The fuel channel box of a zirconium-base alloy is heated at a temperature in a temperature range including &bgr;-phase temperatures so that temperature difference between the opposite walls is 50° C. or below. The fuel channel box manufacturing method is capable of manufacturing a fuel channel box that is not subject to significant irradiated bow even if a deflection is produced therein originally when the same is manufactured and of manufacturing the fuel channel box at a high production efficiency.

Abstract: A fuel assembly for a pressurized-water reactor includes fuel rods held in cells of spacers, control rod guide tubes, and a headpiece and a foot piece, by which it is fixed to upper and lower core grids, respectively. A spacer having a first part, which lies on a radially outer side with respect to a longitudinal center axis of the fuel assembly, and a second part, which lies on a radially inner side and is completely surrounded by the first part are included to reduce the size of gaps between fuel assemblies. The second part is formed of Zircaloy. The first part is made of a metallic material, and when compared to the Zircaloy of the second part, has a lower growth in the radial direction, caused by neutron radiation and a higher coefficient of thermal expansion.

Abstract: A spacer grid with hybrid flow-mixing devices for nuclear fuel bundle is made up of an intersection of a plurality of thin straps at right angles to form a plurality of cells for receiving and supporting fuel rods. Each strap is composed of two types of strap units, called a primary strap unit and a secondary strap unit, which are alternately arranged along the strap. The primary strap unit is a strap section having a primary vane set, and a secondary strap unit is a strap section having a secondary vane set. The straps intersect such that, by primary and secondary strap units, each intersection forms a hybrid flow-mixing device around the top of each junction. The primary vane set, consisting of a trapezoidal primary vane stand and two bent primary mixing vanes on both sides, protrudes upwardly from the strap and is primarily for generating cross flow between channels.

Abstract: The present invention provides an overflow detector for a FIFO. The FIFO includes a plurality of registers each having an input and an output, a plurality of write signals each respectively coupled to a clock, one of the plurality of registers, and a plurality of read switches each respectively coupled to an output of one of the plurality of registers, each of the plurality of read switches being controlled by a respective read signal. The overflow detector includes a plurality of clocked registers each of which is coupled to receive a write signal and its corresponding read signal, wherein each clocked register records a read signal and is clocked by the corresponding write signal.