Abstract: A door operating apparatus is provided for safely and efficiently opening and/or closing a side door of a railway boxcar by moving a door engagement member laterally.

Abstract: In a hoisting/pulling device comprising a pinion gear 4, reduction gears 5a which are meshed with the pinion gear 4 and are rotatably mounted in a frame 1, and a load sheave which is interlocked with reduction gears 5b and is rotatably mounted in a frame, reduction gear bearings 8 are contiguously formed with a load sheave bearing 7 which is formed in the center of the frame 1. By making the distance between the axes of the reduction gears small and by forming the load gear and the load sheave integrally, it becomes possible to provide the hoisting/pulling device which can make the whole device compact and light-weighted and can reduce the number of parts and man-hours for machining.

Abstract: A guard rail system fabricated from standard-sized components, preferably extruded, comprises balusters fastened to a lower rail and to an upper retainer at fixed intervals. The balusters are provided with central bores for receiving fasteners such as screws through predrilled holes in the upper retainer and lower rail. A hand rail is slip-fitted over the upper retainer in locking relation, to provide integrated guard rail sections. Guard rail sections so assembled are fastened to end posts, preferably using mounting brackets having a flanged arm which nests in grooves or recesses in the upper retainer and lower rail to provide a safe, secure and aesthetically appealing guard rail.

Abstract: A semiconductor device having a solid-state image sensor is provided in which the leakage current is less likely to occur. The surface portion of a P-type semiconductor substrate (1) is susceptible to various defects, which are likely to cause the leakage current. Accordingly an N-type buried channel layer (7a) is provided. While the potential is high in the vicinity of the surface of the P-type semiconductor substrate (1) where defects are present, the potential is minimized in the vicinity of the PN junction plane formed by the N-type buried channel layer (7a) and the P-type semiconductor substrate (1). Accordingly, when a transfer switch (M1) is operated, a channel is formed in the vicinity of this PN junction plane, so that a charge stored in an N-type source region (4a) of the photodiode (PD) can be transferred to an N-type drain region (5) without suffering leakage current.

Abstract: A solid state dc-SQUID includes a superconducting loop containing a plurality of Josephson junctions, wherein an intrinsic phase shift is accumulated through the loop. In an embodiment of the invention, the current-phase response of the dc-SQUID sits in a linear regime where directional sensitivity to flux through the loop occurs. Changes in the flux passing through the superconducting loop stimulates current which can be quantified, thus providing a means of measuring the magnetic field. Given the linear and directional response regime of the embodied device, an inherent current to phase sensitivity is achieved that would otherwise be unobtainable in common dc-SQUID devices without extrinsic intervention.

Abstract: Operating margins of a semiconductor integrated circuit are reliably tested at low power consumption by switching power supply circuits between normal operation mode wherein a first step-up power supply serves both memory core and a step-down power supply, and testing mode wherein the memory core is powered by an external testing power supply that provides a fluctuating voltage for testing, and the step-down power supply is served by a second step-up power supply.

Abstract: Test circuits located on semiconductor die enable a tester to test a plurality of die/ICs in parallel by inputting both stimulus and response patterns to the plurality of die/ICs. The response patterns from the tester are input to the test circuits along with the output response of the die/IC to be compared. Also disclosed is the use of a response signal encoding scheme whereby the tester transmits response test commands to the test circuits, using a single signal per test circuit, to perform: (1) a compare die/IC output against an expected logic high, (2) a compare die/IC output against an expected logic low, and (3) a mask compare operation. The use of the signal encoding scheme allows functional testing of die and ICs since all response test commands (i.e. 1-3 above) required at each die/IC output can be transmitted to each die/IC output using only a single tester signal connection per die/IC output. In addition to functional testing, scan testing of die and ICs is also possible.

Abstract: Nickel is selectively held in contact with a particular region of an amorphous silicon film. Crystal growth parallel with a substrate is effected by performing a heat treatment. A thermal oxidation film is formed on the silicon film by performing a heat treatment in an oxidizing atmosphere containing a halogen element. During this step, in the silicon film, impurities included such as oxygen or chlorine, are segregated with extending along the crystal growth, the crystallinity is improved, and the gettering of nickel element proceeds. A thin-film transistor is formed so that the direction connecting source and drain regions coincides with the above crystal growth direction. As a result, a TFT having superior characteristics such as a mobility larger than 200 cm2/Vs and an S value smaller than 100 mV/dec. can be obtained.

Abstract: A light emitting diode device has a body having a recess. The body comprises a pair of half bodies made of metal, an insulation layer provided between the half bodies. An LED is mounted on a bottom of the recess and connected with the half bodies by bumps. The recess is closed by a transparent sealing plate.

Abstract: A group III nitride compound semiconductor light-emitting element of a flip chip bonding type for emitting light with a wavelength not longer than 400 nm is coupled to a Zener diode, and the light-emitting element and the Zener diode coupled to each other are sealed with a metal casing having a window.

Abstract: In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact, the contact formed on a substrate. An electrode is conformally deposited on a wall of the dielectric, utilizing atomic layer deposition (ALD). A programmable material is formed on the electrode and a conductor is formed to the programmable material. In an aspect, a barrier is conformally deposited utilizing ALD, between the electrode and the programmable material.

Abstract: A GaN-based Schottky diode includes a sapphire substrate on which are formed a GaN buffer layer, an n+-type GaN layer, and an n-type GaN layer that has a surface portion thereof shaped to form a protrusion having an upper face with which a Ti electrode forms a Schottky junction and a side face with which a Pt electrode forms a Schottky junction through an Al0.2Ga0.8N layer. A cathode electrode constituted by a TaSi layer forms an ohmic junction with the n+-type GaN layer. The Ti and Pt electrodes constitute a combined anode electrode contributing to increasing a withstand voltage of and decreasing an on-voltage of the Schottky diode.

Abstract: An improved APD structure and an improved manner of operating APD's particularly beneficial for a single photon detection applications are provided. An APD is provided having an absorption region, a control region, and a multiplication region, wherein the multiplication region has a k value of approximately 1. In one example the multiplication region comprises a doped InP layer. The field control layer is designed so as to produce a reduction of electric field that is equal to the multiplication region's breakdown electric field, plus or minus 5V/&mgr;m. The method comprises applying a potential across the APD so as to induce an electric field across the multiplication region that exceeds the breakdown field; while having the control region shield the absorption region to prevent excessive noise.

Abstract: The resist material contains a photo-acid generator having an absorption peak to exposure light having a wavelength of less than 300 nm, and a second photo-acid generator having an absorption peak to exposure light having a wavelength of 300 nm or more. The method for forming a resist pattern comprises a step for selectively exposing which exposes a coating film of the resist material to an exposure light having a wavelength of less than 300 nm, and a step for selectively exposing by using an exposure light having a wavelength of 300 nm or more. The semiconductor device comprises a pattern formed by the resist pattern. The method for forming a semiconductor device comprises a step for forming a resist pattern on an underlying layer by the aforementioned manufacturing method, and a step for patterning the underlying layer by etching using the resist pattern as a mask.

Abstract: A high-speed heterojunction bipolar transistor in a large injection of electrons from the emitter and a method for production thereof. In a typical example of the SiGeC heterojunction bipolar transistor, the collector has a layer of n-type single-crystal Si and a layer of n-type single-crystal SiGe, the base is a layer of heavily doped p-type single crystal SiGeC, and the emitter is a layer of n-type single-crystal Si. At the heterointerface between the layer of n-type single-crystal SiGe and the layer of p-type single-crystal SiGeC, the bandgap of the p-type single-crystal SiGeC is larger than that of the layer of n-type single crystal SiGe. Even though the effective neutral base expands due to an increase in electrons injected from the emitter, no energy barrier occurs in the conduction band at the heterointerface between the layer of n-type single-crystal SiGe and the layer of p-type single-crystal SiGeC.

Abstract: The invention provides a capacitance element, its manufacturing method, a semiconductor device and its manufacturing method in which ferroelectric films can be readily processed, the generation of voids in dielectric films is restrained, and the coverage of films above the capacitance elements are enhanced. A method for manufacturing a capacitor element in accordance with the present invention includes: forming a bottom electrode on an element isolation film, forming a first interlayer dielectric film on the bottom electrode, forming trenches located on the bottom electrode in the first interlayer dielectric film, depositing a ferroelectric film in the trenches and on the first interlayer dielectric film, depositing a conductive film on the ferroelectric film and in the trenches, and embedding ferroelectric films and top electrodes in the trenches by polishing the conductive film, the ferroelectric film and the first interlayer dielectric film by a CMP method.

Abstract: The present invention relates to an interconnect structure for an integrated circuit (1) having a first interconnect (B1; B1′; B1″), which is composed of a plurality of interconnect sections (A11-A16; A11′-A16′; A11″-A14″) lying in a first and a second interconnect plane (M0, M1); and a second interconnect (B2; B2′; B2″), which runs adjacent to the first interconnect (B1; B1′; B1″) and which is composed of a plurality of interconnect sections (A21-A25; A21′-A25′; A21″-A23″) lying in the first and second interconnect planes (M0, M1); the first and second interconnects (B1; B1′; B1″; B2; B2′; B2″) being offset with respect to one another in the longitudinal direction in such a way that the interconnect sections (A12, A14, A16; A12′, A14′, A16′; A12″, A14″) of the first interconnect (B1; B1′; B1″) which lie in the first interconnect plane (M0) run at least in secti

Abstract: In a multi-chip module semiconductor device (1), at least one first semiconductor die (20) is mounted on the base portion (11) of a lead-frame (10). A flip chip IC die (30) is mounted by first bump electrodes (31) to electrode contacts (G, S′) on the at least one first die (20) and by second bump electrodes (32) to terminal pins (14) of the lead frame. The integrated circuit of the flip chip (30) does not require any lead-frame base-portion area for mounting, and low impedance circuit connections are provided by the bump electrodes (31, 32). The first die (20) may be a MOSFET power switching transistor, with a gate driver circuit in the flip chip (30). The circuit impedance for the switching transistor may be further reduced by having distributed parallel gate connections (G), which may alternate with distributed parallel source connections (S′), and furthermore by having distributed and alternating power supply connections (VCC, GND).

Abstract: A shielding arrangement for protecting a circuit containing magnetically sensitive materials from external stray magnetic fields. A shield of a material having a relatively high permeability is formed over the magnetically sensitive materials using thin film deposition techniques. Alternatively, a planar shield is affixed directly to a surface of semiconductor die containing an integrated circuit structure.

Abstract: Stereolithographically fabricated conductive elements and semiconductor device components and assemblies including these conductive elements. The conductive elements may have multiple superimposed, contiguous, mutually adhered layers of conductive material. In semiconductor device assemblies, the stereolithographically fabricated conductive elements may be used to electrically connect different components to one another. The conductive elements may also be used as the conductive traces and vias on circuit boards. The stereolithographically fabricated conductive elements are also useful for rerouting the bond pad locations of a semiconductor die, such as in chip-scale packages.

Abstract: A method for manufacturing a semiconductor device includes the steps of forming a first conductive bump on a substrate, forming a second conductive bump on a semiconductor chip, forming a plurality of spaced apart dielectric supporting pads on one of the substrate and the semiconductor chip, mounting the semiconductor chip on the substrate to confine therebetween a gap, bonding together the first and second conductive bumps, and forming an insulating layer that fills in the gap and that encapsulates the supporting pads and the first and second conductive bumps.

Abstract: In a high-frequency module according to the present invention in which a conductive cap for an electromagnetic purpose is placed on a substrate on which a plurality of electrical components are mounted by soldering, an insulating adhesive is applied between the plurality of electrical components. Since the insulating adhesive is applied between the electrical components on the substrate, it is possible to prevent such deficiencies as “solder touch” between components due to self-alignment which is caused by a solder which melts in the reflow process. As a result, a highly reliable high-frequency module can be obtained, and the number of application points of the insulating adhesive can be reduced.

Abstract: An inventive semiconductor device includes: a substrate; a plurality of first projections each including at least a gate electrode and formed on the substrate; and a plurality of second projections formed on the substrate. When a contour surface constituted by the uppermost face of the substrate and by side and upper faces of the first and second projections is measured for every partial area per unit area of the substrate, the maximum partial area of the contour surface is 1.6 or less times larger than the minimum partial area of the contour surface.

Abstract: A program-controlled unit includes a plurality of semiconductor chips distributed between a plurality of chip carriers that are disposed one above the other and are connected to one another through a bus. Such program-controlled units can be developed, produced, and tested simply, rapidly, and cost-effectively even when they have to be adapted to special requirements.

Abstract: A photodiode 10 of end face incident type which comprises a laminate consisted of an intrinsic semiconductor layer 16 between semiconductor pn conjunction layers 14 and 15 of n-type and p-type InGaAsP. The intrinsic semiconductor layer is formed by InGaAsP to increase a light absorbing region in the intrinsic semiconductor layer 16 toward a direction of depth from the light receiving end plane so as to control light absorptance of the absorbing layer.

Abstract: A synapse configured of an A-MOS transistor has a learning function and can implement high integration similar to that of a DRAM because of its simplified circuit configuration and compact circuit size. With the presently cutting-edge technology (0.15 &mgr;m CMOS), approximately 1G synapses can be integrated on one chip. Accordingly, it is possible to implement a neural network with approximately 30,000 neurons all coupled together on one chip. This corresponds to a network scale capable of associatively storing approximately 5,000 patterns.

Abstract: At least a channel layer and an etching stopper layer are provided on a semiconductor substrate in order, a gate electrode that Schottky-contacts the etching stopper layer is provided on the etching stopper layer, and InGaP having an In composition ratio of 0.66 through 0.9 is used as the etching stopper layer in a field effect type compound semiconductor device.

Abstract: A field effect transistor contains a gate stack with a first layer, preferably a polysilicon layer, on a gate oxide disposed on a substrate, and over the first layer, a second layer, preferably a silicide layer, is provided. Next to the gate electrode is a contact that is separated from the layers of the gate electrode by a layer containing silicon and a spacer layer. Therefore a recrystallization in the silicide layer at elevated temperatures is prevented, which would otherwise cause bulging of the silicide layer toward the contact. It thus prevents shorts between the gate electrode and the contact.

Abstract: An MOS device comprising a gate dielectric formed on a first conductivity type region. A gate electrode formed on the gate dielectric. A pair of sidewall spacers are formed along laterally opposite sidewalls of the gate electrode. A pair of deposited silicon or silicon alloy source/drain regions are formed in the first conductivity region and on opposite sides of a gate electrode wherein the silicon or silicon alloy source/drain regions extend beneath the gate electrode and to define a channel region beneath the gate electrode in the first conductivity type region wherein the channel region directly beneath the gate electrode is larger than the channel region deeper into said first conductivity type region.

Abstract: A capacitor structure is formed over a semiconductor substrate by atomic layer deposition to achieve uniform thickness in memory cell dielectric layers, particularly where the dielectric layer is formed in a container-type capacitor structure. In accordance with several embodiments of the present invention, a process for forming a capacitor structure over a semiconductor substrate is provided. Other embodiments of the present invention relate to processes for forming memory cell capacitor structures, memory cells, and memory cell arrays. Capacitor structures, memory cells, and memory cell arrays are also provided.

Abstract: Exemplary embodiments of the present invention teach a structure and process for forming an array of storage capacitors for a memory array in a memory semiconductor device. The process comprises the steps of: forming a first set of individual storage node plates for a first set of storage capacitors; forming storage node pillars that alternate in position with the individual storage node plates of the first set of individual storage node plates, the storage node pillars being approximately equal in height to neighboring storage node plates; forming a second set of individual storage node plates for a second set of storage capacitors, each individual storage node plate of the second set physically connecting to an individual storage node pillar; forming a cell dielectric material on the first and second sets of individual storage node plates; and forming a second capacitor plate over the first and second sets of individual storage node plates.

Abstract: Semiconductor container capacitor structures having a diffusion barrier layer to reduce damage of the bottom cell plate and any underlying transistor from species diffused through the surrounding insulating material are adapted for use in high-density memory arrays. The diffusion barrier layer can protect the bottom cell plate, any underlying access transistor and even the surface of the surrounding insulating layer during processing including pre-treatment, formation and post-treatment of the capacitor dielectric layer. The diffusion barrier layer inhibits or impedes diffusion of species that may cause damage to the bottom plate or an underlying transistor, such as oxygen-containing species, hydrogen-containing species and/or other undesirable species. The diffusion barrier layer is formed separate from the capacitor dielectric layer. This facilitates thinning of the dielectric layer as the dielectric layer need not provide such diffusion protection.

Abstract: A dynamic random access memory (DRAM) device having a vertical transistor and an internally-connected strap (ICS) to connect the transistor to the capacitor. The ICS makes no direct contact with the substrate. The DRAM cell operates at a substantially lower cell capacitance than that required for a conventional buried strap trench (BEST) cell without causing any negative impact on device performance. The lower cell capacitance also extends the feasibility of deep trench capacitor manufacturing technology without requiring new materials or processing methods. A method of manufacturing the DRAM includes forming a very thin Si layer on top of a DT cell while at the same time the method forms an isolated layer replacing a conventional collar. The formation of the SOI by internal thermal oxidation (ITO) makes the structure in such a manner that the device may be fully depleted.

Abstract: A method for fabricating a semiconductor device that forms a capacitor and metal interconnection in the same level, simultaneously using a damascene process for forming a metal interconnection. A capacitor structure having the high capacitance needed for logic elements is obtained without increasing the number of layers for fabricating the capacitor by forming a three-dimensional capacitor in the damascene pattern while maintaining the conventional processes in a damascene interconnection process.

Abstract: Disclosed is a nonvolatile semiconductor memory device in which a disturbance phenomenon can be prevented. A nonvolatile semiconductor memory device has a semiconductor substrate, and a floating gate electrode formed on the semiconductor substrate via a gate insulating film. The floating gate electrode includes a lower conductive layer formed on the gate insulating film and having a first width W1 in a channel width direction, and an upper conductive layer formed on the lower conductive layer and having a second width W2 wider than the first width W1 in the channel width direction.

Abstract: A gate electrode made of semiconductor is formed on the partial surface area of a semiconductor substrate. A mask member is formed on the surface of the semiconductor substrate in an area adjacent to the gate electrode. Impurities are implanted into the gate electrode. After impurities are implanted, the mask member is removed. Source and drain regions are formed by implanting impurities into the surface layer of the semiconductor substrate on both sides of the gate electrode. It is possible to reduce variations of cross sectional shape of gate electrodes and set an impurity concentration of the gate electrode independently from an impurity concentration of the source and drain regions.

Abstract: A semiconductor device including a semiconductor substrate; a metal gate electrode; and a silicon oxynitride spacer formed on a surface of the metal gate electrode, wherein an interface of the silicon oxynitride spacer and the metal gate electrode is substantially free of metal silicide. In one embodiment, the silicon oxynitride spacer includes a first portion and a second portion, in which the first portion is formed under starving silicon conditions.

Abstract: A method to electronically modulate the energy gap and band-structure of semiconducting carbon nanotubes is proposed. Results show that the energy gap of a semiconducting nanotube can be narrowed when the nanotube is placed in an electric field perpendicular to the tube axis. Such effect in turn causes changes in electrical conductivity and radiation absorption characteristics that can be used in applications such as switches, transistors, photodetectors and polaron generation. By applying electric fields across the nanotube at a number of locations, a corresponding number of quantum wells are formed adjacent to one another. Such configuration is useful for Bragg reflectors, lasers and quantum computing.

Abstract: A method for fabricating a CMOS gate electrode by using Re, Rh, Pt, Ir or Ru metal and a CMOS structure that contains such gate electrodes are described. The work functions of these metals make them compatible with current pFET requirements. For instance, the metal can withstand the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. The thermal stability of the metal on dielectric layers such as SiO2, Al2O3 and other suitable dielectric materials makes it compatible with post-processing temperatures up to 1000° C. A low temperature/low pressure CVD technique with Re2 (CO)10 as the source material is used when Re is to be deposited.

Abstract: The present invention is directed toward an edge detecting photodiode that includes a waveguide comprising a p-doped InP cladding layer, an n-doped InP cladding layer, a p-side waveguide layer, an n-side waveguide layer, and an InGaAs absorption layer therebetween, in which the absorption layer is doped to have an absorption region and a depletion region that, when under bias, will overlap by an amount sufficient to substantially balance the transit time of positive and negative charged carriers across the waveguide. The photodiode is preferably formed on an InP substrate. The photodiode preferably has a planar polymer layer in contact with the InP substrate. The polymer layer also preferably has a ridge formed therein for the photodiode waveguide. The polymer layer may have a coplanar transmission line deposited thereon, and a pair of metal-insulator-metal (“MIM”) capacitors may be incorporated into the coplanar transmission line.

Abstract: It is a main object to provide a semiconductor device with trench isolation, improved so as to be capable of not only relaxing a stress but also forming a channel cut layer under good control to thereby achieve a good isolation characteristic. A trench is formed in a semiconductor substrate at and below a surface thereof. An insulating film, part of which fills the interior of the trench so as to be capable of forming a void in the interior of the trench, and extending above. A diameter of the top end of the trench is smaller than a diameter of the insulating film.

Abstract: A semiconductor device structure has trenches of two widths or more. The smallest widths are to maximize density. The greater widths may be required because of more demanding isolation, for example, in the case of non-volatile memories. These more demanding, wider isolation trenches are lined with a high quality grown oxide as part of the process for achieving the desired result of high quality isolation. For the case of the narrowest trenches, the additional liner causes the aspect ratio, the ratio of the depth of the trench to the width of the trench, to increase. Subsequent deposition of insulating material to fill the trenches with the highest aspect ratios can result in voids that can ultimately result in degraded yields. These voids are avoided by etching at least a portion of the liners of those trenches with the highest aspect ratios to reduce the aspect ratio to acceptable levels.

Abstract: An isolation trench formed in a semiconductor substrate has side walls and a bottom wall. Spacers are on the side walls and face each other for forming a narrow channel therebetween. The bottom wall and the spacers are coated with an electrically insulating material for delimiting a closed empty cavity in the channel. The isolation trench is applicable to the manufacture of integrated circuits.

Abstract: A wafer level packaging process for making flip-chips and integrated circuits formed are proposed. The process comprises in turn, providing a wafer, forming a protective material, bumping the wafer, removing the protective material, probing the wafer, laser repairing, and dicing the wafer. The laser repairing step is after bumping step. The protective material such as photoresist or metal layer is filled into the depression portions above the fuses for temporary protection of the fuses during bumping.

Abstract: The present invention provides a semiconductor device comprising: antifuses having insulation films; and a breakdown-circuit transistor provided in a breakdown circuit for breaking down the insulation films to set the antifuses in a conductive state. The insulation films of the antifuses are made up of the same material as that for a gate insulation film of the breakdown-circuit transistor and formed such that the film thickness of the insulation films are thinner than that of the gate insulation film.

Abstract: A spiral coil pattern is formed on a substantially rectangular insulation substrate of an inductor by photolithography. In the coil pattern, the electrode width of a portion of the pattern provided in the vicinity of the right short side of the substrate so as to be substantially parallel to the short side is wider than the electrode width of the other portion of the pattern. The interelectrode spacing of a portion of the pattern is wider than the interelectrode spacing of the other portion of the pattern. When the inductance of the inductor is required to be reduced to make the inductance a desired inductance value, the electrode width of the portion of the coil pattern is made wider in the inner direction of the coil pattern than the original electrode width.

Abstract: A hydrogen diffusion barrier in an integrated circuit is located to inhibit diffusion of hydrogen to a thin film of a metal oxide, such as a ferroelectric layered superlattice material, in an integrated circuit. The hydrogen diffusion barrier comprises at least one of the following chemical compounds: strontium tantalate, bismuth tantalate, tantalum oxide, titanium oxide, zirconium oxide and aluminum oxide. The hydrogen barrier layer is amorphous and is made by a MOCVD process at a temperature of 450° C. or less. A supplemental hydrogen barrier layer comprising a material selected from the group consisting of silicon nitride and a crystalline form of one of said hydrogen barrier layer materials is formed adjacent to said hydrogen diffusion barrier.

Abstract: A leadframe of a conductive material includes a central region to accommodate a chip and a plurality of connecting fingers extending at least from one side in the direction of the central region, a contact region being provided adjacent to the central region on at least some of the connecting fingers. The course of the connecting fingers is such that a sectional face in an arbitrary imaginary cross-section at right angles to the main face of the leadframe has leadframe material. In such a case, it is attempted to keep cross-sections in a component without leadframe material as small as possible.

Abstract: Dielectric collars are configured to be positioned laterally around contact pads of a semiconductor device or another substrate. Substrates on which the collars are positioned and that include contact pads that are exposed through the collars are also disclosed, as are methods for fabricating the collars and for-positioning the collars on substrates. The collars may be positioned laterally adjacent to the contact pads of a substrate before or after conductive structures are secured to the contact pads. When the conductive structures are electrically connected to contact pads of another semiconductor device component, the collars prevent the material of the conductive structures from contacting regions of the surface of the substrate or other semiconductor device component that surround the contact pads. The collars may be preformed structures that are assembled with the substrate, or they may be formed on the substrate. A stereolithographic method of fabricating the collars is disclosed.

Abstract: A 180 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 180 degree bump placement structures is provided.