Abstract: A conductive composition is obtained by dispersing conductive particles in a curable polymer. At least 50% by weight of the entire conductive particles are those conductive particles coated with a metal on their outermost layer surface and having a specific gravity which differs within ±1.5 from the specific gravity of the curable polymer. The composition remains stable during storage, experiences a minimal change with time of curability, and cures into a conductive rubber which experiences a minimal change with time of volume resistivity.

Abstract: A nonlinear optical chromophore having the formula D-&pgr;-A, wherein &pgr; is a &pgr; bridge including a thiophene ring having oxygen atoms bonded directly to the 3 and 4 positions of the thiophene ring, D is a donor, and A is an acceptor.

Abstract: A shock-absorbing carpet kicker for positioning and stretching carpet is disclosed. The carpet kicker includes an engaging head with forwardly-inclined pins for engaging carpet materials on a floor, a shaft connected to the engaging head and extending therefrom, a cushioned pad facing away from the engaging head and connected to the shaft a distance away from the engaging head, and a shock-absorbing device connected to the shaft and interposed between the engaging head and the cushioned pad. The shock-absorbing device comprises a resilient member preloaded against a collapsible tension member, whereby kicks to the cushioned pad are transmitted through the shock-absorbing device to the engaging head. The preloaded tension member permits a portion of the energy of each kick to be transmitted directly to the engaging head, while the resilient member absorbs excess energy of the kick.

Abstract: A winch for use in a heave compensation system has a winch drum (42) driven by an AC asynchronous motor (50) via a gearbox (52). The motor (50) is controlled by a variable speed control (58) as a function of heave speed. The motor (50) and its drive train, and the winch (42), are chosen to have low inertia. The winch pays out and reels in to compensate for heave substantially instantaneously, without the need for prediction of wave patterns.

Abstract: An improved driving device (10) for the traction of cables or chains, in particular a device (10) for driving electric anchor winches (15), electric winches or windlasses (24), which are able to drive boat or ship anchors; wherein the drive units (45, 46), e.g. relays, contactors, mos units or four-quadrant units, are incorporated inside the motor (23B). The power (P) and control (S) cables are wired to a common connector terminal (60) on the motor.

Abstract: A modular-grid fence system that comprises integral connectors on each end that allows each respective grid to be connected to each other grid and form a fence. The connectors also provide that the modular-grid fence system may be utilized in angles from near zero degrees, to an in-line angle of 180 degrees. This connecting feature provides that the modular-grid fence system may be used to augment and provide additional restriction to an existing fence, or be used as a freestanding fence. In addition, the modular-grid fence system is stackable, easily assembled without tools, and storable or shippable in a flat container.

Abstract: A semiconductor device comprises a first Si1−&agr;Ge&agr; film, a first cap film, a second Si1−&agr;Ge&agr; film (&bgr;<&agr;≦1) and a second cap film formed in this order on a substrate whose surface is formed of silicon, wherein the first Si1−&agr;Ge&agr; film is relaxed to have substantially the same lattice constant as that of the second Si1−&bgr;Ge&bgr; film in a horizontal plane.

Abstract: In accordance with embodiments of the present invention, a junction of an unconventional superconductor, an intermediate material, and a conventional superconducting material is presented. In some embodiments, the resulting junction is in the c-axis direction of the orthorhombic unconventional superconductor. Alternatively, the junction is in the a-b plane direction. Interface junctions according to embodiments of the present invention may be used in super low inductance qubits (SLIQs) and in permanent readout superconducting qubits (PRSQs), can form the basis of quantum registers, and can allow for parity keys or other devices made from conventional superconducting material to be attached to qubits made from unconventional superconducting material or vice versa. Coherent tunnel junctions according to embodiments of the present invention may be used to form parity keys or coherently couple two regions of a superconducting material.

Abstract: The invention concerns an optoelectronic device comprising at alteration of at least three semiconductor layers with selected shape, and two air layers. The semiconductor layers having N-type or P-type doping which may differ or not from one layer to the next layer, are separated by spacers whereof the doping is non-intentional (I-type) or intentional (N-type or P-type) to define a PINIP or NIPIN structure with air cavities, and are adapted to be set at selected respective electric potentials. The respective thicknesses and compositions of the layers and the spacers are selected so that the structure has at least an optical transfer function adapted to light to be treated and adjustable in accordance with the selected potentials applied to the semiconductor layers.

Abstract: Each of a plurality of semiconductor chips comprises an integrated circuit region and a plurality of electrodes for electrical connection to outside. The electrodes are disposed on a surface of each of the semiconductor chips in a predetermined pattern. A distance between a left side of each of the semiconductor chips and each of the electrodes, and a distance between a right side of each of said semiconductor chips and each of the electrodes are predetermined distances, respectively.

Abstract: A MIS type semiconductor device and a method for fabricating the same characterized in that impurity regions are selectively formed on a semiconductor substrate or semiconductor thin film and are activated by radiating laser beams or a strong light equivalent thereto from above so that the laser beams or the equivalent strong light are radiated onto the impurity regions and on an boundary between the impurity region and an active region adjoining the impurity region.

Abstract: An array substrate for use in an in-plane switching liquid crystal display device has a plurality of common electrodes and a plurality of pixel electrodes. One of the common electrodes is formed at the same time with the plurality of pixel electrodes using a transparent conductive material. This transparent common electrode is connected to other common electrode through a common electrode connector. Therefore, aperture ratio can be increased. Further in the present invention, a capacitor electrode is disposed over the common line and then forms a first storage capacitor with a portion of the common line, and a pixel electrode connector is disposed over the gate line and then forms a second storage capacitor with a portion of the gate line. As a result, the IPS-LCD device can obtain an improved and stable capacitance from the two storage capacitors.

Abstract: In a semiconductor device having an SOI structure and a method of manufacturing the same, influence by a parasitic transistor can be prevented, and no disadvantage is caused in connection with a manufacturing process. In this semiconductor device, an upper side portion of a semiconductor layer is rounded. Thereby, concentration of an electric field at the upper side portion of the semiconductor layer can be prevented. As a result, lowering of a threshold voltage of a parasitic transistor can be prevented, so that the parasitic transistor does not adversely affect subthreshold characteristics of a regular transistor. Owing to provision of a concavity of a U-shaped section, generation of etching residue can be prevented when etching a gate electrode for patterning the same. Thereby, a disadvantage is not caused in connection with the manufacturing process.

Abstract: A gate line extending in a horizontal direction is formed on an insulating substrate, and a data line is formed perpendicular to the gate line defining a pixel of a matrix array. Pixel electrodes receiving image signals through the data line are formed in a pixel, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode is formed on the portion where the gate lines and the data lines intersect. A storage wire including a storage electrode line in the horizontal direction, a storage electrode connected to the storage electrode line, and at least one of the storage electrode connection portions connecting storage electrodes of neighboring pixels is formed in the same direction as the gate line.

Abstract: A liquid crystal display panel (and a method for manufacturing the liquid crystal display panel) includes a gate line and a signal line intersecting the gate line at an intersection portion where the gate line and the signal line intersect each other. The gate line includes at least two conductive portions and at least one opening portion on the intersection portion.

Abstract: In silicon carbide semiconductor device and manufacturing method therefor, a metal electrode which is another than a gate electrode and which is contacted with a singlecrystalline silicon carbide substrate is treated with a predetermined heat process at a temperature which is lower than a thermal oxidization temperature by which a gate insulating film is formed and is sufficient to carry out a contact annealing between the singlecrystalline silicon carbide substrate and a metal after a whole surrounding of the gate insulating film is enclosed with the singlecrystalline silicon carbide substrate, a field insulating film, and the gate electrode. The present invention is applicable to a MOS capacitor, an n channel planar power MOSFET, and an n channel planar power IGBT.

Abstract: The present invention is to provide an organic electroluminescent device with a containing fluorine inorganic layer whose structure sequentially comprises a substrate, a transparent conductive layer (anode), a containing fluorine inorganic layer, a hole-transport layer, an organic light-emitting layer, an electron-transport layer, and a metallic conductive layer (cathode), wherein said a containing inorganic layer is made of metallic fluoride, and it can stabilize as well as increase the lifetime for an organic electroluminescent device.

Abstract: An electrically conductive high-melting-point oxide light source that can be used in an oxygen-containing atmosphere includes a sintered oxide having as an essential constituent an oxide of an element selected from the group consisting of ruthenium, iridium, rhodium and rhenium. It is used an oxygen-containing atmosphere at a temperature of not less than 1700° C. A high-melting-point conductive paste includes particles of a sintered oxide having as an essential constituent an oxide of an element selected from the group consisting of ruthenium, iridium, rhodium and rhenium, and a binder and solvent. An exhaust gas filter includes a powdered sintered oxide having as an essential constituent an oxide of an element selected from the group consisting of ruthenium, iridium, rhodium and rhenium, the powdered sintered oxide being applied to and baked on, or formed into a heating element and attached to, a surface of a diesel engine exhaust gas filter of ceramic to form a heating element.

Abstract: A terminal interconnection 45a including an aluminum alloy film 4a and a nitrogen-containing aluminum film 5a layered together is formed on a glass substrate 2. Nitrogen-containing aluminum film 5a in a contact portion 12a within a contact hole 11a exposing the surface of terminal interconnection 45a has a predetermined thickness d1 determined based on a specific resistance of the nitrogen-containing aluminum film. The thickness of the nitrogen-containing aluminum film outside the contact portion is larger than that of the nitrogen-containing aluminum film within the contact portion. Thereby, a semiconductor device or a liquid crystal display device having a reduced contact resistance and an appropriate resistance against chemical liquid is achieved.

Abstract: A semiconductor chip has a substrate that is in the form of a parallelepiped whose side surfaces are shaped as tilted parallelograms. Such a semiconductor chip has a high output efficiency and a homogeneous thermal load due to having at least two side surfaces that are provided with an acute angle and are in the form of parallelograms.

Abstract: An opto-electronic semiconductor element has a radiation emitting or receiving, that is, radiation active semiconductor chip secured to an electrically conductive base frame. One, or a plurality of chips, are surrounded by a housing which may be integral with or have, separately, a cover. All materials of the housing, as well as of the conductive base frame, have mutually matching thermal coefficients of expansion within the temperature ranges which arise during manufacture and in application of the semiconductive element, singly or as a plurality in a common housing. Glass, quartz glass, ceramic or glass ceramic are suitable for the housing or parts thereof; the conductive base frame is preferably made of cladded or jacketed copper wire or strip with an iron-nickel core. Assembling a plurality of chips in a housing which has a luminescence conversion layer, e.g. a phosphor applied thereto, permits construction of a flat light source.

Abstract: A semiconductor light-emitting element having a structure that does not complicate a fabrication process, can be formed in high precision and does not invite any degradation of crystallinity is provided. A light-emitting element is formed, which includes a selective crystal growth layer formed by selectively growing a compound semiconductor of a Wurtzite type, and a clad layer of a first conduction type, an active layer and a clad layer of a second conduction type, which are formed on the selective crystal growth layer wherein the active layer is formed so that the active layer extends in parallel to different crystal planes, the active layer is larger in size than a diffusion length of a constituent atom of a mixed crystal, or the active layer has a difference in at least one of a composition and a thickness thereof, thereby forming the active layer having a plurality of light-emitting wavelength region whose emission wavelengths differ from one another.

Abstract: Provided is a diode circuit with small power consumption. A first voltage comparator (4) compares a voltage at a cathode terminal (101) with a sum of a voltage at an anode terminal (102) and a voltage across a first voltage source (10) to output a reset signal, and a second voltage comparator (5) compares a voltage at the anode terminal (102) with a sum of a voltage at the cathode terminal (101) and a voltage across the second voltage source (11) to output a set signal. A first latch circuit (20) outputs an L signal when the reset signal from the first voltage comparator (4) is inputted, and outputs an H signal when the set signal from the second voltage comparator (5) is inputted. An n-channel MOS transistor (2) turns off upon receiving the L signal, and turns on upon receiving the H signal, to thereby limit an output current.

Abstract: The present invention has an object of providing a thyristor-type semiconductor device and a manufacturing method for the same which can prevent, even when conventional manufacturing equipment is used, the electrode terminals 13, 14 from being provided in a significantly tilted state where the electrode terminals 13, 14 are in contact with the silicon substrate 20, and can also prevent the electrode terminals 13, 14 from being provided in a state where the electrode terminals 13, 14 come into contact with the silicon substrate 20, even when there are warping and undulations in the silicon substrate 20. In a semiconductor device of the present invention, the supports 11a, 11b are provided on both surfaces of the silicon substrate 20 using a glass material. When doing so, the support 11b is disposed in a part of the boundary between the second N-type layer 18 and the second P-type layer 19 that is opposite the side surface 22.

Abstract: A high frequency high voltage semiconductor device having a shifted doping profile and method for forming the same are provided. Specifically, the present invention provides a semiconductor device (<250V) in which the doping profile is shifted towards the source or body region of the device. The shift in doping profile under the present invention allows both transconductance and capacitance to be optimized so that a SOI device can operate at high frequencies.

Abstract: A super self-aligned heterojunction bipolar semiconductor device and its manufacturing method are disclosed. The present invention provides a super self-aligned heterojunction bipolar transistor that may maintain the operational stability and the uniformity of a device, facilitate the manufacturing process, and reduce manufacturing time by employing a highly concentrated thick polysilicon film; and its manufacturing method. Also, the present invention provides a super self-aligned heterojunction bipolar transistor that may reduce noise by making the base resistance reduced by a highly concentrated thick polysilicon film, and may minimize the parasitic capacitance between a collector and a base and between a base and an emitter, and the parasitic resistance of a base, so as to realize high-speed operation of a device; and its manufacturing method.

Abstract: A method for manufacturing a semiconductor device. A trench is formed in a substrate. An insulation spacer is then formed on the sidewall of the trench. A first epitaxial silicon layer is formed in the trench, followed by doping the first epitaxial layer as a doped source/drain (S/D) region. A second epitaxial silicon layer is formed on the substrate and on the first epitaxial silicon layer, followed by forming a gate on the second epitaxial silicon layer. Then using the gate as a mask, ions are implanted to form an extended doped region. Thereafter, a rapid thermal annealing is performed to convert both the source/drain doped region and the extended doped region to a source/drain region.

Abstract: An object of the present invention is to provide a large-size light-emitting device from which uniform light emission can be obtained.

Abstract: Improve the productivity and cost for the manufacturing of a semiconductor device referred to as a wafer level CSP. The manufacturing method for a semiconductor device related to this invention contains each of the processes that form a wiring (18) for the purpose of electrically connecting each electrode pad (10a) and external connecting terminals on top of a wafer (10) on which semiconductor elements are formed, connect conductive balls that are preformed by a separate process on top of this, and next, cover the above-mentioned wafer with a resin (32) such that the upper portion of the conductive supporting posts (30) are exposed. In a later process, solder balls (34) are arranged as external connecting terminals on the upper portion of the conductive supporting posts, and in the final process, semiconductor elements are formed by dicing the above-mentioned wafer along the boundary lines of the above-mentioned semiconductor elements.

Abstract: A select gate transistor has a select gate electrode composed of a first-level conductive layer and a second-level conductive layer. The first-level conductive layer has a plurality of contact areas. The second-level conductive layer has its portions removed that are located above the contact areas. Two adjacent select gate electrodes that are adjacent to each other in the column direction are arranged such that the contact areas of one select gate electrode are not opposed to the contact areas of the other select gate electrode. One select gate electrode has its first- and second-level conductive layers removed in their portions that are opposed to the contact areas of the other select gate electrode.

Abstract: To significantly reduce parasitic capacitance of component's landing pad, the present invention forms patterned holes in reference potential layers below the pad, thus effectively increasing the dielectric distance between the pad and the reference potential planes below the pad, raising the characteristic impedance of the pad above that of the trace connected to the pad. A controlled amount of parasitic capacitance is re-introduced to the pad by forming at least one grounded metal plate adjacent to the pad, bringing the characteristic impedance of the pad to substantially match that of the trace. The distance of the metal plates from the pad, and the configuration of the patterned holes are predetermined to substantially match the pad's impedance with that of the trace.

Abstract: A tunneling magnetoresistive storage unit (TMR unit) includes a hollow cylinder-shaped free-spin element having one open end, a columnlike fixed-spin element formed inside the cylinder-shaped free-spin element, and a thin insulator layer located between them. The spin direction in the fixed-spin element is fixed to a predefined circumferential direction of its column-shaped magnetic substance beforehand and a tunneling current is flowed between the free-spin element and the fixed-spin element. A rotating magnetic field produced as a consequence is used to set the spin direction in the cylinder-shaped free-spin element to one of its circumferential directions. This structure decreases the amount of electric current required for performing data write operation, also enabling miniaturization and a higher level of integration of the TMR unit and a magnetic random-access memory by employing such TMR units.

Abstract: A probe of a scanning probe microscope (SPM) having a field-effect transistor (FET) structure at the tip of the probe, and a method of fabricating the probe are provided. The SPM probe having a source, channel, and drain is formed by etching a single crystalline silicon substrate into a V-shaped groove and doping the etching sloping sides at one end of the V-shaped groove with impurities.

Abstract: A substrate exposure apparatus, having a display apparatus and a control system. The display apparatus is used to display the pattern and to transfer the pattern to the photoresist, and includes a non-self luminescent display or a self-luminescent display. The control system is used to control the pattern displayed on the display apparatus.

Abstract: A composite module and its production process which allow multiple functions, miniaturization, low power consumption and low costs without requiring any external chip parts at all. A high-frequency integrated circuit is embedded in a silicon substrate, a high-frequency high-capacity bypass capacitor and a matching coil using thin films of different types of materials are also formed on the silicon substrate, a high-frequency high-capacity bypass capacitor is further formed with an interlayer insulation film between them, and these elements and the high-frequency integrated circuit are connected via a wiring layer.

Abstract: Noise-reduced semiconductor devices operating at a high frequency band greater than several GHz are disclosed. Also disclosed is a method for manufacturing such semiconductor devices. A trench penetrating through a semiconductor substrate is configured to surround a noise-generating circuit block and/or a noise-susceptible circuit block, in order to reduce noise propagation through the substrate. Noise-reduced semiconductor device are fabricated with a conventional silicon wafer instead of an SOI (Silicon on Insulator) wafer, which is manufactured in a complicated process sequence.

Abstract: First and second epitaxial layers are spaced apart from one another over the surface of a semiconductor substrate. A gate electrode is formed over the surface of the substrate, and extends within a gap defined between the first and second epitaxial layers and partially overlaps each of the first and second epitaxial layers adjacent the gap. First and second impurity regions are contained at least partially within the first and second epitaxial layers, respectively, and a gate insulating layer is located between the gate electrode and the semiconductor substrate. A non-planar channel region may be defined within the portions of the first and second epitaxial layers which are overlapped by the gate electrode and within a surface portion the semiconductor substrate located between the first and second epitaxial layers.

Abstract: First and second epitaxial layers are spaced apart from one another over the surface of a semiconductor substrate. A gate electrode is formed over the surface of the substrate, and extends within a gap defined between the first and second epitaxial layers and partially overlaps each of the first and second epitaxial layers adjacent the gap. First and second impurity regions are contained at least partially within the first and second epitaxial layers, respectively, and a gate insulating layer is located between the gate electrode and the semiconductor substrate. A non-planar channel region may be defined within the portions of the first and second epitaxial layers which are overlapped by the gate electrode and within a surface portion the semiconductor substrate located between the first and second epitaxial layers.

Abstract: A semiconductor device having: a semiconductor substrate having first and second regions defined in a principal surface of the semiconductor substrate; a first underlying film formed in the second region; a first lamination structure formed in a partial area of the first region, the first lamination structure having a conductive film and an insulating film stacked in this order from the substrate side; and a second lamination structure formed on the first underlying film and having a conductive film and an insulating film stacked in this order from the substrate side, wherein the insulating films of the first and second lamination structures are made of the same material and the height of the upper surface of the second lamination structure as measured from the principal surface of the semiconductor substrate is equal to or lower than the height of the upper surface of the first lamination structure as measured from the principal surface of the semiconductor substrate.

Abstract: A method for making a filed-effect semiconductor device includes the steps of forming a gate electrode on a semiconductor layer composed of a gallium nitride-based compound semiconductor represented by the formula AlxInyGa1-x-yN, wherein x+y=1, 0≦x≦1, and 0≦y≦1; and forming a source electrode and a drain electrode by self-alignment using the gate electrode as a mask. A field-effect semiconductor device fabricated by the method is also disclosed.

Abstract: An image sensor having an array of pixel elements constructed using a two level polysilicon CMOS process that provides individual addressability and a non-destructive readout of the pixels. The pixel elements each includes a substrate, an insulating layer formed on the substrate, a collection capacitor electrode, a transfer electrode, a readout capacitor electrode, and a readout transistor. The transfer electrode is located between the collection and readout capacitor electrodes and all three electrodes are electrically isolated from the substrate and each other by the insulating layer. The collection capacitor electrode and insulating layer are transparent so that incident light can pass through these elements and be absorbed by the substrate. A bias voltage is applied to the collection electrode to form a depletion region in the substrate where photoelectrically generated charge is collected.

Abstract: In an array of integrated transistor/memory structures the array comprises one or more layers (1) of semiconducting material, two or more electrode layers, and memory material (11) contacting electrodes (2,6,10) in the latter. At least one layer of a semiconducting material and two electrode layers form transistor structures such that the electrodes of the first electrode layer forms source/drain electrode pairs and those of a second electrode layer form the gate electrodes thereof. The source and drain electrodes (2;6) of a single transistor/memory structure are separated by a narrow recess (3) extending down to the semiconducting (1) layer wherein the transistor channel (8) is provided beneath the recess and with extremely small width, while the source and drain regions are provided beneath the respective source and drain electrodes (2;6) on either side of the transistor channel (8). Memory material (11) is provided in the recess (3) and contacts the electrodes (2,6,10) of the transistor.

Abstract: Field effect transistors having a ferroelectric layer overlying a gate insulator layer as well as methods of their formation and use, and devices produced therefrom. Such ferroelectric field effect transistors are suitable for use in memory devices as the polarization of the ferroelectric layer can represent distinct logic states. The polarization of the ferroelectric layer alters the threshold voltage of the field effect transistor thus producing distinctly different conductivity states through the weak ferroelectric transistor at a given gate potential depending upon the polarization. The ferroelectric layer may contain a weak ferroelectric material having spontaneous polarization values in the range of approximately 0.01 &mgr;Coulomb/cm2 to 1 &mgr;Coulomb/cm2. The ferroelectric layer may contain a doped zinc oxide material doped with lithium and/or magnesium.

Abstract: Each of a plurality of repeating units comprises a plurality of memory cells. A second-conductivity-type well is formed in a surface layer of a semiconductor substrate extending over the plurality of the repeating units. In the second-conductivity-type well, first-conductivity-type channel MOS transistors of the plurality of the repeating units are provided. A second-conductivity-type well tap region is formed in one of the memory cells in each repeating unit and in the second-conductivity-type well. In the memory cell provided with the second-conductivity-type well tap region or in the memory cell adjacent thereto, an interlayer connection member is provided. The interlayer connection member is connected to the source region of one of the first-conductivity-type channel MOS transistors and to the corresponding second-conductivity-type well tap region.

Abstract: First and second transistors are formed on the principal surface of the semiconductor substrate, and an insulating film is formed over the principal surface of the semiconductor substrate so as to cover the first and second transistors. A first storage node is connected to the first transistor and has a first enclosed wall structure which is formed over the insulating film and encloses a surface region of the insulating film. A second storage node is connected to the second transistor and has second enclosed wall structure which is formed over the insulating film and surrounds the first enclosed wall structure. A capacitor insulating film covers the first and second enclosed wall structures, and a cell-plate is formed on the capacitor insulating film.

Abstract: A semiconductor device having a structure in which the amount of stress on a semiconductor substrate or a gate wire is low, even in a case when the sidewalls of the gate wire are formed of a nitride film is obtained. A gate conductive layer positioned above a silicon substrate, a stress mitigating film that covers a sidewall of the gate conductive layer and a sidewall external layer spacer that covers the stress mitigating film and that exposes the upper edge of the stress mitigating film and the side edge of the bottom portion of the stress mitigating film are provided and the stress mitigating film has silicon oxide films positioned in the areas ranging inwardly from the upper edge and from the side edge so as to sandwich the silicon oxide film from both ends.

Abstract: The invention provides a semiconductor device having a ferroelectric substance capacitor small in the occupying area and large in capacitance and a semiconductor device having a ferroelectric substance capacitor reducing influence of noise and being few in malfunctions. The semiconductor device includes a first capacitor formed on a surface of a semiconductor substrate and a second capacitor of a ferroelectric substance capacitance laminated on the first capacitor so as to connect in series.

Abstract: A disadvantage upon heat treatment in an oxygen atmosphere of a dielectric film formed on a lower electrode of capacitance device of DRAM that oxygen permeating the lower electrode oxidizes a barrier layer to form an oxide layer of high resistance and low dielectric constant is prevented. An Ru silicide layer is formed on the surface of a plug in a through hole formed below a lower electrode for an information storage capacitance device C and an Ru silicon nitride layer is formed further on the surface of the Ru silicide layer. Upon high temperature heat treatment in an oxygen atmosphere conducted in the step of forming a dielectric film on the lower electrode, the Ru silicon nitride layer is oxidized sacrificially into an Ru silicon oxynitride to prevent progress of oxidation in the Ru silicide layer.

Abstract: Methods for removing titanium-containing layers from a substrate surface where those titanium-containing layers are formed by chemical vapor deposition (CVD) techniques. Titanium-containing layers, such as titanium or titanium nitride, formed by CVD are removed from a substrate surface using a sulfuric acid (H2SO4) solution. The H2SO4 solution permits selective and uniform removal of the titanium-containing layers without detrimentally removing surrounding materials, such as silicon oxides and tungsten. Where the titanium-containing layers are applied to the sidewalls of a hole in the substrate surface and a plug material such as tungsten is used to fill the hole, subsequent spiking of the H2SO4 solution with hydrogen peroxide (H2O2) may be used to recess the titanium-containing layers and the plug material below the substrate surface.

Abstract: A method for forming a refractory metal-silicon-nitrogen capacitor in a semiconductor structure and the structure formed are described. In the method, a pre-processed semiconductor substrate is first positioned in a sputtering chamber. Ar gas is then flown into the sputtering chamber to sputter deposit a first refractory metal-silicon-nitrogen layer on the substrate from a refractory metal silicide target, or from two targets of a refractory metal and a silicon. N2 gas is then flown into the sputtering chamber until that the concentration of N2 gas in the chamber is at least 35% to sputter deposit a second refractory metal-silicon-nitrogen layer on top of the first refractory metal-silicon-nitrogen layer. The N2 gas flow is then stopped to sputter deposit a third refractory metal-silicon-nitrogen layer on top of the second refractory metal-silicon-nitrogen layer. The multi-layer stack of the refractory metal-silicon-nitrogen is then photolithographically formed into a capacitor.