Abstract: A magnetic resonance imaging apparatus generates an MR signal from an object to be examined by applying a gradient field pulse generated by a gradient field coil and a high-frequency magnetic field pulse generated by a high-frequency coil onto the object in a static field generated by a static field magnet, and reconstructs an image on the basis of the MR signal. The gradient field coil is housed in a sealed vessel. A cable extending from an external power supply and connected to the gradient field coil has predetermined flexibility.

Abstract: The invention relates to a metal detector with at least one driver circuit 2, at least one transmitter winding 4 having two external terminals 4a, b, and at least one receiver winding 5 having two external terminals 5a, b. The efficiency is increased in comparison to conventional metal detectors by providing at least one tap subdividing the transmitter winding 4, whereby a transformed electrical AC voltage is provided at the external terminals 4a, b of the transmitter winding 4 by the driver circuit via the tap 4c.

Abstract: A coil array for high resolution induction logging comprises a transmitter, a first receiver set positioned at a first distance from the transmitter and a second receiver set positioned at a second distance from the transmitter, and the second receiver set includes at least one portion of the first receiver set. Also disclosed is a method for deriving an apparent conductivity log from at least one induction well log that comprises a plurality of depth samples, comprising the steps of raising each depth sample of the apparent conductivity signal to several predetermined powers to generate a plurality of powers of conductivity, convolving in depth the powers of conductivity with a plurality of filters, where each power has a distinct filter, and summing the results of all of the convolutions to produce a conductivity log that is substantially free from the effects of adjacent beds and the nonlinear effects of true conductivity.

Abstract: A monitoring system and method detects electrical parameters associated with a conductive strap attached to a user to detect electrical characteristics which may be destructive of sensitive electrical components being manipulated by the user.

Abstract: The electrical short-circuit detection device comprises first signal processing means receiving a signal representative of an electrical current and supplying a first signal representative of the value of said electrical current and a second signal representative of the differential of said electrical current, and second processing means receiving said signals and comprising short-circuit detection means supplying a detection signal according to a curve overshoot. The second processing means monitor a limit curve overshoot and a ratio between variations of said signals. A short-circuit detection signal is supplied if said ratio exceeds a preset threshold. The circuit breaker incorporates such a device. The process comprises monitoring steps of limit curve overshoot and of the ratio between variations of the signals.

Abstract: The present invention relates to a method for protecting a zone in a power system, which zone comprises a number of transmission lines connected to power sources and a number of transmission lines connected to a number of loads where the power sources and the loads are arranged outside the zone, wherein the method comprises the steps of: continuously measuring all the incoming currents (Iin) to the zone, continuously measuring all the outgoing currents (Iout) from the zone, and continuously calculating the differential current (Id) according to Id=Iin−Iout. The method is characterised in continuously integrating Iin, Iout and Id according to Formula (I), where T is the fundamental frequency cycle, whereby changes of the continuously integrated values I?IN?, IOUT and ID constitute indications of whether faults on the power system occur within or outside the zone. The present invention also relates to a device and computer program product for performing the method.

Abstract: A coaxial radio frequency adapter and method are disclosed. An adapter has a tapered signal pin and a tapered ground sleeve to maintain a consistent impedance and minimize reflections while connecting two elements having different dimensions. A method employs an adapter to characterize losses in a system for evaluating a device under test.

Abstract: A cable continuity test system, comprising a terminator unit electrically connected to a first side of a cable to be tested, and a test set unit electrically connected to a first side of said cable. The test set unit includes a display and further includes a microprocessor adapted for performing standard continuity tests. The test unit stores records for each site tested with a time and date stamp. The terminator unit is a programmable unit, and preferably is capable of being programmed with a unique terminator ID between the numbers of 00 and 99.

Abstract: The test rig (1) comprises a first assembly (6) comprising a coupling shaft (7) which can be connected, via coupling means (8) to an output shaft (3) of the power transmission device (2) that is to be tested; a second assembly (9) which can be connected to an input shaft (4) of the device (2) that is to be tested; a position-adjustable support (14) on which the casing (5) of the device (2) can be mounted; and means (15) for adjusting the position of the support (14). The coupling means (8) produce a rigid and coaxial coupling and the adjusting means (15) allow the forces and moments likely to be generated on the output shaft (3) to be applied to the casing (5).

Abstract: A polymer-type humidity sensor for use in a microwave oven and which has a polymer structure which comprises a rubber and a predetermined amount of carbon, and a pair of electric terminals connected to the polymer structure. The polymer-type humidity sensor of the present invention has a rapid response time, durability, excellent adherence to terminals, low hysteresis, and exhibit stability to exposures of high temperatures and high relative humidity.

Abstract: This invention relates to an apparatus for, and method of, making electrical measurements on objects, in particular cells, liposomes or similar small objects, in a medium. More particularly the invention relates to an apparatus for, and method of, making electrophysiological measurements on cells, liposomes or similar small objects, in a medium.

Abstract: Methods and device for a probe card in the form of a multi-beam probe card that includes one or more beam assemblies disposed across an opening in a head plate. The probe card has a plurality of probe needles extending through the beam assemblies that provide for wide area coverage of a wafer undergoing test prior to cutting the wafer into individual chips. The multi-beam probe card may be used in a wafer test system that is configured to send test signals to the wafer and to evaluate the signal upon return.

Abstract: A multi-channel, low input capacitance signal probe head has a housing that receives one or more substrates having input signal pads exposed on one end of the substrate. The substrate is positioned in the housing such that the signal contact pads are exposed at an open end of the housing. A removable signal contact holder mounts to the housing and supporting electrically conductive elastomer signal contacts. The holder is disposed over an open end of housing such that the elastomer signal contacts engage the input signal pads. A probe head retention member is provided for securing the multi-channel signal probe head to a device under test.

Abstract: An adapter for a multi-channel, low input capacitance signal probe head has a housing with a cavity formed therein that receives one of a mating plug or receptacle portion of multi-channel, controlled impedance connector. The housing has probe head retention members formed in the sidewalls and alignment flanges disposed adjacent to the probe head retention members that are received in the signal probe head. The adapter includes a substrate having first and second arrays of contact pads formed on the respective top and bottom surfaces of the substrate. The first array of contact pads mate with electrically conductive elastomer signal contacts of the signal probe head and the second array of contact pads mate with the contact pads of the transmission lines of the plug or receptacle. Screws extend through bores in the signal probe head and engage threaded pins in the retention members.

Abstract: An improved structure of wire clip for integrated circuit is disclosed.

Abstract: A test arrangement includes a semiconductor device, a first conductive pad electrically connected to the semiconductor device, a second conductive pad, and a programmable fuse. The second conductive pad is electrically connected to the semiconductor device through the programmable fuse.

Abstract: An integrated test circuit, as part of an integrated circuit, includes phase-shifted test signals fed through inputs A and B. These test signals are conducted through a plurality of cascaded delay elements, the advancing of the first test signal through the delay elements being held and evaluated by the second test signal.

Abstract: A method and systems to evaluate the propagation delay within a semiconductor chip (305) that is embedded in an electronic system without requiring measure apparatus and specific electrical contacts is disclosed. Since most of electronic systems use a microprocessor, the basic principle of the invention consists in using the microprocessor capabilities to measure the propagation delay of a chip embedded in such an electronic system. Thus, according to the invention, the microprocessor transmits an instruction to the semiconductor chip that performs propagation delay evaluation and then read the result in a dedicated memory register (415) of the chip. As a consequence, the chip does not required dedicated pins and measure apparatus are not necessary. To measure the propagation delay, the chip comprise a logic path (400) wherein propagation delay is created, a rising edge detector (405) to analyze logic path signals and a counter (410) based on a system clock to measure propagation delay.

Abstract: Techniques for performing wafer-level burn-in and test of semiconductor devices include a test substrate having active electronic components such as ASICs mounted to an interconnection substrate or incorporated therein, metallic spring contact elements effecting interconnections between the ASICs and a plurality of devices-under-test (DUTs) on a wafer-under-test (WUT), all disposed in a vacuum vessel so that the ASICs can be operated at temperatures independent from and significantly lower than the burn-in temperature of the DUTs. The spring contact elements may be mounted to either the DUTs or to the ASICs, and may fan out to relax tolerance constraints on aligning and interconnecting the ASICs and the DUTs.

Abstract: A testing apparatus for testing an electron device, has a first supply unit that supplies a first current to the electron device; a first feedback circuit which feeds back voltage applied to the electron device to the, first supply unit; a first switch which switches to whether or not connect electrically the electron device to the first feedback circuit; a second supply unit that supplies a second current to the electron device, the second supply unit being separated from the electron device by the first switch.

Abstract: Localizing bypass capacitance for the purpose of reducing or eliminating noise in power supplies in an integrated circuit (IC). After a data path block of macro cells has been constructed by the IC designer, a determination is made as to which cells of the macro cells comprise functionality that will not be used by the IC when it is operating. At least a plurality of cells that are determined to be cells that comprise functionality that will not be used when the IC is operating are filled with bypass capacitors. Because there are typically a large number of cells that will not be used when the IC is operating, filling a plurality or all of these cells with bypass capacitors ensures that bypass capacitors will be located in close proximity to power supplies on the IC, which ensures that the bypass capacitors will be effective at reducing or eliminating noise in the power supplies.

Abstract: An integrated circuit providing mixed signal processing. I/O pin interface circuits include logic gates and other circuits for processing digital and analog signals. Processor-controlled configuration circuits allow the various I/O pin interface circuits to process either analog or digital circuits. The I/O pins can be configured for digital or analog operation on the fly.

Abstract: An integrated circuit comprising a standard cell is disclosed. The standard cell includes a plurality of logic functions; at least a portion of the logic functions requiring initialization. The circuit includes a field programmable gate array (FPGA) cell coupled to the at least a portion of the plurality of logic functions. The at least a portion of the plurality of logic functions are initialized by the FPGA cell. In a method and system in accordance with the present invention, an on-chip Field Programmable Gate Array (FPGA) cell is configured to implement the required application-specific function initializations. The FPGA cell could be wired directly to each of the registers within the functional blocks requiring initialization. These registers would also be wired to the processor bus allowing software access for normal operation after initialization.

Abstract: An application specific integrated circuit (ASIC) is disclosed. The ASIC comprises a standard cell, the standard cell including a plurality of logic functions. The ASIC further includes at least one FPGA interconnect coupled to at least a portion of the logic functions. The FPGA interconnect can be configured to select a particular logic function of the plurality of logic functions. An ASIC in accordance with the present invention allows “field selection” of functions that are connected to the internal bus(es) and to external I/O. In addition, functional block connections made with internal buses can be significantly wider and faster than buses brought on chip via external chip I/Os. Further, the ASIC reduces cost because selective bus connections can be made internal to the chip, thus eliminating the need for external pins. Finally, the ASIC reduces the cost of the packaged component by allowing the chip to be packaged in a lower pin count package.

Abstract: An object of the present invention is to provide a programmable logic device which intends to reduce electric power consumption or heat generation sufficiently as a whole device while preventing a clock skew from being generated and retaining a processing speed of the device. To this end, according to the present invention, there is provided a device including logic blocks for carrying out logical operation, lines for connecting the logic blocks, line-changing means for changing the state of lines connecting the logic blocks by programming, a clock net for supplying a clock signal to each of the logic blocks, and clock control means for dynamically controlling switching between a clock signal supply mode and a clock signal stop mode for each logic block so that at least one non-active logic block of the logic blocks can be stopped from being supplied with the clock signal.

Abstract: An improved, high density CPLD includes a plurality of macrocell sections. Each macrocell section can receive a relatively large number of independent input terms and can generate as a base cluster, at least as many as 5 different product term signals (PT's) therefrom. Part or all of the macrocell's local 5 PT's may be used for generating a local sum-of-products (SoP) signal in a local, first-level ORring operation. Additionally SoP's generated in neighboring macrocell sections may be selectively and incrementally cascaded (cross-laced) for supplemental summing into the local SoP signal. SoP signals of neighboring sections may be further selected in a sums sharing array for second level summing. The combination of the first-level cascading (cross-lacing) and second-level sums sharing provides a wide range of programmably selectable granulations including that of having relatively fast generation of a sum of just a few PT's (e.g.

Abstract: Structures and methods for programmable logic arrays are provided. In one embodiment, the programmable logic array includes a first logic plane and a second logic plane. The first logic plane receives a number of input signals. The first logic plane has a plurality of logic cells arranged in rows and columns that are interconnected to provide a number of logical outputs. The second logic plane has a number of logic cells arranged in rows and columns that receive the outputs of the first logic plane and that are interconnected to produce a number of logical outputs such that the programmable logic array implements a logical function. Each of the logic cells includes a vertical pillar extending outwardly from a semiconductor substrate. Each pillar includes a single crystalline first contact layer and a second contact layer separated by an oxide layer. Each logic cell further includes at least one single crystalline ultra thin vertical transistor that is selectively disposed adjacent the vertical pillar.

Abstract: In a level conversion circuit mounted in an integrated circuit device using a plurality of high- and low-voltage power supplies, the input to the differential inputs are provided. In a level-down circuit, MOS transistors that are not supplied with 3.3 V between the gate and drain and between the gate and source use a thin oxide layer. In a level-up circuit, a logic operation function is provided.

Abstract: A voltage-level converter and a method of converting a first logic voltage level to a second logic voltage level are described. In one embodiment, a voltage-level converter connects a first logic unit connected to a first supply voltage to a second logic unit connected to a second supply voltage. The voltage-level converter includes at least one transistor connected to the second supply voltage. The at least one transistor has a threshold voltage whose absolute value is greater-than-or-about-equal to the absolute value of the difference between the second supply voltage and the first supply voltage.

Abstract: A variable voltage tolerant input/output circuit, wherein a leakage current is not produced while having high reliability, characterized in that the circuit includes a clamping circuit for clamping the N-well potential of M1. When the supply voltage VCC is higher than or equal to the input/output voltage VI/O, the N-well potential of M1 is clamped to the supply voltage VCC; when the supply voltage VCC is lower than the input/output voltage VI/O, the N-well potential of M1 is clamped to the input/output voltage VI/O.

Abstract: An output driver circuit for a semiconductor device. In one embodiment, the output driver is coupled to an output terminal of the semiconductor device and consists of an N-channel pull-down transistor and a P-channel pull-up transistor formed in an N-well in a P-type substrate. A tie-down region formed in the N-well is selectively coupled to a supply potential by means of a decoupling transistor, and during normal operation of the driver maintains the supply voltage bias of the N-well. An overdrive detection circuit is coupled to the output terminal. Upon detection of an overdrive condition on the output terminal, such as a voltage exceeding a predetermined maximum, or excessive current injected into the output terminal (or both), the overdrive detection circuit deasserts a control signal applied to the gate of the decoupling transistor, thereby decoupling the N-well from the supply potential. In one embodiment, the decoupling transistor is not coupled to the output terminal.

Abstract: A synchronous circuit comprising a first flip-flop which has a first clock input terminal inputting an input signal, a first output terminal outputting a first output signal based on the input signal, a second output terminal outputting a second output signal based on the input signal and a first data input terminal inputting the second output signal; a second flip-flop which has a second clock input terminal inputting a clock signal, a reset terminal inputting a reset signal, a third output terminal outputting a third output signal based on the clock signal and the reset signal, a fourth output terminal outputting a fourth output signal based on the clock signal and the reset signal and a second data input terminal inputting the fourth output signal; a third flip-flop which has a third clock input terminal inputting the third output signal of which voltage level is reversed, a fifth output terminal outputting a fifth output signal based on the reversed third output signal, a sixth output terminal outputting

Abstract: A sense amplifier having a sampling circuit to sample the amplifier input signal; a reference node storing a reference signal corresponding to the input signal; and a timing circuit activating the sampling circuit for a predetermined interval, and admitting the reference signal to the reference node. The sense amplifier also can include a pump capacitor substantially maintaining a value of the reference signal; and a gain circuit coupled with the reference node and disposed to adaptively adjust gain of an output signal produced by the sense amplifier. The sense amplifier can be a single-ended sense amplifier.

Abstract: The comparator input stage uses low voltage transistors 20 and 21 as the input pair. They have a small threshold voltage, and hence support a low common mode. The circuit includes a current sink 22 coupled to the input pair 20 and 21; a first resistor 33 coupled between a first branch of the input pair and a voltage node V24; a second resistor 36 coupled between a second branch of the input pair and the voltage node V24; a first transistor 23 coupled to the voltage node V24; a second transistor 24 having a gate coupled to a gate of the third transistor 23; a third resistor 32 coupled to a first end of the second transistor 24; and a current source 29 coupled to a second end of the second transistor 24 for controlling a voltage across the third resistor 32 wherein the voltage across the third resistor 32 sets a voltage at the voltage node V24. This voltage at the voltage node V24 serves as an open loop regulation for protection of the input pair transistors 20 and 21.

Abstract: The present invention relates to a device and method for selecting within a group of analog signals the one with the lowest or with the highest value. In one embodiment the device comprises a differential amplifier configuration having an input to receive a comparison signal, a plurality inputs to receive analog signals and a corresponding plurality of outputs to provide digital voltage signals. This device also comprises at least one logic circuit having a plurality of input terminals, each connected to a corresponding output of the differential amplifier configuration, and having at least one output terminal. Finally, this device incorporates at least one plurality of latches each having at least one input terminal connected to a corresponding output of the differential amplifier configuration and at least one drive terminal coupled to the output terminal of the logic circuit with each of said latch circuits having at least one output terminal corresponding to an output of the selector.

Abstract: A digital interconnect system transmits pulses across a differential transmission line in response to transitions in an input data signal.

Abstract: A digital input signal is analyzed by a peak detector (210) configurable to trigger a first logic signal (260) if the peak detector detects the digital input signal level crossing a certain threshold. The threshold value can be modified by an overhead. The amplifier (250) employs a plurality of supply rails of differing voltages (253, 255) as a function of the logic signals. A digital signal delay element (220) may delay the signal to allow sufficient time for the amplifier to switch between supply sources. A logic delay element (280) may delay transmittal of the first logic signal by the peak detector to compensate for signal delay caused by a filter. A hold element (270) ensures that the first logic signal is applied to the output amplifier for a given amount of time.

Abstract: A half sine wave resonant drive circuit provides a greater duty cycle range of operation without a loss in power, particularly at higher frequencies. A resonant circuit is capacitivly coupled to a single switching device to provide the greater duty cycle range by recycling the gate charge of the switching device through the resonant circuit. A half sine wave drive signal is thereby produced from an input square wave signal. The driving amplitude is constant for operation over the range of duty cycles.

Abstract: A data output buffer is disclosed that is capable of reducing the power consumption of a circuit utilizing low power consumption in such a way that a data output buffer driver of the data output buffer is turned off to place a data output signal at a HIGH impedance state during a deep power mode wherein all internal supply voltages used are in an OFF state. Therefore, the data output buffer can prevent a data contention in a data bus and shut off a current path to prevent unnecessary power consumption.

Abstract: A digital frequency synthesizer (DFS) circuit adds little additional delay on the clock path. True and complement versions of an input clock signal are provided to a first and second passgates, respectively. Under the direction of a control circuit, the passgates pass selected rising edges of the true clock signal, and selected falling edges of the complement clock signal, to an output clock terminal of the DFS circuit. When neither the true nor the complement clock signal is passed, a keeper circuit retains the value already present at the output clock terminal. In some embodiments, both passgates can be disabled and a ground or power high signal can be applied to the output terminal. Other embodiments include PLDs in which the DFS circuits are employed to allow individual clock control for each programmable logic block.

Abstract: The present invention provides a semiconductor integrated circuit device and a communication device incorporating same. Two MOS (strong and weak) devices are connected to each control input of a transceiver. Both MOS devices are turned on while the supply voltage is ramping from 0V. The strong device remains on for a period of 10-20 microseconds. The strong MOS device pulls the input to a disabled state against external capacitance which is attempting to pull the input to an enabled state. The weak MOS device remains on while pulling the input to a disabled state. The input is pulled to an enabled state when an external source overcomes the weak MOS device. Once the control input is pulled beyond the input voltage threshold to the enabled state, the weak MOS device will be turned off permanently and the input will revert to a standard CMOS input with infinite input resistance.

Abstract: A method for synchronizing a plurality of sub-systems, comprising the steps of measuring a relationship between a divider associated with each of the plurality of sub-systems; and adjusting a phase of one or more of the dividers to a known relationship with one of the dividers. A command is issued synchronous to a divider associated with one of the plurality of sub-systems. The command is received at one of the sub-systems and is acted upon synchronous to a divider associated with the one of the sub-system receiving said command.

Abstract: Dual loop phase lock loops having a high loop bandwidth with low power consumption are described. Each loop is provided with a voltage supply regulator circuit which regulates the voltage of a portion of each loop. In one embodiment, the outer loop employs a regulation circuit comprising a two stage operational amplifier which is compensated by a compensation circuit that is configured to ensure that the dominant pole of the operational amplifier is associated with the first stage of the operational amplifier.

Abstract: A semiconductor device is disclosed which includes an input unit for charging and discharging an output terminal in response to an input signal; and a dummy input unit to reduce jitter in a voltage associated with the output terminal.

Abstract: A differential charge pump includes a first current, a second current, a first switching device, a second switching device, a first phase inverting switching device, a second phase inverting switching device, and a common mode feedback device. The common mode feedback device is used to adjust the current level exported by the first current source, according to the common mode voltage of the differential charge pump, so that the respective currents exported by the first current source and the second current source are to be the same. The present invention has used the property that the common mode voltage of the differential charge pump should be a constant value, so as to correct the level of the current source. As a result, the current exported by the differential charge pump can be precisely corrected. Also, the present invention only needs one set of charge pump, so that the structure is simple and the fabrication is easy.

Abstract: Flip-flop circuitry having an input configured to receive an input signal and an output configured to deliver an output signal corresponding to the input signal; a clock terminal configured to provide timing signals for reception of the input signal at the input and transmission of the output signal at the output; two on-path inverters connected serially between the input and output, and configured not to respond to the timing signals; and two feedback inverters respectively connected in parallel with the two on-path inverters, the first and second feedback inverters being configured to respond to the timing signals.

Abstract: A latch circuit is arranged by means for detecting a signal, a unit for holding a signal detection condition, and a unit for releasing the signal detection condition. When a detection output produced from the detecting unit is entered into the signal detection condition holding unit, the signal detection condition holding unit continuously holds the detection condition until a power supply is interrupted even when the detection output is not entered thereinto. The signal detection condition releasing unit produces a release signal only when the power supply is turned ON. Once the signal detection condition holding unit holds the signal detection condition, the signal detection condition holding unit is reset to an undetection condition only when the power supply is interrupted and then is again turned ON. The latch circuit can firmly reset the stopped system to the initial condition by merely again turning ON the power supply.

Abstract: A method for compensating a baseline wander of a transmission signal and related circuit are provided. The transmission signal includes a plurality of first pulses and a plurality of second pulses for representing digital data coded in the transmission signal. The method includes generating an accumulation result according to a number of the first pulses and a number of the second pulses for estimating the baseline wander of the transmission signal, and compensating the baseline wander of the transmission line according to the accumulation result.

Abstract: An ESD protection circuit protecting an internal circuit from ESD damage. The internal circuit is connected to a voltage interface and powered by a first and second power supply. A first signal with a first amplitude received from a pad is transformed to a second signal with a second amplitude by the voltage interface. The second signal is input to the internal circuit. A first and second diode are serially but inversely connected between the pad and the first power supply.

Abstract: A driver circuit is disclosed for driving a half bridge driver or similar circuit. The driving circuit induced transient currents in two passive devices, and utilizes the transient currents to set or reset a latch at appropriate times required to properly drive a half bridge driver or similar type of circuit.