Abstract: This invention provides improved electroporation methods for transferring nucleic acids of interest into host cells, wherein the host cells are (1) suspended in a substantially non-ionic solution comprising at least one sugar or sugar derivative, (2) mixed with the nucleic acids of interest, and (3) electrically treated. Also, this invention provides for kits used in the method for transferring nucleic acids into host cells.

Abstract: An improved method of gene targeting, referred to as PCR-based gene targeting is disclosed, which generates cell lines or mice in which at least one allele of a specific gene is disrupted by double homologous recombination of a PCR-derived targeting vector with chromosomal DNA. The method is especially applied to murine macrophage cytokine-inducible nitric oxide synthase (MøiNOS).

Abstract: A method for engineering and utilizing large DNA vectors to target, via homologous recombination, and modify, in any desirable fashion, endogenous genes and chromosomal loci in eukaryotic cells. These large DNA targeting vectors for eukaryotic cells, termed LTVECs, are derived from fragments of cloned genomic DNA larger than those typically used by other approaches intended to perform homologous targeting in eukaryotic cells. Also provided is a rapid and convenient method of detecting eukaryotic cells in which the LTVEC has correctly targeted and modified the desired endogenous gene(s) or chromosomal locus (loci) as well as the use of these cells to generate organisms bearing the genetic modification.

Abstract: This invention relates to a nucleic acid molecule encoding the catalytic subunit of a protein phosphatase (PP2AC-JD) that belongs to the PP2A family. The PP2AC-JD interacts with the phytochrome A, a primary photoreceptor in the light signal transduction in plants, in the photoperiodic control of flowering. The present invention also provides the methods and processes for generating transgenic higher plants transformed with said nucleic acid molecule to engineer flowing time of economically important crop plants.

Abstract: A method for the detection of cell contents, the method comprising the steps of, introducing a cell into a channel in a microchip; lysing the cell to release cell contents into the channel; moving the cell contents towards a detection zone; and detecting the cell contents at the detection zone. An apparatus for the detection of cell contents, the apparatus comprising: a microchip; a cell mobilization channel formed in the microchip, the cell mobilization channel having a cell introduction end and a detection end; a cell mobilizer operably connected with the cell introduction end for moving cells from the cell introduction end to the detection end; means for lysing cells in the cell mobilization channel at a lysing zone, the lysing zone being located between the cell introduction end and the detection end; and a detector, disposed adjacent the detector end, arranged to detect cell contents appearing at the detector end that have been moved from the lysing zone to the detector end by the cell mobilizer.

Abstract: An article, apparatus and method for simulating poisoning and deactivating catalysts with catalyst poison compounds at least one catalyst poison compound selected from the group consisting of a compound comprising phosphorous, a compound comprising zinc compound and a compound comprising phosphorous and zinc.

Abstract: This invention relates to an automated device for loading a centrifuge where tubes are presented to the centrifuge via an automated routing system.

Abstract: Chemical sensor compositions and methods for quantifying analytes are described. The chemical sensors include analyte-binding moieties and reporter moieties covalently attached to a framework including two trityl groups connected by a linear spacer such as ethyne or butadiyne. The sensors chelate an analyte across the acetylene axis of the molecule to stabilize the molecule in an eclipsed rotamer conformation. This conformation causes the sensors to emit a measurable signal.

Abstract: A multiwell plate scanner comprises a detector for measuring an attribute of a sample which is scanned continuously over wells of a multiwell plate. A signal obtained during the scan may be sampled and digitized based on detector position over the multiwell plate. The scanner is also disclosed for scanning microarrays, bio-chips and areas of samples not having physical separations. The scanner may be used in a high throughput screening system comprising a storage and retrieval module, a sample distribution module, a reagent distribution module, and a detector which incorporates the scanner. The screening system may further comprise a transport module and a data processing and integration module for transporting samples between the components of the system and for controlling system operation.

Abstract: In accordance with the invention, a liquid sample for thermal analysis is disposed within a receptacle having a bottom surface and side walls. The top edges of the side walls are bent towards the center of the receptacle. A sheet of flexible, transparent material substantially impermeable to the sample is disposed across the top edges of the side walls, and an open lid compresses an o-ring onto the sheet material, sealing it against the bent top edges of the receptacle. The bottom surface of the receptacle is advantageously coated with a a material not wetted by the sample such as a fluorcarbon.

Abstract: A platelet/leukocyte interaction assay method and reagent therefor are provided using the presence of a solid-phase stimulus, such as magnetic or non-magnetic particles or mixtures thereof, having bound to the surface thereof one or more ligands that interact directly with platelets, leukocytes or both, for providing a fast, reliable point-of-care assessment of platelet/leukocyte interaction.

Abstract: A method of forming an electrode and a ferroelectric thin film thereon, includes preparing a substrate; depositing an electrode on the substrate, wherein the electrode is formed of a material taken from the group of materials consisting of iridium and iridium composites; and forming a single-phase, c-axis PGO ferroelectric thin film thereon, wherein the ferroelectric thin film exhibits surface smoothness and uniform thickness.

Abstract: In the method for determining a preceding wafer, at least one semiconductor wafer is determined as a preceding wafer among a plurality of semiconductor wafers constituting one lot. The preceding wafer is then subjected to a given process among a plurality of processes for fabrication of a semiconductor device. The determination of the preceding wafer is based on processing results of an upstream process among the plurality of processes performed for the plurality of semiconductor wafers prior to the given process. After examination of processing results of the given process on the preceding wafer, the given process is performed for the plurality of semiconductor wafers other than the preceding wafer.

Abstract: The present invention is a method for end point detection where emission spectra are detected during etching of an object to be processed, such as a semiconductor wafer, by a spectrometer, and an end point of the etching is detected, comprising performing etching of a sample, corresponding to a product, prior to etching of a semiconductor wafer which is the product, sequentially measuring full-spectra of plasma, performing principal component analysis of the emission spectra using the emission intensities of all wavelengths of each of the full-spectra, holding the results as data, thereafter obtaining a principal component score for each of the full-spectra sequentially measured during etching of a semiconductor wafer to be manufactured on the basis of the emission intensities of all the wavelengths, and then detecting an end point of etching on the basis of a substantial change of the principal component score for each of the full-spectra sequentially measured.

Abstract: A first method for determining the offset between the origins of the coordinate systems used for inspection of at least two different defect inspections of a wafer with integrated circuits disposed on it, comprises creating a database containing location data for defects disposed on at least two inspection layers of an integrated circuit wafer; defining maximum offsets for interlayer defects; defining minimum spacings for intralayer defects; for all defects having spacings larger than the minimum spacings searching the database for interlayer defect pairs having offsets smaller than the maximum offsets; calculating an actual offset for each interlayer defect pair; determining whether the actual offsets are randomly distributed; identifying dense zones for the actual offsets if they are not randomly distributed; and developing an estimate of the offset between the origins of the at least two layers and a confidence value for the estimate for said actual offsets.

Abstract: For a semiconductor device including a gate electrode in an area of part of a surface of a semiconductor substrate, a gate length is determined and to be set as an upper-limit gate length. For a semiconductor device of which a gate length is almost equal to the upper-limit gate length, an impurity implantation condition is determined to calculate a representative impurity concentration distribution. A limit gate length is obtained according to the representative impurity concentration distribution. For a semiconductor device of which a gate length is equal to or greater than the limit gate length and equal to or less than the upper-limit gate length, an impurity concentration distribution of the semiconductor device is calculated according to the representative impurity concentration distribution. Characteristics of the semiconductor device are obtained according to the impurity concentration distribution. This method reduces the period of time to calculate the characteristics of the semiconductor device.

Abstract: The present invention provides a method of tool matching for a semiconductor manufacturing process having a first and second path completed by serial combinations of tools for processing of wafers. The method comprises the steps of providing a target value, obtaining a first and second test result of the wafers processed through the first and second path respectively, calculating differences between the first and second test result and the target value to obtain a first and second estimate respectively, and selecting one of the first and second paths according to the estimates.

Abstract: A multiple integrated circuit chip structure provides interchip communication between integrated circuit chips of the structure with no ESD protection circuits and no input/output circuitry. The interchip communication is between internal circuits of the integrated circuit chips. The multiple integrated circuit chip structure has an interchip interface circuit to selectively connect internal circuits of the integrated circuits to test interface circuits having ESD protection circuits and input/output circuitry designed to communicate with external test systems during test and burn-in procedures. The multiple interconnected integrated circuit chip structure has a first integrated circuit chip mounted to one or more second integrated circuit chips to physically and electrically connect the integrated circuit chips to one another.

Abstract: A transient fuse (102) and antenna (110) for detecting charge-induced plasma damage in a device (112). When the transient fuse (102) is placed between the antenna (110) and the device (112), only charge-induced damage during a metal clear portion of an etch occurs in device (112). When the transient fuse (102) is placed between ground and both the device (112) and the antenna (110), charge-induced damage occurring during an overetch portion of the etch can be detected in the device (112).

Abstract: An optoelectronic component and a method of manufacturing such a component. The component includes at least one pixel comprising a first and a second electrode for electric coupling. An optoelectronically active material is between the electrodes. The optoelectronically active material is a hybrid sol-gel glass that is chemically supplemented with a material affecting the optoelectronic properties. The component is manufactured by spreading the optoelectronically active hybrid sol-gel on the first electrode, hardening the hybrid sol-gel glass by radiation, and forming the second electrode on the optoelectronically active hybrid sol-gel glass.

Abstract: A photoconductive relay that comprises a light-emitting device, a photoconductive switching element and columns of a conductive, fusible material. The light-emitting device and the photoconductive switching element respectively include including a light-emitting region and a light-receiving region. The columns extend between the light-emitting device and the photoconductive switching element to locate the light-emitting region of the light-emitting device opposite the light-receiving region of the photoconductive switching element and separated from one another by a distance of no more than 100 &mgr;m.

Abstract: A process for producing a stable photovoltaic element having an electrode structure comprising a collecting electrode and a metal bus bar which are connected to have an improved connection between them. Said electrode structure is formed by dotting an electrically conductive paste onto a metal wire as the collecting electrode such that a dotted electrically conductive paste has an elliptical form whose major axis and minor axis are respectively perpendicular to and parallel to a lengthwise direction of said metal wire, arranging the metal bus bar on said dotted electrically conductive paste, and heating the resultant while pressing it to cure the electrically conductive paste to form connection between the metal wire as the collecting electrode and the metal bus bar.

Abstract: A method of manufacturing a solar cell module includes the use of low cost polymeric materials with improved mechanical properties. A transparent encapsulant layer is placed adjacent a rear surface of a front support layer. Interconnected solar cells are positioned adjacent a rear surface of the transparent encapsulant layer to form a solar cell assembly. A backskin layer is placed adjacent a rear surface of the solar cell assembly. At least one of the transparent encapsulant layer and the backskin layer are predisposed to electron beam radiation.

Abstract: The present invention relates to the method for manufacturing an MSM photodetector using a HEMT structure incorporating a low-temperature grown semiconductor. The object of the present invention is to improve the speed characteristic of an MSM photodetector by using a HEMT structure incorporating a low-temperature grown semiconductor. The use of a HEMT structure incorporating a low-temperature grown semiconductor can reduce the number of holes reaching the metal electrode of MSM detectors, resulting in reduced hole current. As a result, the photocurrent response of the MSM detector using a HEMT structure incorporating a low-temperature grown semiconductor is dominated by electron current, resulting in a significant improvement in speed performance.

Abstract: A method of manufacturing a semiconductor device is provided. The method comprises a wire-forming step of forming a wiring on a substrate having an electrode pad so as to connect the electrode pad to a mounting terminal. The wire-forming step includes the steps of: applying a metal foil to the substrate by providing an adhesive therebetween; patterning the metal foil into a predetermined pattern so as to form the wiring; and connecting the wiring to the electrode pad electrically.

Abstract: A semiconductor device comprising a substrate including a metal portion and a resin portion and having a plurality of through holes formed in the resin portion, conductive members formed within the through holes, a semiconductor chip attached to one surface of the substrate, and a plurality of solder balls attached to the other surface of the substrate. The semiconductor chip and solder balls are electrically connected through the conductive members.

Abstract: A thermal-stress-absorbing interface structure between a semiconductor integrated circuit chip and a surface-mount structure and a method for manufacturing the same. The thermal-stress-absorbing interface structure comprises an elongated conductive-bump pad having a first length-wise end and a second length-wise end, and a side. The thermal-stress-absorbing interface structure includes means for allowing the first end of the pad to move up when the second end of the pad moves down and alternately allowing the first end to move down when the second end moves up, upon thermal cycling. The means has a center axis and the up-and-down movements of the pad are balanced on the center axis. In accordance with this novel structure of the present invention, interconnection reliability such as solder joint reliability can be significantly improved.

Abstract: A passivation layer is formed over a semiconductor wafer carrying a plurality of independent circuits. The passivation layer includes openings to expose bond pads on the wafer. A conductive adhesion material is then deposited over the wafer and an optional protection layer is deposited over the conductive adhesion material. The wafer is then cut up into individual microelectronic dice. During a subsequent packaging process, one or more microelectronic dice are fixed within a package core to form a die/core assembly. Expanded bond pads are then formed over the die/core assembly. The adhesion material on each die enhances the adhesion between the expanded bond pads and the passivation material on the die. One or more metal layers are then built up over the die/core assembly to provide, for example, conductive communication between the terminals of the die and the external contacts/leads of the package.

Abstract: A semiconductor package structure for a ball grid array type package using a plurality of pieces of adhesive elastomer film to attach a semiconductor die to a substrate having conductive traces in order to alleviate thermal mismatch stress between the semiconductor die and the printed circuit board to which the packaged device is soldered, while maintaining the reliability of the packaged device itself.

Abstract: A method for mounting an electronic component on a substrate is shown, which involves positioning an electronic component 1 on wiring electrodes 5 of a substrate 4 via bumps 3, application of ultrasonic oscillation to the electronic component 1 where the ultrasonic oscillation of the top portion of an ultrasonic-oscillation applying unit (a collet) 8 is larger than the oscillating amplitude of the electronic component 1. After heating the bumps 3 and an area in proximity thereto, the bumps 3 and the wiring electrodes 5 on the substrate 4 are metallically bonded, thereby mounting the electronic component 1 on the substrate 4 via the bumps 3.

Abstract: A method of integrating a heat spreader into a semiconductor package includes depositing an adhesion metal layer on the back of a wafer at low temperature. A heat transfer metal layer is subsequently deposited on the adhesion metal layer at low temperature to form a heat spreader.

Abstract: A method of manufacturing a semiconductor device including a substrate and a die supported thereon. The substrate has at least one electrical connection region on a first portion of a surface of the substrate. The die has a bottom surface portion supported by a second portion of the surface of the substrate. The die also includes a top surface portion comprising a metal layer and a number of semiconductor elements below the metal layer. The top and bottom surface portions of the die are separated by a die body portion which lies above the surface of the substrate. A conforming metal layer extends from at least a portion of the metal layer of the top surface of the die and electrically interfaces with the at least one electrical connection region on the first portion of the surface of the substrate.

Abstract: Integrated circuit fabrication techniques are provided which allow non-horizontal/non-vertical wires to traverse the entire chip surface, rather than just the corners as in the conventional Manhattan geometry, while interconnecting circuit points. This is achieved by employing a variable rotational assignment methodology with respect to the interconnect layers or levels during the IC fabrication operation. These techniques thus eliminate the litho step problem, reduce interconnect distances and lessen the influence of capacitance interaction between interconnect wires.

Abstract: A method of manufacturing a semiconductor device comprises forming a thin film over a semiconductor substrate, patterning the thin film to define a portion of a laser trimming registration position pattern while simultaneously forming a fuse element formed from the same thin film and separate from the portion of the laser trimming position registration pattern, and forming a metallic film on the portion of the laser trimming position pattern but not on the fuse element.

Abstract: An apparatus and a method for protecting charge storage elements from photo-induced currents in silicon integrated circuits are provided. In order to protect against photo-induced currents that are generated outside the storage node circuits themselves, an n-well guard ring is placed as closely as possible to the transistors and other elements in the storage node circuits. As a result there is a minimum of exposed silicon area in which light can produce current in areas next to the storage node circuits, and the n-well guard ring captures photo-induced currents that are generated outside the storage node circuits. In order to protect against the photo-induced currents that are generated inside the storage node circuits, an aluminum interconnect layer is placed on top of the storage node circuit, separated by an insulating layer of silicon dioxide. This creates a shield against the light and protects the storage node circuit by reflecting light away.

Abstract: The present invention relates to a silicon-on-insulator (SOI) substrate, a method for fabricating the SOI substrate and a SOI MOSFET using the SOI substrate to easily migrate the design applied to a conventional bulk silicon substrate to the SOI design and to remove a floating body effect. The SOI substrate includes a mono-silicon substrate, a buried oxide layer formed over the surface of the mono-silicon substrate, and a thin mono-silicon layer formed over the surface of the buried oxide layer. Conductive layers are formed at through holes of the buried oxide layer positioned between the predetermined regions of the thin layer and the substrate for body contacts. Therefore, additional layout spaces are not needed for body contacts and the constant body contact resistance can allow the conventional circuit design applied to die bulk silicon substrate to be migrated to the circuit design applied to the SOI substrate without any modifications.

Abstract: A first cleaning is conducted on a plasma enhanced chemical vapor deposition chamber at room ambient pressure. After the first cleaning, elemental titanium comprising layers are chemical vapor deposited on a first plurality of substrates within the chamber using at least TiCl4. Thereafter, titanium silicide comprising layers are plasma enhanced chemical vapor deposited on a second plurality of substrates within the chamber using at least TiCl4 and a silane. Thereafter, a second cleaning is conducted on the chamber at ambient room pressure. In one implementation after the first cleaning, an elemental titanium comprising layer is chemical vapor deposited over internal surfaces of the chamber while no semiconductor substrate is received within the chamber. In another implementation, a titanium silicide comprising layer is chemical vapor deposited over internal surfaces of the chamber while no semiconductor substrate is received within the chamber.

Abstract: A thin film transistor substrate for a liquid crystal display includes an insulating substrate, and a gate line assembly formed on the substrate. The gate line assembly has a double-layered structure with a lower layer exhibiting good contact characteristics with respect to indium tin oxide, and an upper layer exhibiting low resistance characteristics. A gate insulating layer, a semiconductor layer, a contact layer, and first and second data line layers are sequentially deposited onto the substrate with the gate line assembly. The first and second data line layers are patterned to form a data line assembly, and the contact layer is etched through the pattern of the data line assembly such that the contact layer has the same pattern as the data line assembly. A passivation layer is deposited onto the data line assembly, and a photoresist pattern is formed on the passivation layer by using a mask of different light transmissties mainly at a display area and a peripheral area.

Abstract: The invention provides a method for fabricating a TFT including a crystalline silicon active layer. The inventive method forms a metal offset region between the metal layer used to induce the cystallization of the active layer and the channel region of the TFT without introducing an additional process such as photoresist processing. Therefore, the inventive method improves the performance and manufacturing productivity of TFT and lower its production cost as well.

Abstract: A method of forming dual-metal gates in a semiconductor device, including the steps of providing a semiconductor substrate having a PMOS area and an NMOS area wherein dummy gates are formed in the PMOS and NMOS areas respectively, forming an insulating interlayer on the semiconductor substrate so as to cover the dummy gates, polishing the insulating interlayer until the dummy gates are exposed, forming a first groove defining a first metal gate area by selectively removing one of the dummy gates formed in the PMOS and NMOS areas, forming a first gate insulating layer and a first metal layer on an entire area of the semiconductor substrate including the first groove successively, forming a first metal gate in the first groove by etching the first metal layer and first gate insulating layer until the insulating interlayer is exposed, forming a second groove defining a second metal gate area by removing the remaining dummy gate, forming a second gate insulating layer and a second metal layer on the entire area o

Abstract: A method and structure for improving the gate activation of metal oxide semiconductor field effect transistor (MOSFET) structures are provided. The method of the present invention includes the steps of forming a structure having a plurality of patterned gate stacks atop a layer of gate dielectric material; forming a non-conformal film on the structure including the plurality of patterned gate stacks; blocking some of the plurality of patterned gate stacks with a first resist, while leaving other patterned gate stacks of said plurality unblocked; implanting first ions into the unblocked patterned gate stacks; removing the first resist and blocking the previously unblocked patterned gate stacks with a second resist; implanting second ions into the patterned gate stacks that are not blocked by the second resist; and removing the second resist and the non-conformal film.

Abstract: An ESD protection structure for I/O pads is formed with well resistors underlying the active areas of a transistor. The well resistors are coupled in series with the active areas and provide additional resistance which is effective in protecting the transistor from ESD events. Metal conductors over the active areas, have a plurality of contacts to the active areas formed through an insulative layer to contact the active areas. Additional active areas adjacent to the active areas of the transistor are also coupled to the well resistors, and to a conductive layer which provides a conductor to the I/O pads. The active areas are silicided to reduce their resistance and increase the switching speed of the transistor. The n-well resistors are coupled in series to provide a large resistance with respect to that of the active areas to reduce the impact of ESD events.

Abstract: A memory cell having a transistor and a capacitor formed in a silicon substrate. The capacitor is formed with a lower electrically conductive plate etched in a projected surface area of the silicon substrate. The lower electrically conductive plate has at least one cross section in the shape of a vee, where the sides of the vee are disposed at an angle of about fifty-five degrees from a top surface of the silicon substrate. The surface area of the lower electrically conductive plate is about seventy-three percent larger than the projected surface area of the silicon substrate in which the lower electrically conductive plate is etched. A capacitor dielectric layer is formed of a first deposited dielectric layer, which is disposed adjacent the lower electrically conductive plate. A top electrically conductive plate is disposed adjacent the capacitor dielectric layer and opposite the lower electrically conductive plate.

Abstract: A methodology of creating integrated circuits with improved noise isolation is presented. The circuitry of an integrated circuits is separated into noise generating circuit blocks and noise sensitive circuit blocks. N-type and P-type diffusion guard rings are placed around each of the circuit blocks. Substantially overlying the N-type and P-type diffusion guard rings are power supply meshes which are intimately in contract with the guard rings below through spaced apart vias. The power supply meshes not only supply power for the circuit blocks, but also reverse-bias the diffusion guard rings for improved noise isolation.

Abstract: To prevent a thick gate oxide film from being damaged by a cleaning and hydrofluoric-acid treatment preprocess performed prior to formation of a thin gate oxide film. A thick first gate oxide film is formed, and an insulating film, having etching resistance against the cleaning and hydrofluoric-acid treatment process for formation of thin second gate oxide film, is formed in an upper region of the first gate oxide film. A resist is then formed in a region where a thick gate insulating film is to be formed, and etching is performed on the first gate oxide film with the resist as a mask. The resist is stripped, then cleaning and hydrofluoric-acid treatment are performed on the silicon surface in a region where a thin gate insulating film is to be formed, and the thin second gate oxide film is formed.

Abstract: A method for processing dual threshold nMOSFETs and pMOSFETs requiring only one additional masking and implantation operation over single threshold MOSFETs is disclosed. The additional mask and implant operation both enhances the threshold voltage doping of one type of FET and compensates the threshold voltage doping of another type of FET. Where a first threshold voltage implant sets the threshold voltage for an NMOS device to a low threshold voltage, and a second threshold voltage implant sets the threshold voltage for a PMOS device to a high threshold voltage, a third implant may both enhance a NMOS device threshold implant to set the threshold voltage high while compensating a PMOS device threshold implant to set the threshold voltage low.

Abstract: A trench 5 for element separation is formed in a silicon substrate 1 by an etching process using an SiO2 film 2 as a mask (FIG. 1B). Side walls 18 are formed in a manner covering the trench 5 laterally (FIG. 1C). Defect-forming ions such as silicon ions are implanted into the silicon substrate 1 with the SiO2 film 2 and side walls 18 used as a mask, whereby a gettering layer 1 is formed only at a bottom of the trench 5.

Abstract: A method is provided for processing a semiconductor topography. In particular, a method is provided for forming wells of opposite conductivity type using a single patterned layer. In addition, the method may include forming a silicon layer having first and second portions of opposite conductivity type. The formation of the silicon layer may include the use of the single patterned layer or an additional patterned layer. In addition, the method may include forming channel dopant regions within the wells of opposite conductivity type. The formation of such channel dopant regions may be incorporated into the method using the one or two patterned layers used for the formation of the wells and doped silicon layer. Such a method may include introducing impurities at varying energies and doses to compensate for the introduction of subsequent impurities. As such, the method may form a dual gate transistor pair, including n-channel and p-channel transistors.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor is fabricated by forming a metastable epitaxial silicon-germaniuim base on a collector. The metastable epitaxial silicon-gernaniuim base, for example, may have a concentration of germanium greater than 20.0 atomic percent of germanium. The heterojunction bipolar transistor, for example, may be an NPN silicon-germanium heterojunction bipolar transistor. According to this exemplary embodiment, the heterojunction bipolar transistor is further fabricated by fabricating an emitter over the metastable epitaxial silicongermanium base. The heterojunction bipolar transistor is further fabricated by doping the emitter with a first dopant. The first dopant, for example, may be arsenic.

Abstract: A method of fabricating a bipolar transistor structure is provided in which a blanket silicon-germanium (SiGe) film is used in a self-aligned manner to form the active base region of the bipolar device, thereby eliminating the need for a complicated selective SiGe process.