Abstract: A nitride semiconductor light emitting device includes an emission layer (106) having a multiple quantum well structure where a plurality of quantum well layers and a plurality of barrier layers are alternately stacked. The quantum well layer is formed of XN1-x-yAsxPySbz (0≦x≦0.15, 0≦y≦0.2, 0≦z≦0.05, x+y+z>0) where X represents one or more kinds of group III elements. The barrier layer is formed of a nitride semiconductor layer containing at least Al.

Abstract: An electronic device containing a polythiophene of Formula (I) 1

Abstract: An organic light-emitting device comprising: a back electrode; an organic light-emitting layer; a transparent electrode; a first reflective mirror; a substrate; and a second reflective mirror in this order, the second reflective mirror having R1(&thgr;=0°) of 80 to 100% and R2(&thgr;=0°) of 0 to 40%, wherein R1(&thgr;) is an average reflectance at a wavelength &lgr; being 400 nm to (&lgr;0−&Dgr;&lgr;) (where &lgr;0 is a resonance wavelength; and &Dgr;&lgr;=&lgr;max−&lgr;0, &lgr;max is a maximum wavelength that is obtained by measuring reflectance having the same value equal to R&agr; in a wavelength range about 400-700 nm, and R&agr; is an average reflectance at a wavelength range from 400 nm to (&lgr;0−100) nm) at an incidence angle &thgr;, and R2(&thgr;) is an average reflectance at a wavelength &lgr; is &lgr;0 to 700 nm at an incidence angle &thgr;.

Abstract: Techniques are used to detect and identify analytes. Techniques are used to fabricate and manufacture sensors to detect analytes. An analyte (810) is sensed by sensors (820) that output electrical signals in response to the analyte. The electrical signals may be preprocessed (830) by filtering and amplification. In one embodiment, a plurality of sensors are formed on a single integrated circuit. The sensors may have diverse compositions.

Abstract: A silicon wafer having a controlled oxygen precipitation behavior such that a denuded zone extending inward from the front surface and oxygen precipitates in the wafer bulk sufficient for intrinsic gettering purposes are ultimately formed. Specifically, prior to formation of the oxygen precipitates, the wafer bulk comprises dopant stabilized oxygen precipitate nucleation centers. The dopant is selected from a group consisting of nitrogen and carbon and the concentration of the dopant is sufficient to allow the oxygen precipitate nucleation centers to withstand thermal processing such as an epitaxial deposition process while maintaining the ability to dissolve any grown-in nucleation centers.

Abstract: The active matrix display device has a thin film transistor and a pixel electrode, which is provided with a pixel voltage through the thin film transistor, for each of pixels. A supplemental pixel electrode, which is connected to the pixel electrode of one of the pixels adjacent to each other, and which extends to the region between the two pixels adjacent to each other, is also disposed. The supplemental pixel electrode enables the region between the pixels to be used as a part of the display region. The liquid crystal of this region is also driven by the voltage same as the pixel electrode. The configuration of the peripheral circuit of the pixel portion is simplified, reducing the framing area of the panel.

Abstract: A self-aligned transistor including a first silicon portion on an isolation layer, the silicon portion having formed therein a source region and a drain region separated by a channel region. The channel region has a first side and a second side and a top portion, and a gate oxide surrounds the channel on said first side, second side and top portion. A first, a second and a third silicon gate regions are positioned in a second silicon portion surrounding the first silicon portion about the first side, second side and top portion and the channel region.

Abstract: The present invention describes thin film transistors in which the active channel layer is a thin film of a polycyclic aromatic compound, such as, pentacene, prepared by solution processing a soluble precursor of the polycyclic aromatic compound on a substrate followed by heating to a moderate temperature to convert the precursor back to the polycyclic aromatic compound. The soluble precursors of the polycyclic aromatic compounds are organic solvent-soluble Diels-Alder adducts of polycyclic aromatic compounds, such as, oligothiophene, perylene, benzo[ghi]perylene, coronene and a polyacene with a variety of dienophiles that contain at least one heteroatom. The Diels-Alder adducts can be converted back to pentacene by retro-Diels-Alder reaction at moderate (60-250° C.) temperatures both in bulk, in solution or as thin-films.

Abstract: A semiconductor diode has a semiconductor die that includes a substrate, a first semiconductor film, a second semiconductor film, a first metal contact, and a second metal contact. The semiconductor die defines two diagonally opposite first corners and two diagonally opposite second corners. The first semiconductor film has an exposed area that is exposed from the second semiconductor film and that extends between one of the first corners and one of the second corners. The first metal contact is formed on the exposed area and has an extension section and a wire-bonding section that has a width greater than that of the extension section and a length less than that of the extension section. The second metal contact extends between the other one of the first corners and the other one of the second corners and has an extension section and a wire-bonding section that has a width greater than that of the extension section and a length less than that of the extension section.

Abstract: An organic EL display unit is manufactured in an efficient manner. A light emission device (1000) is manufactured by bonding together a driving circuit substrate (100) formed with driving circuit constituted by thin film transistors 11, and a light emission substrate (300) comprising a successively laminated transparent electrode layer 31, bank layer 32 made from insulating material, positive hole injection layer 33, organic EL layer 34 and cathode layer 36.

Abstract: A switching device for switching a plurality of RF signal lines to deliver a selected one of the RF signals to a receiver has an isolation D/U characteristic as high as 40 dB or higher. The switching device includes a mounting board made of dielectric and a matrix switch mounted thereon and implemented by one or more of SWIC. The RF signal lines in the switching device has no crossing point therebetween on either side of the mounting board to achieve the high isolation D/U ratio or lower cross-talk.

Abstract: A microelectronic package including an optoelectronic element having a front face including contacts and a rear surface; flexible conductive leads having first ends connected to the contacts and second ends connected to conductive pads adjacent the optoelectronic element; and an at least partially transparent encapsulant covering the optoelectronic element, the flexible leads and the conductive pads, the conductive pads being exposed on a bottom surface of the encapsulant, the bottom surface of the encapsulant defining a bottom of the package, wherein the encapsulant at the bottom of the package extends between the conductive pads.

Abstract: In a process for producing a semiconductor light emitting device, first, a lamination including an active zone, cladding layers, and a current confinement layer is formed. Then, a near-edge portion of the lamination having a stripe width is removed so as to produce a first space, and a second near-edge portion located under the first space and a stripe portion of the lamination being located inside the first space and having the stripe width are concurrently removed so that a second space is produced, and cross sections of the active layer and the current confinement layer are exposed in the second space. Finally, the first and second spaces are filled with a regrowth layer so that a dopant to the regrowth layer is diffused into a near-edge region of the remaining portion of the active layer.

Abstract: In a semiconductor light emitting device such as a semiconductor laser using nitride III-V compound semiconductors and having a structure interposing an active layer between an n-side cladding layer and a p-side cladding layer, the p-side cladding layer is made of an undoped or n-type first layer 9 and a p-type second layer 12 that are deposited sequentially from nearer to remoter from the active layer. The first layer 9 is not thinner than 50 nm. The p-type second layer 12 includes a p-type third layer having a larger band gap inserted therein as an electron blocking layer. Thus the semiconductor light emitting device is reduced in operation voltage while keeping a thickness of the p-side cladding layer necessary for ensuring favorable optical properties.

Abstract: A gate wire including a gate line, a gate pad and a gate electrode is formed on a substrate. A gate insulating layer, a semiconductor layer, a doped amorphous silicon layer and a conductive layer are deposited in sequence, and then a photoresist film pattern is formed thereon. The photoresist film pattern includes a first portion positioned between a source electrode and a drain electrode, a second portion thicker than the first portion, and the third portion with no photoresist. A data wire including a data line, a data pad, a source electrode, a drain electrode and a conductor pattern for storage capacitor, an ohmic contact layer pattern and a semiconductor pattern are formed by etching the conductive layer, the doped amorphous silicon layer and the semiconductor layer using the photoresist film pattern. A plurality of color filters of red, green and blue having apertures exposing part of the drain electrode are formed thereon.

Abstract: An optoelectronic module has at least two components, which are coupled via an optical waveguide, in a monolothically integrated structure. At least two of the components of the module are coupled in series to form an associated PINIP structure, with at least one active layer of the waveguide having a multiquantum well structure, in particular in at least two quantum well types. The optoelectronic module can be driven quite efficiently.

Abstract: The present invention provides a semiconductor device in which a V-groove for holding an optical fiber and an alignment groove for adjusting the distance between the optical fiber and an optical element chip are formed in an optical fiber packaging region on the upper face of a semiconductor substrate, and an optical element chip is packaged in an optical element packaging region on the upper face of the semiconductor substrate so that its optical axis matches the direction in which the V-groove extends. A semiconductor integrated circuit is formed on the lower face of the semiconductor substrate. Through holes are provided in the optical element packaging region of the semiconductor substrate, passing from its upper face to its lower face, and the optical element chip and the semiconductor integrated circuit are connected via the through holes.

Abstract: An IGBT has a thick buffer region with increased doping to improve self-clamped inductive switching and device manufacture. A planar or trench gate IGBT has a buffer layer more than 25 microns thick. The buffer layer is doped high enough so that its carriers are more numerous than minority carriers, particularly at the transition between the N buffer & N drift region.

Abstract: A method for improving the SiGe bipolar yield as well as fabricating a SiGe heterojunction bipolar transistor is provided. The inventive method includes ion-implanting carbon, C, into at one of the following regions of the device: the collector region, the sub-collector region, the extrinsic base regions, and the collector-base junction region. In a preferred embodiment each of the aforesaid regions include C implants.

Abstract: A first address subset is allocated as a first column address in a nonvolatile semiconductor memory. In addition, a second address subset higher in order than the first address subset is allocated as a first row address. Furthermore, a third address subset higher in order than the second address subset is allocated as a second column address.

Abstract: A semiconductor integrated circuit includes cells, cell rows and potential feeders. Each cell includes a partial trunk that is used to constitute a power supply trunk and/or a ground trunk, and that is electrically isolated from the remaining components within the cell. Each cell row includes a plurality of cells placed adjacently, and the power supply trunk and/or ground trunk composed of the partial trunks. The potential feeders selectively connect one of the power supply trunk and ground trunk of any one of the plurality of cell rows to the components within the cells to supply them with the potential of the power supply trunk and/or ground trunk. This enables the components in the adjacent cells to be supplied with different potentials.

Abstract: The invention provides a semiconductor memory device comprising a plurality of word lines, a plurality of bit lines, and a plurality of static memory cells each having a first, second, third, fourth, fifth, and sixth transistors. While each of channels of the first, second, third, and fourth transistors are formed vertical against a substrate of the semiconductor memory device. Each of semiconductor regions forming a source or a drain of the fifth and sixth transistors forms a PN junction against the substrate. According to another aspect of the invention, the SRAM device of the invention has a plurality of SRAM cells, at least one of which is a vertical SRAM cell comprising at least four vertical transistors onto a substrate, and each vertical transistor includes a source, a drain, and a channel therebetween aligning in one aligning line which penetrates into the substrate surface at an angle greater than zero degree.

Abstract: A bonding pad structure in an integrated circuit (IC) and a method for manufacturing thereof comprises a plurality of dummy patterns deposited in sub-layers of the IC, each dummy pattern being connected via a metal link to a plurality of complementary top surface bonding pads, wherein the dummy patterns and the metal link are constructed during the same process steps used to construct the circuit elements included in the IC, without additional or special process steps. Such an imbedded and anchored bonding pad provides contact reliability for both conductive and non-conductive pads used for the interconnection of integrated circuits in a manner that resists layer separation or de-lamination under pulling stresses that are present on the bonding pads.

Abstract: An exposure control method for an image pickup apparatus with a CMOS image sensor comprises the steps: opening an mechanical shutter to guide incident light falling on the CMOS image sensor; generating a signal for eliminating residual image data, and initiating exposure controlled by an electronic shutter in the CMOS image sensor; generating an instruction for closing the mechanical shutter before the exposure finished; beginning to close the mechanical shutter after the exposure finished; and starting to read out the image data acquired as soon as the mechanical shutter has been closed completely.

Abstract: A solid-state imaging device having, in each of unit pixels, an on-chip microlens composed of plural convex lens parts for each of photoelectric conversion elements provided on a semiconductor chip is disclosed. A floating diffusion part and a signal-charge read gate for taking out a signal charge from the photoelectric conversion element are provided on a region positioned in a boundary of each convex lens part of the on-chip microlens. A wiring for the floating diffusion part and a wiring for the read gate are provided along the respective boundaries of the convex lens parts of the on-chip microlens. In this device, the film thickness of the on-chip microlens can be reduced with regard to the area of each unit pixel, thereby facilitating the process control and enhancing the light transmission efficiency. It is also possible to enhance the circuit wiring efficiency in each unit pixel while avoiding any incomplete charge transfer to consequently improve the picture quality.

Abstract: A CMOS imager having multiple graded doped regions formed below respective pixel sensor cells is disclosed. A deep retrograde p-well is formed under a red pixel sensor cell of a semiconductor substrate to increase the red response. A shallow p-well is formed under the blue pixel sensor cell to decrease the red and green responses, while a shallow retrograde p-well is formed below the green pixel sensor cell to increase the green response and decrease the red response.

Abstract: The invention relates to a phase-change memory device. The device includes a lower electrode disposed in a recess of a first dielectric. The lower electrode comprises a first side and a second side. The first side communicates to a volume of phase-change memory material. The second side has a length that is less than the first side. Additionally, a second dielectric may overlie the lower electrode. The second dielectric has a shape that is substantially similar to the lower electrode.

Abstract: There is provided a semiconductor device comprising a gate electrode which is formed on a semiconductor substrate through a gate insulating film and in which a plurality hexagonal rings are mutually connected so as to form a honeycomb structure, drain diffusion layers each formed in the semiconductor substrate on the inside of one hexagonal ring, source diffusion layers formed in the semiconductor substrate on the inside of a plurality of hexagonal rings which are adjacent to the hexagonal ring having the drain diffusion layer formed therein, and, insulating layers formed between respective source diffusion layers in the semiconductor substrate.

Abstract: A microelectronic structure includes at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type. In a further aspect of the invention, a process for forming a microelectronic structure, such as a MOSFET, having at least one source/drain terminal of a first conductivity type that is partially isolated from a region of semiconductor material of a second conductivity type includes forming a recess having a surface, forming a dielectric material over a portion of the surface of the recess, and back-filling the recess to from a source/drain terminal.

Abstract: Transition metal doped III-V nitride material films exhibit ferromagnetic properties at or above room temperature. A III-V nitride material film may be doped with a transition metal film in-situ during metal-organic chemical vapor deposition and/or by solid-state diffusion processes. Doping of the III-V nitride material films may proceed in the absence of hydrogen and/or in the presence of nitrogen. In some embodiments, transition metal-doped III-V nitride material films comprise carbon concentrations of at least 1017 atoms per cubic centimeter.

Abstract: In a non-volatile semiconductor storage device, a barrier layer is disposed, via an interlayer isolating film, in an area surrounding a floating gate, including an area adjoining a connecting part of the floating gate, without covering the floating gate. The edge of the barrier layer is, in an overhead view relative to the surface of the semiconductor substrate, disposed at a space of 2 &mgr;m apart from the edge of the floating gate.

Abstract: Semiconductor container capacitor structures having a diffusion barrier layer to reduce damage of the bottom cell plate and any underlying transistor from species diffused through the surrounding insulating material are adapted for use in high-density memory arrays. The diffusion barrier layer can protect the bottom cell plate, any underlying access transistor and even the surface of the surrounding insulating layer during processing including pre-treatment, formation and post-treatment of the capacitor dielectric layer. The diffusion barrier layer inhibits or impedes diffusion of species that may cause damage to the bottom plate or an underlying transistor, such as oxygen-containing species, hydrogen-containing species and/or other undesirable species. The diffusion barrier layer is formed separate from the capacitor dielectric layer. This facilitates thinning of the dielectric layer as the dielectric layer need not provide such diffusion protection.

Abstract: There is described an integrated device comprising a thin-film capacitor formed of first and second electrodic layers, electrically separated by a dielectric layer formed of a hydrogen-degradable compound characterized in that it further comprises at least a getter layer of a material of the group consisting of the alloys of zirconium, vanadium and iron, optionally containing minor quantities of manganese and/or elements of the “Rare Earths” group, alloys of zirconium with at least one among the metals of the group consisting of iron, cobalt and nickel, optionally containing up to 15% by weight of elements belonging to the “Rare Earths” group.

Abstract: An integrated circuit configuration includes a semiconductor body having a first semiconductor zone of a first conductivity type in a region near a rear side and a second semiconductor zone of the first conductivity type adjoining the first semiconductor zone and doped more weakly than the first semiconductor zone in a region near a front side, a first component region in the body having at least one semiconductor zone of a second conductivity type, a second component region in the body having at least one semiconductor zone of the second conductivity type, and a conversion structure having a semiconductor zone of the second conductivity type and a semiconductor zone of the first conductivity type that are short-circuited and disposed at a distance from the first semiconductor zone between the first and second component regions in the second semiconductor zone.

Abstract: A process for manufacturing a thin film transistor liquid crystal display (TFT-LCD) is disclosed. The process can reduce the number of the mask used in the photolithography process to three masks, form a capacitor during the manufacturing process simultaneously, and enhance the transmission rate of the TFT-LCD. Because the pixel electrodes are formed directly on the substrate, without forming an insulator layer in the pixel area, the transmission can be enhanced. The manufacturing process also provides a protective circuit for avoiding electrostatic discharge damage, and a passivation layer to protect the capacitor, the gate line, and the signal line.

Abstract: In a multi-terminal MOS varactor, a floating electrode 8 of a MOS capacitor (Cf) 5 is connected to one of two terminals of each of a plurality of capacitors (C1-Cn) 6-1 through 6-n. To the other terminals (Vg1-Vgn) 9-1 through 9-n of the respective capacitors (C1-Cn) 6-1 through 6-n, control voltages Vg1-Vgn are applied, and a terminal (Vn) 11 of the MOS capacitor (Cf) 5, the terminal being on the side of a well, receives a control voltage. In the multi-terminal MOS varactor with the arrangement above, it is possible to progressively change the valid electrostatic capacity C of the other terminal (Vgj) 9-j of an arbitrary capacitor (Cj) 6-j, by changing the control voltage. Since electrostatic capacity can be progressively changed in this MOS varactor, adopting this MOS varactor to an oscillator enables to control a frequency and sensitivity of the oscillator.

Abstract: A method for forming a back-side contact for a vertical trench device includes grinding a back-side of a semiconductor substrate, milling a trench in the back-side of the semiconductor substrate, wherein a vertical trench fill is exposed, and depositing a conductive material, wherein the conductive material shorts the vertical trench fill to a buried plate. Grinding the back-side of the semiconductor substrate further includes grinding a dimple beneath a portion of the vertical trench device, wherein the trench is milled in the bottom portion of the dimple.

Abstract: A semiconductor component has a cavity formed in a monocrystalline silicon substrate. The wall of the cavity is covered by a cover layer, at least in an upper collar region, and a covering layer is then applied to the surface of the silicon substrate using a selective epitaxial growth method. The cavity is thereby covered in the process. The method is physically simple and can be carried out cost-effectively. In particular, the described method can be used in order to cover a trench prior to high-temperature processes during the production of a DRAM memory, and to open the trench once again after the high-temperature processes, in order to provide a trench capacitor.

Abstract: A method and structure for high capacitance memory cells is provided. The method includes forming a trench capacitor in a semiconductor substrate. A self-structured mask is formed on the interior surface of the trench. The interior surface of the trench is etched to form an array of silicon pillars. The self-structured mask is removed. Then an insulator layer is formed on the array of silicon pillars. A polycrystalline semiconductor plate extends outwardly from the insulator layer in the trench.

Abstract: The disclosure describes a stacked capacitor and a method of forming the same. The method prevents a storage node of the stacked capacitor from crumbling due to lack of support, thereby improving the reliability of semiconductor devices that incorporate stacked capacitors. The disclosure also describes a stacked capacitor with a greater capacitance than a stacked capacitor in accordance with the conventional art.

Abstract: A thin film capacitor comprising an insulating substrate, a capacitor structure located on the substrate, the capacitor structure having a dielectric layer sandwiched between a lower electrode layer and an upper electrode layer, and conductor members respectively connected to the lower electrode layer and the upper electrode layer, wherein at least the dielectric layer has a side face having a sufficient slope for preventing the short circuit of the upper electrode layer with the lower electrode layer through the conductor member. A method of manufacturing such a thin film capacitor is also disclosed.

Abstract: The capacitor comprises an lower electrode 22, a dielectric film 30 formed on the lower electrode 22, a floating electrode 20 formed on the dielectric film 30, a dielectric film 50 formed on the floating electrode 40 and having a film orientation different from that of the dielectric film 30, and an upper electrode 80 formed on the dielectric film 50, whereby various characteristics depending on film orientations of the dielectric films can be simultaneously improved.

Abstract: A semiconductor device includes a semiconductor substrate having a first surface, a pair of active areas formed in the first surface, a deposited oxide layer proximate the active areas, and a gate over the first surface between the pair of active areas.

Abstract: A flash memory with virtual ground scheme. The memory includes a first type substrate, second type doped regions, a stacked gate structure, a first type ion-implanted region, and switches. The second type doped regions are formed in the first type substrate. The stacked gate structure is formed on the surface of the first type substrate and between the second type doped regions. The first type ion-implanted region is formed on only one side of the second type doped region and the first type substrate. The switches are coupled to the second type doped regions respectively for selective provision of a predetermined voltage value and a ground level to the second type doped regions.

Abstract: a new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying said semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. An interpoly oxide layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly oxide layer. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions for planned Flash EEPROM memory cells in the semiconductor substrate where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions.

Abstract: A non-volatile memory cell that includes a semiconductor substrate, a well region implanted with a first-type dopant formed in the semiconductor substrate, a first doped region implanted with a second-type dopant formed in the semiconductor substrate, a second doped region, formed spaced-apart from the first doped region, implanted with a second-type dopant formed in the semiconductor substrate, the second doped region further including a third region implanted with the first-type dopant, a first dielectric layer disposed over the semiconductor substrate, a floating gate disposed over the first dielectric layer and extending over the well region and a portion of the second doped region, a second dielectric layer disposed over the floating gate, and a control gate disposed over the first dielectric layer and the second dielectric layer.

Abstract: Embodiments in accordance with the present invention provide for forming floating gate transistor structures as well as the structures so formed. An exemplary method provides a substrate encompassing semiconductive material. A first layer is formed over the semiconductive material. At least one pair of spaced shallow trench isolation (STI) structures are formed extending through the first layer and into the semiconductive material, and at least a portion of the first layer between the spaced STI structures is removed effective to form a recess there between. The recess is at least partially filled by forming a conductive floating gate material therein and a control gate is formed operatively over the conductive floating gate material to form the floating gate transistor.

Abstract: Embodiments in accordance with the present invention provide for forming floating gate transistor structures as well as the structures so formed. An exemplary method provides a substrate encompassing semiconductive material. A first layer is formed over the semiconductive material. At least one pair of spaced shallow trench isolation (STI) structures are formed extending through the first layer and into the semiconductive material, and at least a portion of the first layer between the spaced STI structures is removed effective to form a recess there between. The recess is at least partially filled by forming a conductive floating gate material therein and a control gate is formed operatively over the conductive floating gate material to form the floating gate transistor.

Abstract: An EEPROM (100) comprises a source region (122), a drain region (120); and a polysilicon layer (110). The polysilicon layer (110) comprises a floating gate comprising at least one polysilicon finger (112A-112E) operatively coupling the source region (122) and drain region (120) and a control gate comprising at least one of the polysilicon fingers (112A-112E) capacitively coupled to the floating gate. The EEPROM (100) has a substantially reduce area compared to prior art EEPROM since an n-well region is eliminated.

Abstract: a new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying said semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. An interpoly oxide layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly oxide layer. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions for planned Flash EEPROM memory cells in the semiconductor substrate where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions.