Patents Issued in July 24, 2003
  • Publication number: 20030137007
    Abstract: A fabrication process of a flash memory device includes microwave excitation of high-density plasma in a mixed gas of Kr and an oxidizing gas or a nitriding gas. The resultant atomic state oxygen O* or hydrogen nitride radicals NH* are used for nitridation or oxidation of a polysilicon electrode surface. It is also disclosed the method of forming an oxide film and a nitride film on a polysilicon film according to such a plasma processing.
    Type: Application
    Filed: February 7, 2003
    Publication date: July 24, 2003
    Inventors: Tadahiro Ohmi, Shigetoshi Sugawa
  • Publication number: 20030137008
    Abstract: A readout gate electrode is selectively formed on a silicon substrate. An N-type drain region is formed at one end of the readout gate electrode, and an N-type signal storage region is formed at the other end thereof. A P+-type surface shield region is selectively epitaxial-grown on the signal storage region, and a silicide block layer is formed on the surface shield region to cover at least part of the signal storage region. A Ti silicide film is selective epitaxial-grown on the drain region.
    Type: Application
    Filed: January 10, 2003
    Publication date: July 24, 2003
    Inventors: Hidetoshi Nozaki, Ikuko Inoue, Hirofumi Yamashita
  • Publication number: 20030137009
    Abstract: A protection structure against electrostatic discharges for a semiconductor electronic devicethat is integrated inside a well is disclosed, wherein the well is formed on a SOI substrateand isolated dielectrically by a buried oxide layer and an isolation structure, which isolation structure includes in turn at least a dielectric trench filled with a filler material. Advantageously, the protection structure is formed at the isolation structure.
    Type: Application
    Filed: October 8, 2002
    Publication date: July 24, 2003
    Applicant: STMICROELECTRONICS S.R.L.
    Inventor: Salvatore Leonardi
  • Publication number: 20030137010
    Abstract: A semiconductor configuration for current control has an n-type first semiconductor region with a first surface, a p-type covered island region, within the first semiconductor region, with a second surface, an n-type contact region arranged on the second surface within the island region and a lateral channel region, formed between the first and second surface as part of the first semiconductor region. The channel is part of a current path from or to the contact region. The current within the lateral channel region may be influenced by at least one depletion zone. A lateral edge of the lateral channel region extends as far as the contact region.
    Type: Application
    Filed: January 27, 2003
    Publication date: July 24, 2003
    Inventors: Peter Friedrichs, Heinz Mitlehner, Reinhold Schorner
  • Publication number: 20030137011
    Abstract: An isolating insulation film (1) and a P type active region (2) defined by the isolating insulation film (1) are formed on a semiconductor substrate. Then, an access transistor gate electrode (3), driver transistor gate electrodes (4a, 4b), and a dummy gate electrode (20) are formed. The dummy gate electrode (20) is formed to cover part of the active region (2) within a region (8) into which an N type dopant is to be implanted to form N+ source/drain regions (9). As a result, the N+ source/drain regions (9) are not formed under the dummy gate electrode (20), and the N+ source/drain regions (9) are reduced in width. This reduces the conductance of access transistors, that is, improves a conductance ratio between the driver and access transistors.
    Type: Application
    Filed: July 22, 2002
    Publication date: July 24, 2003
    Applicant: MITSUBISHI DENKI KABUSHIKI KAISHA
    Inventor: Yasuichi Masuda
  • Publication number: 20030137012
    Abstract: A higher-performance short channel MOS transistor with enhanced resistance to soft errors caused by exposure to high-energy rays is realized. At the time of forming a deep source/drain diffusion layer region at high density, an intermediate region of a density higher than that of impurity of a semiconductor substrate is formed between the source/drain diffusion layer and the semiconductor substrate of a conduction type opposite to that of the source/drain diffusion layer. The intermediate region is formed with a diffusion window for forming the source/drain, an intermediate layer of uniform concentration and uniform width can be realized at low cost.
    Type: Application
    Filed: November 26, 2002
    Publication date: July 24, 2003
    Inventors: Ken Yamaguchi, Yoshiaki Takemura, Kenichi Osada, Masatada Horiuchi, Takashi Uchino
  • Publication number: 20030137013
    Abstract: A device isolation structure and method for a semiconductor device according to the present invention includes forming first and second trenches by etching predetermined regions of a semiconductor substrate, forming a buried insulating film in the trenches, filling in the trenches by depositing single crystal silicon film on the buried insulating film by a silicon epitaxy method, and forming a field insulating film on portions of the semiconductor substrate between the first and second trenches. The field oxide film isolating the single crystal silicon layers fills the adjacent trenches, thus isolating semiconductor devices, such as a high voltage device and a low voltage device, to be fabricated in the single crystal silicon layers.
    Type: Application
    Filed: February 3, 2003
    Publication date: July 24, 2003
    Applicant: Hyundai Electronics Industries Co., Ltd.
    Inventor: Jong-Hak Back
  • Publication number: 20030137014
    Abstract: A capacitive element C1 having a small leakage current is formed by utilizing a gate oxide film 9B thicker than that of a MISFET of a logic section incorporated in a CMOS gate array, without increasing the number of steps of manufacturing the CMOS gate array. The capacitive element C1 has a gate electrode 10E. A part of the gate electrode 10E is made of a polycrystalline silicon film. The polycrystalline silicon film is doped with n-type impurities, so that the capacitive element may reliably operate even at a low power supply voltage.
    Type: Application
    Filed: February 5, 2003
    Publication date: July 24, 2003
    Inventors: Kazuhisa Suzuki, Toshiro Takahashi, Yasunobu Yanagisawa, Yusuke Nonaka
  • Publication number: 20030137015
    Abstract: An IGBT has striped cell with source stripes 2a, 2b continuous or segmented along the length of the base stripe 3. The opposite stripes are periodically connected together by the N+ contact regions 20 to provide channel resistance along the width of the source stripes 2a, 2b. For continuous stripes the resistance between two sequential contact areas 20a, 20b is greatest in the middle and current concentrates near the source contact regions 20. The wider the spacing between the contacts 20, the larger the resistive drop to the midpoint between two N+ contacts 20.
    Type: Application
    Filed: January 23, 2002
    Publication date: July 24, 2003
    Inventors: Joseph A. Yedinak, Dwayne S. Reichl, Jack E. Wojslawowicz, Bernard J. Czeck, Robert D. Baran, Douglas Lange
  • Publication number: 20030137016
    Abstract: A lateral power metal-oxide-semiconductor field effect transistor (MOSFET) having a gate structure in which the insulated gate is coupled to the gate electrode through contacts at a plurality of locations. The source electrode includes first and second segments. The first segment is interposed between the drain electrode and the gate electrode and acts as a field plate.
    Type: Application
    Filed: January 10, 2003
    Publication date: July 24, 2003
    Applicant: Power Integrations, Inc.
    Inventors: Donald Ray Disney, Wayne Bryan Grabowski
  • Publication number: 20030137017
    Abstract: A semiconductor integrated circuit device wherein plural field effect transistors having different threshold values are integrated on one chip by forming plural gate electrodes of silicon-germanium mixed crystals having different germanium contents. By varying the germanium content of the gate electrode material, a work function with respect to the channel region can be varied, so a semiconductor integrated circuit device wherein plural field effect transistors having different threshold voltage values are integrated on one chip can be manufactured.
    Type: Application
    Filed: February 4, 2003
    Publication date: July 24, 2003
    Inventors: Dai Hisamoto, Tsuyoshi Kachi
  • Publication number: 20030137018
    Abstract: A compound semiconductor structure is provided, which includes a GaAs-based supporting semiconductor structure having a surface on which a dielectric material is to be formed. A first layer of gallium oxide is located on the surface of the supporting semiconductor structure to form an interface therewith. A second layer of a Ga—Gd oxide is disposed on the first layer. The GaAs-based supporting semiconductor structure may be a GaAs-based heterostructure such as an at least partially completed semiconductor device (e.g., a metal-oxide field effect transistor, a heterojunction bipolar transistor, or a semiconductor laser). In this manner a dielectric layer structure is provided which has both a low defect density at the oxide-GaAs interface and a low oxide leakage current density because the dielectric structure is formed from a layer of Ga2O3 followed by a layer of Ga—Gd-oxide.
    Type: Application
    Filed: January 18, 2002
    Publication date: July 24, 2003
    Inventors: Matthias Passlack, Nicholas William Medendorp
  • Publication number: 20030137019
    Abstract: Lanthanum oxide-based gate dielectrics are provided for integrated circuit field effect transistors. The gate dielectrics may include lanthanum oxide, preferably amorphous lanthanum oxide and/or an alloy of lanthanum oxide and silicon oxide, such as lanthanum silicate (La2SiO5). Lanthanum oxide-based gate dielectrics may be fabricated by evaporating lanthanum on a silicon surface of an integrated circuit substrate. The lanthanum may be evaporated in the presence of oxygen. Lanthanum and silicon may be co-evaporated. An anneal then may be performed. Lanthanum oxide-based dielectrics also may be used for integrated circuit capacitors.
    Type: Application
    Filed: January 13, 2003
    Publication date: July 24, 2003
    Inventors: Jon-Paul Maria, Angus Ian Kingon
  • Publication number: 20030137020
    Abstract: The present invention discloses a tunable optical device. The tunable optical device includes a tuning cavity having a tuning means provided for alternately bonding to at least two different tunable optical cells each comprising a tuning membrane wherein the tuning cavity disposed near the tuning membrane for moving the tuning membrane for tuning one of the at least two tunable optical cells bonded thereon. In a preferred embodiment, the tuning cavity further includes a first electrode disposed on the tuning membrane and a second electrode disposed on a substrate supporting the tuning cavity for applying a voltage to move the tuning membrane. In a preferred embodiment, the optical device further includes an optical device control circuit connected to the tuning means for controlling and moving the tuning membrane.
    Type: Application
    Filed: June 7, 2002
    Publication date: July 24, 2003
    Applicant: INTPAX, Inc.
    Inventors: Naiqian Han, Jidong Hou, Xiaoping Zhang, Liji Huang, Gaofeng Wang
  • Publication number: 20030137021
    Abstract: The present invention provides an integrated electronic microphone formed as part of a semiconductor device, and a manufacturing method therefor. The microphone is formed with a sensing electrode as part of a sensing membrane, and the sensing electrode is connected to the gate of a sensing transistor to provide an output. The microphone may be operated in constant bias or constant charge mode.
    Type: Application
    Filed: January 18, 2002
    Publication date: July 24, 2003
    Inventors: Man Wong, Yitshak Zohar
  • Publication number: 20030137022
    Abstract: An optoelectronic submount for providing optical connection and electrical connection to a vertically communicating optical device, such as a vertical cavity surface-emitting laser. The submount has a trench for holding the optoelectronic device on-edge, and electrical connection pits adjoining the trench. A metallization layer is disposed in the electrical connection pits. The electrical connection pits are aligned with the trench and optoelectronic device so that compact pads on the optoelectronic device can be soldered to the metallization layer. A groove can be provided in the submount for holding an optical fiber in alignment with an active area of the optoelectronic device.
    Type: Application
    Filed: January 31, 2002
    Publication date: July 24, 2003
    Inventors: Mindaugas F. Dautartas, Dan A. Steinberg
  • Publication number: 20030137023
    Abstract: An optoelectronic device has at least one quantum dot structure in a semiconductor material and at least two monolithically integrated components. At least two components are functionally coupled to one another in the semiconductor material via at least one quantum dot structure. This results in a very compact optoelectronic device.
    Type: Application
    Filed: January 9, 2003
    Publication date: July 24, 2003
    Inventor: Bernhard Stegmuller
  • Publication number: 20030137024
    Abstract: To provide a mask able to prevent a drop in pattern position accuracy due to the influence of internal stress of a membrane and able to align patterns including complementary divided patterns precisely, a method of producing the same, and a method of producing a semiconductor device. A stencil mask having lattice-shaped struts formed by etching a silicon wafer on four regions of a membrane wherein the lattices are offset from each other in the four regions and all of the struts are connected to other struts or the silicon wafer around the membrane (frame), a method of producing a stencil mask, and a method of producing a semiconductor device.
    Type: Application
    Filed: February 3, 2003
    Publication date: July 24, 2003
    Inventors: Shigeru Moriya, Shinji Omori
  • Publication number: 20030137025
    Abstract: A multi-layered gate for use in a CMOS or CCD imager formed with a second gate at least partially overlapping it. The multi-layered gate is a complete gate stack having an insulating layer, a conductive layer, an optional silicide layer, and a second insulating layer, and has a second gate formed adjacent to it which has a second conductive layer that extends at least partially over the surface of the multi-layered gate. The multi-layered gate has improved insulation, thereby resulting in fewer shorts between the conductive layers of the two gates. Also disclosed are processes for forming the multi-layered gate and the overlapping gate.
    Type: Application
    Filed: January 14, 2003
    Publication date: July 24, 2003
    Inventor: Howard E. Rhodes
  • Publication number: 20030137026
    Abstract: Disclosed is an avalanche photodiode for use in super-high speed optical communication, more particularly, to a structure of an avalanche photodiode device capable of suppressing edge breakdown to increase avalanche gain factor of a light signal and to reduce a noise. The avalanche photodiode includes a wafer characterized in that the guard ring has a depth equal to that of a center part of the active region (diffused region), an edge of the active region is shallower than the center part, and the guard ring is electrically isolated from the active region. Therefore, a gain-bandwidth characteristic may be increased, and also the higher receiver sensitivity may be achieved.
    Type: Application
    Filed: April 29, 2002
    Publication date: July 24, 2003
    Inventor: Chan Yong Park
  • Publication number: 20030137027
    Abstract: A body (1) consisting of a doped semiconductor material with a pn junction (10) and an area (2) of reduced mean free path length (&lgr;r) for free charge carriers is disclosed. Said area (2) has sections (21, 22) which succeed each other in at least one specified direction (x, y, z) and between which there is at least one region (23), containing a mean free path length (&lgr;0) for the free charge carriers that is larger in relation to the reduced mean free path length (&lgr;r).
    Type: Application
    Filed: February 28, 2003
    Publication date: July 24, 2003
    Inventors: Veli Kartal, Hans-Joachim Schulze
  • Publication number: 20030137028
    Abstract: A semiconductor integrated circuit device includes a cell transistor, a bit line, an intracell local interconnection and a magnetoresistive element. The intracell local interconnection provided above the bit line and electrically connected to one of source and drain regions of the cell transistor. The magnetoresistive element provided on the bit line and electrically connected to the bit line and the intracell local interconnection.
    Type: Application
    Filed: July 22, 2002
    Publication date: July 24, 2003
    Inventors: Keiji Hosotani, Yoshiaki Asao, Yoshiaki Saito, Minoru Amono, Shigeki Takahashi, Tatsuya Kishi, Yoshihisa Iwata
  • Publication number: 20030137029
    Abstract: A vertical bipolar transistor having low breakdown voltage, low ESD clamping voltage and high beta is fabricated in a semiconductor 301 of a first conductivity type, which has a buried layer 360 of the opposite conductivity type with sharp junctions, suitable as collector. This layer extends laterally to deep wells 371 of the opposite conductivity type, thus isolating the subsurface band 301a of the semiconductor of the first conductivity type. This band is suitable as the base and has a width 301c controlled by the proximity of the buried layer junction 360a. The emitter 310 is supplied by a surface region of the opposite conductivity type.
    Type: Application
    Filed: January 18, 2002
    Publication date: July 24, 2003
    Inventors: Craig T. Salling, Zhiqiang Wu
  • Publication number: 20030137030
    Abstract: A method for forming a die on a wafer is provided. The method includes forming on a wafer a die having an active portion that includes integrated circuitry. The method further includes forming at least one input bond pad on the active portion and at least one test pad on the die. A conductive path is formed between the input bond pad and the test pad. A portion of the conductive path is formed on the die outside of the active portion of the die.
    Type: Application
    Filed: January 22, 2002
    Publication date: July 24, 2003
    Inventor: Aron T. Lunde
  • Publication number: 20030137031
    Abstract: A semiconductor device has a semiconductor die with a rhombic shape and including a substrate with a hexagonal crystal structure, first and second semiconductor films formed on the substrate, and first and second metal contacts formed respectively on the semiconductor films. The hexagonal crystal structure has six equilateral sides. The semiconductor die has two parallel first side edges and two parallel second side edges, which extend in directions that are substantially parallel to respective ones of the six equilateral sides of the hexagonal crystal structure.
    Type: Application
    Filed: January 23, 2002
    Publication date: July 24, 2003
    Inventors: Tai-Fa Young, Jiun-Feng Liou
  • Publication number: 20030137032
    Abstract: A leadframe for use with integrated circuit chips comprising a base metal, usually copper or a copper alloy, having a modified surface adapted to provide bondability and solderability and adhesion to polymeric compounds. The modified surface comprises a layer created by converting a percentage of base metal atoms into substitutional metal complexes, usually hydrated chromates. A thin layer of plated copper may be employed for controlling uniformity and consistency of the replacement reaction.
    Type: Application
    Filed: November 20, 2002
    Publication date: July 24, 2003
    Inventor: Donald C. Abbott
  • Publication number: 20030137033
    Abstract: A semiconductor package according to the present invention includes a die attachment area for receiving a die attachment material and a stitch bond area for receiving a wire lead from a die. The stitch bond area is adjacent to said die attachment area on the substrate. Moreover, a stud bump is formed on the substrate for preventing the die attachment material from contacting the stitch bond area when a die is attached to the die attachment area. A method for manufacturing a semiconductor package according to the present invention also is disclosed.
    Type: Application
    Filed: January 15, 2003
    Publication date: July 24, 2003
    Inventors: Akira Karashima, Margaret Simmons-Matthews, Sohichi Kadoguchi
  • Publication number: 20030137034
    Abstract: Disclosed herein is a semiconductor device comprising a substrate having a first area on which a semiconductor element is mounted, a second area which surrounds the first area, and a third area located in a central portion of the first area; wirings extending from the second area to the third area and formed over the substrate; an insulting film which is formed in the first and second areas so as to expose the third area and covers the substrate and the wirings; and the semiconductor element which is electrically connected to the wirings within the third area and which has a size equal to the first area and is mounted on the first area so as to be spaced a predetermined interval from the insulating film.
    Type: Application
    Filed: January 16, 2003
    Publication date: July 24, 2003
    Inventor: Kaname Kobayashi
  • Publication number: 20030137035
    Abstract: A substrate and a fabrication method thereof are proposed, with at least a check point being formed on the substrate. Prior to wire bonding and/or molding processes, cleanness of the substrate (cleaned by plasma) is determined according to color variation of the check point, so as to allow only cleaned and contamination-free substrates to be subsequently formed with bonding wires and encapsulants thereon. Thereby, qualities of wire-bonded electrical connection and encapsulant adhesion for the substrate can be assured, which helps prevent the occurrence of delamination between the encapsulant and the substrate. Moreover, the check point formed on the substrate is made during general substrate fabrication by using current equipment and technique, and in a manner as not to interfere with trace routability on the substrate; thereby, costs and complexity of substrate fabrication would not undesirably increased.
    Type: Application
    Filed: April 4, 2002
    Publication date: July 24, 2003
    Applicant: Siliconware Precision Industries Co., Ltd.
    Inventors: Chien-Ping Huang, Han-Ping Pu, Chih-Chin Liao
  • Publication number: 20030137036
    Abstract: Disclosed are semiconductor packages and methods incorporating the use of vias in layers of leaded and nonleaded multilayer packages. The vias provide fluid communication between layers such that bonding material flows among layers for the formation of a 3D bond. As disclosed, the layers may comprise leads, dice, bond pads, or other substantially planar semiconductor package surfaces.
    Type: Application
    Filed: August 7, 2002
    Publication date: July 24, 2003
    Inventor: Terence Quintin Collier
  • Publication number: 20030137037
    Abstract: A plurality of semiconductor chips is each arranged over a first conductor. Each of semiconductor chips has a first main electrode, a second main electrode and a control electrode. A second conductor is electrically connected to the second main electrode and has columns each having an upper surface arranged over each of the semiconductor chips and equal to the number of the semiconductor chips. A circuit board has openings penetrated by the columns and equal to the number of the semiconductor chips and has a first insulating film, a third conductive film arranged on a back surface of the first insulating film and electrically connected to the second conductor, and a fourth conductive film arranged on a surface of the first insulating film and electrically connected to the control electrode.
    Type: Application
    Filed: January 22, 2003
    Publication date: July 24, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ichiro Omura, Tomokazu Domon, Eitaro Miyake
  • Publication number: 20030137038
    Abstract: An apparatus and method for dissipating static electrical charge following a manufacturing operation is disclosed. A semiconductor package is provided with ground pads that are located to assure electrical contact with ejection pins used to translate the package from one position to another. Static electricity builds up on the semiconductor package. The ejection pins provide the pathway for dissipating static electrical charge out of the semiconductor package.
    Type: Application
    Filed: February 25, 2003
    Publication date: July 24, 2003
    Inventors: Arthur K. Lin, Robert A. Anderson, Kuljeet Singh
  • Publication number: 20030137039
    Abstract: A basic portion layer 21 of a substrate electrode 12a connected to a projecting electrode 13 electrically and mechanically on a substrate member of ceramics. The substrate member on which the basic portion layer 21 is formed is subjected to sintering. A surface of the basic portion layer 21 in the sintered substrate member is polished. On the polished basic portion layer 21, the plating layers 22, 23, are formed, so that surface roughness of the substrate electrode 12a may be, for example, not larger than 0.1 &mgr;mRMS. Accordingly, junction strength of an integrated circuit element mounted on a packaging substrate by a flip-chip method can be improved.
    Type: Application
    Filed: November 18, 2002
    Publication date: July 24, 2003
    Applicant: TDK Corporation
    Inventors: Masahiro Nakano, Katsuhiko Gunji, Yasunobu Oikawa, Katsuo Sato
  • Publication number: 20030137040
    Abstract: A co-package semiconductor device including an outer clip in the form of a metal can includes also two semiconductor dies, at least one of which uses the outer clip as an electrical connector. An inner clip is used to dispose one of the dies within the outer clip. The inner clip may be insulated from the outer clip by an insulating layer.
    Type: Application
    Filed: January 18, 2002
    Publication date: July 24, 2003
    Inventor: Martin Standing
  • Publication number: 20030137041
    Abstract: A method and structure for a memory structure that includes a plurality of substrates stacked one on another is disclosed. The invention includes a plurality of connectors connecting the substrates to one another and a plurality of memory chip packages mounted on the substrates. The connectors have a size sufficient to form a gap between the substrates. The gap is larger than a height of the memory chip packages.
    Type: Application
    Filed: January 24, 2002
    Publication date: July 24, 2003
    Applicant: International Business Machines Corporation
    Inventors: Edmund D. Blackshear, William F. Beausoleil, N. James Tomassetti
  • Publication number: 20030137042
    Abstract: A stacked multiple offset chip device is formed of two or more dice of similar dimensions and bond pad arrangement, in which bond pads are located in fields along less than three edges of the active surface of each die. A first die is attached to a substrate and subsequent die or dice are attached in a vertical sequence atop the first die, each in an offset configuration from the next lower die to expose the bond pads thereof for conductive bonding to metallization of the substrate. The multiple chip device permits a plurality of dice to be stacked in a maximum density low profile device. A particularly useful application is the formation of stacked mass storage flash memory package.
    Type: Application
    Filed: January 15, 2003
    Publication date: July 24, 2003
    Inventors: Leonard E. Mess, Jerry M. Brooks, David J. Corisis
  • Publication number: 20030137043
    Abstract: A polybenzoxazine based wafer-level underfill material. The material may be provided to a surface of a semiconductor wafer. The semiconductor wafer may then be sawed into individual chips. The polybenzoxazine based underfill material may be for use between a chip and a package substrate.
    Type: Application
    Filed: January 10, 2003
    Publication date: July 24, 2003
    Inventors: Lejun Wang, Song-Hua Shi, Tian-An Chen
  • Publication number: 20030137044
    Abstract: Two different switches with two different signal input schemes are fabricated by mounting the same semiconductor chip on the same lead pattern. Two of the leads of the lead pattern provides space enough for wire-bonding connection to corresponding electrode pads on the semiconductor chip at both ends of the semiconductor chip. Because each of electrode pads can be connected to the corresponding lead at either end of the semiconductor chip, two sets of bonding wire connection between the leads and the electrode pads provides two different switches with two different signal inputs scheme.
    Type: Application
    Filed: November 15, 2002
    Publication date: July 24, 2003
    Inventors: Tetsuro Asano, Mikito Sakakibara, Hideyuki Inotsume, Haruhiko Sakai, Shigeo Kimura
  • Publication number: 20030137045
    Abstract: A circuit component built-in module includes: a first electrical insulating substrate made of a mixture containing an inorganic filler and a thermosetting resin; a plurality of wiring patterns formed at least on a principal surface of the first electrical insulating substrate; a semiconductor chip incorporated in the first electrical insulating substrate and connected electrically with the wiring patterns; and inner vias electrically connecting the plurality of wiring patterns with one another, the inner vias passing through the first electrical insulating substrate. In the circuit component built-in module, the semiconductor chip has a thickness of not less than 30 &mgr;m and not more than 100 &mgr;m, and has a non-wired surface ground, and the circuit component built-in module has a thickness in a range of not less than 80 &mgr;m and not more than 200 &mgr;m.
    Type: Application
    Filed: January 17, 2003
    Publication date: July 24, 2003
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Yasuhiro Sugaya, Toshiyuki Asahi, Shingo Komatsu, Yoshiyuki Yamamoto, Seiichi Nakatani, Satoru Yuhaku, Kazuo Ohtani
  • Publication number: 20030137046
    Abstract: A semiconductor device includes a multilayer substrate provided with a cavity, a semiconductor chip placed in the cavity, wiring lines provided with lands, a cover formed of a potting material, covering the semiconductor chip and having a protruding part, and chips bonded to the wiring lines with a solder having a low melting point. The protruding part has a height (h1) from the surface of the multilayer substrate greater than the thickness of the wiring layer.
    Type: Application
    Filed: June 13, 2002
    Publication date: July 24, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Shigeki Kageyama
  • Publication number: 20030137047
    Abstract: A cooler for an electronic device of the present invention is provided with a heatsink and a cross flow blower with an electric motor. The heatsink comprises a base and heat exchanging means made as flat disks, fins or flat plates. The base provides thermal contact with the electronic device and the heat exchanging means. The cross flow blower comprises a drum type impeller with an axis of rotation substantially normal to the base. The flat disks substantially perpendicular to the axis of rotation and located inside of the drum type impeller. The fins or flat plates substantially perpendicular to the axis of rotation and located outside of said drum type impeller. The heatsink further comprises heat-spreading means that provide thermal contact between the base and the flat disks and flat plates. The heat-spreading means may be heat-pipes.
    Type: Application
    Filed: November 25, 2002
    Publication date: July 24, 2003
    Inventors: Edward Lopatinsky, Daniel Schaefer, Saveliy Rosenfeld, Lev Fedoseyev
  • Publication number: 20030137048
    Abstract: The present invention stacks integrated circuits into modules that conserve board surface area. In a two-high stack or module devised in accordance with a preferred embodiment of the present invention, a pair of integrated circuits is stacked, with one integrated circuit above the other. The two integrated circuits are connected with a pair of flexible circuit structures. Each of the pair of flexible circuit structures is partially wrapped about a respective opposite lateral edge of the lower integrated circuit of the module. The flex circuit pair connects the upper and lower integrated circuits and provides a thermal and electrical path connection path between the module and an application environment such as a printed wiring board (PWB). The present invention may be employed to advantage in numerous configurations and combinations of integrated circuits in modules provided for high-density memories or high capacity computing.
    Type: Application
    Filed: March 27, 2003
    Publication date: July 24, 2003
    Applicant: Staktek Group, L.P.
    Inventors: James W. Cady, James Wilder, David L. Roper, James Douglas Wehrly, Julian Dowden, Jeff Buchle
  • Publication number: 20030137049
    Abstract: An impurity region is formed on the surface of a semiconductor substrate. An insulating layer is provided on the semiconductor substrate to cover the impurity region. A trench for defining a wiring layer is provided on the surface of the insulating layer. A connection hole is provided in the insulating layer for connecting the trench and the impurity region with each other. A conductive layer made of a high melting point metal or a compound thereof is embedded in the connection hole. A copper wire is formed in the trench to be connected to the conductive layer. According to the present invention, a semiconductor device improved to be capable of implementing an excellent wiring circuit and providing a highly integrated semiconductor circuit is obtained.
    Type: Application
    Filed: August 1, 2002
    Publication date: July 24, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Sumio Yamaguchi
  • Publication number: 20030137050
    Abstract: A method, apparatus, system, and machine-readable medium for an interconnect structure in a semiconductor device and its method of formation is disclosed. Embodiments comprise a carbon-doped and silicon-doped interconnect having a concentration of silicon to avoid to forming a copper silicide layer between an interconnect and a passivation layer. Some embodiments provide unexpected results in electromigration reliability in regards to activation energy and/or mean time to failure.
    Type: Application
    Filed: November 12, 2002
    Publication date: July 24, 2003
    Inventors: Stephen T. Chambers, Valery M. Dubin, Andrew W. Ott, Christine S. Hau-Riege
  • Publication number: 20030137051
    Abstract: An anti-reflection coating 5 used at time of forming a first contact hole 6 is interposed between a first insulating layer 4 and a second insulating layer 80, and the anti-reflection coating 5 is served as an etching prevention film for the first insulating layer 4 at time of forming a second contact hole 9 in the second insulating layer 80, whereby an electrical short between a conductive plug and an electrode layer is prevented; an electrical connection between upper and lower conductive plugs is stabilized; and a semiconductor device having a highly reliable contact structure, in which multi-layer conductive plugs are included, is obtainable.
    Type: Application
    Filed: May 18, 2000
    Publication date: July 24, 2003
    Inventor: Kenji Kawai
  • Publication number: 20030137052
    Abstract: A method is provided for manufacturing a semiconductor device having a multilayer wiring structure in which at least one insulating film is formed with a set of conducting portions which are electrically connected to each other to have a surface area of no less than 500 &mgr;m2 and which include a wiring having a width of no more than l.0 &mgr;m. The method includes a polishing step (501) for flattening the conducting portions together with the insulating film by chemical mechanical polishing, a chemical cleaning step (502) for cleaning the flattened surface of the insulating film with a cleaning liquid, and a rising step (503) for removing the cleaning liquid using a rinsing liquid. The rinsing step is performed using water with a dissolved oxygen concentration decreased to no more than 6 ppm by weight as the rinsing liquid.
    Type: Application
    Filed: December 23, 2002
    Publication date: July 24, 2003
    Applicant: FUJITSU LIMITED
    Inventors: Hiroshi Horiuchi, Tamotsu Yamamoto, Yukio Takigawa, Shigeru Suzuki, Nobuaki Santo, Motoshu Miyajima
  • Publication number: 20030137053
    Abstract: A wiring structure including a transmission line structure capable of simplifying a manufacturing process is obtained. This wiring structure comprises a first trench formed on a first insulator film provided on a substrate, a first wire formed in the extensional direction of the first trench along at least part of the inner surface of the first trench and a second wire formed to be opposed to the first wire through a second insulator film for forming a transmission line for transmitting signals with the first wire. The first wire, the second insulator film and the second wire are embedded in the first trench. This wiring structure is manufactured through a single lithography step, a single etching step and a single resist removing step for forming the first trench and a single CMP step, whereby the manufacturing process is simplified.
    Type: Application
    Filed: January 8, 2003
    Publication date: July 24, 2003
    Applicant: SANYO ELECTRIC CO., LTD.
    Inventor: Yoshio Okayama
  • Publication number: 20030137054
    Abstract: A semiconductor device includes an upper wiring layer, a lower wiring layer, an electrically insulating layer sandwiched between the upper and lower wiring layers, a tungsten plug formed in a through-hole formed through the electrically insulating layer, for electrically connecting the upper and lower wiring layers to each other, a titanium film covering an inner surface of the through-hole and a surface of the electrically insulating layer therewith, a first titanium nitride film entirely covering the titanium film therewith, and a second titanium nitride film covering the first titanium nitride film and a surface of the tungsten plug therewith.
    Type: Application
    Filed: January 17, 2003
    Publication date: July 24, 2003
    Applicant: Elpida Memory, Inc.
    Inventor: Yoshitaka Ishihara
  • Publication number: 20030137055
    Abstract: The invention includes a dual-damascene semiconductor processing method. A semiconductor substrate is provided, and the substrate includes a conductive structure and an insulative layer over the conductive structure. A via is etched through the insulative layer and into the conductive structure, and a resist is formed within the via. A material is formed over the resist and substrate. A portion of the material in contact with the resist is hardened, and another portion of the material that does not contact the resist is not hardened. The portion of the material which is not hardened is removed, and a slot is etched into the insulative layer.
    Type: Application
    Filed: August 27, 2002
    Publication date: July 24, 2003
    Inventor: Jigish D. Trivedi
  • Publication number: 20030137056
    Abstract: A circuit substrate comprises a glass substrate 16, through-holes 18 formed through the glass substrate 16 and via electrodes 20 buried in the through-holes 18. An opening width of the through-holes 18 is minimum inside the glass substrate and is increased toward both surfaces of the glass substrate 16. Accordingly, the detachment of the via electrodes 20 can be prevented without increasing the surface roughness of the inside walls of the through holes, and stresses generated in the core substrate can be mitigated.
    Type: Application
    Filed: January 6, 2003
    Publication date: July 24, 2003
    Applicant: Fujitsu Limited
    Inventors: Osamu Taniguchi, Yasuo Yamagishi, Koji Omote