Abstract: The present invention provides a composition of matter for introducing an exogenous nucleic acid molecule into a target cell, comprising a liposome, a ligand polymeric scaffold, wherein the ligand can bind to a cell surface receptor or molecule. The invention also provides methods for introducing an exogenous nucleic acid molecule into a target cell using the composition of matter.

Abstract: The present invention provides an improved method for gene delivery in eukaryotic cells by electroporation, preferably in human hematopoietic cells, particular dendritic cells. The method of the invention is superior to lipofection and passive pulsing of mRNA and to electroporation of plasmid cDNA for gene delivery, including tumor antigen loading of dendritic cells.

Abstract: The present invention provides Inter alia, a method for the production of cotton somatic embryos comprising (a) isolating a totipotent stomatal cell-containing epidermal explant from leaf material excised from a cotton plant; and (b) culturing said explant in a basal medium which comprises an embryogenic callus-inducing quantity of an auxin and a cytokinin under an embryogenic callus inducing intensity of light until embryogenic callus is formed; and (c) sub-culturing said embryogenic callus onto a somatic embryo differentiation media to produce said somatic embryos. Plants may be regenerated from the somatic embryos and in a particular embodiment of the invention said totipotent stomatal cell is transformed, prior to the inducement of embryogenic callus, with a polynucleotide that provides for a desired agronomic trait.

Abstract: Provided herein are heretofore-unknown strains of Streptomyces that are unable to express undecylprodrodigiosin, actinorhodin, or both, as well as novel vectors that permit the creation of chromosomal mutations in Streptomyces and do not insert selection markers in the genome of Streptomyces, along with vectors and methods for transferring large segments of DNA into the Streptomyces and Psuedomonas chromosome by conjugation.

Abstract: A wearable periodic self-calibrating body analyte monitoring system based on the principles of microdialysis for measurement of a body analyte is disclosed. In a preferred embodiment, the system is designed to measure glucose, and can be held on the body with a skin adhesive for comfort. The system may be combined with an insulin delivery system to create an artificial pancreas.

Abstract: A method and apparatus for determining changes in a supply system, designed to supply repeated pulses of a vapor phase reactant to a reaction chamber is disclosed. One embodiment involves providing the reactant source, and a gas conduit to connect the reactant source to the reaction chamber, a valve positioned in communication with the reactant source such that switching of the valve induces vapor phase reactant pulses from the reactant source to the reaction chamber and a sensor positioned in communication with the reactant source and configured to provide a signal indicative of a characteristic parameter of the reactant pulse as a function of time. A curve is derived from the signal and the shape of the curve is monitored to determine changes in the curve shape over time during subsequent pulses.

Abstract: The present invention refers to a milk sampling apparatus for use with an automated milking system, said apparatus comprising a cassette (7) wherein milk sample collecting elements (9) are placed, and at least one filling member (27) capable of being placed above a selected one of said milk sample collecting elements (9) by means of a positioning system, and capable of bringing a milk sample, representatively taken from milk yielded during the milking of an animal by means of said automated milking system, into said selected one of said milk sample collecting elements (9). According to the invention the milk sampling apparatus comprises agitating means, preferably a shaking table (5), capable of agitating said milk sample.

Abstract: The present invention refers to a milk sampling apparatus and method for use with an automated milking system. The apparatus comprises a cassette (7) wherein milk sample collecting elements (9) are placed, and at least one filling member (27) capable of being placed above a selected one of said milk sample collecting elements (9) by means of a positioning system, and capable of bringing a milk sample, representatively taken from milk yielded during the milking of an animal by means of said automated milking system, into said selected one of said milk sample collecting elements (9).

Abstract: A peptide compound for measuring sulfur compound and ammonia and measurement method and device using the compound. The method comprises contacting an analyte with a sensory device coated with the peptide compound to produce a signal, processing the signal to produce a result, and comparing the result with a database to define the presence of the sulfur compound and ammonia in the analyte.

Abstract: A method of using a chemical array reader, chemical array readers, and computer program products for use with a chemical array reader. The chemical array reader may include a holder to mount an array and hold the array at a reading position. A light system illuminates a mounted array when at a reading position. A detection system having a focal plane, to detect light from different regions across the array emitted in response to the illumination, when at the reading position, and which generates a resulting signal for each of the regions across the array. An autofocus system which detects and reduces offset between the different regions of an array at the reading position and a determined position of the focal plane.

Abstract: Methods and apparatus for evaluating the quality of a sample of a product, an ingredient, an environment or process by measuring multiple parameters thereof, including light emitted from a reacting sample containing ATP, ADP, alkaline phosphatase or other parameters such as pH, temperature, conductivity, reduction potential, dissolved gases, specific ions, and microbiological count. The apparatus comprises an integrated sample testing device used to collect a sample, mix reagents, react the sample, and collect it in a measurement chamber. The apparatus also comprises an instrument having a photon detection assembly for use with the sample testing device. The instrument can also comprise one or more sensing probes and a communication port to facilitate data collection, transfer and analysis.

Abstract: The present invention relates to antioxidant analysis for solder plating solutions, by using a complexing solution comprising a molybdenum compound, such as MoO2Cl2, to form a highly colored antioxidant-molybdenum complex, which can be detected and analyzed by UV-Vis spectroscopic, as a basis for concentration determination for the antioxidant.

Abstract: An apparatus and method for pumping and optionally mixing of small quantities of biological fluid wherein the pumping mechanism is segregated from the biological fluid being pumped. The micro-pump pushes the biological fluid by compressing a cartridge housing the blood and reagents with collapsible walls with a roller or ball bearing, synchronized perpendicular plungers, or an acutely-angled member to push the biological fluid by collapsing the walls of the cartridge in the direction of flow.

Abstract: An analytical test device incorporating a dry porous carrier to which a liquid sample, eg. urine, suspected of containing an analyte such as HCG or LH can be applied indirectly, the device also incorporating a labelled specific binding reagent which is freely mobile in the porous carrier when in the moist state, and an unlabelled specific binding reagent which is permanently immobilised in a detection zone on the carrier material, the labelled and unlabelled specific binding reagents being capable of participating in either a sandwich reaction or a competition reaction in the presence of the analyte, in which prior to the application to the device of a liquid sample suspected of containing the analyte, the labelled specific binding reagent is retained in the dry state in a macroporous body, eg.

Abstract: A method, apparatus, and computer program products for fabricating multiple chemical arrays on a substrate, each array having multiple rows of feature locations with arrays of different sets being arranged in a sideways orientation with respect to the rows. The method includes dispensing drops from a drop dispensing head onto the substrate while maintaining a gap between the head and substrate and moving them relative to one another along a path so as to fabricate the arrays. The path for the relative moving includes moving the head in a direction along the rows of a first array set then moving the head in an opposite direction along the rows of a second array set. This pattern is repeated with the second array set of an earlier cycle being the first array set of a later cycle.

Abstract: The present invention relates to methods for detecting chemical moieties that may serve as the core or scaffold of a potential drug that is directed to a target. The invention further relates to a chemical library of drug cores and the use of that library to identify useful drug cores for a particular target protein.

Abstract: The present invention provides: a reagent and a kit for an insoluble carrier particle nephelometric immunoassay which stabilize the agglutination reaction by suppressing the action of blood plasma components that are involved in the agglutination reaction of insoluble carrier particles such as latex and affect the values to be determined, to provide the stable absorbances of the reaction solutions and the accurate determination results; and a method of an insoluble carrier particle nephelometric immunoassay utilizing said reagent or kit.

Abstract: Methods are disclosed for determining, in a sample derived from a human, the functional activity of a component of the human blood coagulation system, which activity can be correlated to conversion of a substrate specific for activated Protein C (APC), by measuring in an assay medium containing the sample and a substrate for APC, the conversion of the substrate by APC and correlating the conversion to the functional activity of the component. When the component is anticoagulant Factor V, at least one of exogenous APC, Protein S or an inhibitor of Protein S activity is added to the medium. When the component is Protein C, APC, or Protein S, exogenous anticoagulant Factor V or an inhibitor of anticoagulant activity of Factor V is added to the medium. Methods are also disclosed for diagnosing a blood coagulation/anticoagulation disorder or for determining a predisposition thereto in a human by determining anticoagulant Factor V activity in an assay medium containing a sample derived from the human.

Abstract: The invention relates to a monoclonal antibody which forms an immunological complex with an epitope of an antigen belonging to normal human tau protein as well as abnormally phosphorylated human tau protein, with said tau protein being liable to be obtained from a brain homogenate, itself isolated from human cerebral cortex. The monoclonal antibodies of the invention can be used to detect tau and abnormally phosphorylated tau in brain extracts and in unconcentrated cerebrospinal fluid.

Abstract: Upon formation of semiconductor micro patterns, an interlayer alignment error occurs due to asymmetry of each alignment mark. Prior to alignment of a mask with a wafer, the asymmetry of each alignment mark is measured according to the principle of a scatterometry, and the alignment is performed in consideration of the result of measurement to execute exposure. Thus, high-accuracy alignment can be carried out without sacrificing throughput, and the performance of a semiconductor device is improved. Further, manufacturing yields can be enhanced and a reduction in cost can be realized.

Abstract: An interconnect structure including a substrate, an interconnect device formed on the substrate, and a test device formed on the substrate.

Abstract: A microelectronic device is provided including an integrated circuit mounted to a substrate. A break through multiple conductive layers of the substrate corresponds to a break in the power planes of the integrated circuit. The breaks in the substrate and in the integrated circuit allow for a rotational burn-in of a first portion and a second portion of the integrated circuit.

Abstract: An interconnect for semiconductor components includes a substrate, and interconnect contacts on the substrate for electrically engaging component contacts on the components. The interconnect contacts include silicon carbide conductive layers, and conductors in electrical communication with the silicon carbide conductive layers. The silicon carbide conductive layers provides a wear resistant surface, and improved heat transfer between the component contacts and the interconnect contacts. The silicon carbide conductive layers can comprise doped silicon carbide, or alternately thermally oxidized silicon carbide. The interconnect can be configured for use with a testing apparatus for testing discrete components such as dice or chip scale packages, or alternately for use with a testing apparatus for testing wafer sized components, such as wafers, panels and boards. In addition, the interconnect can be configured for constructing semiconductor packages and electronic assemblies such as multi chip modules.

Abstract: The method of fabricating a nitride semiconductor device of this invention includes plural steps of respectively growing plural nitride semiconductor layers on a substrate; and between a step of growing one nitride semiconductor layer and a step of growing another nitride semiconductor layer adjacent to the one nitride semiconductor layer among the plural steps, a step of changing a growth ambient pressure from a first growth ambient pressure to a second growth ambient pressure different from the first growth ambient pressure.

Abstract: A flat panel display module includes a transparent substrate, a light emitting section, a sealing cap, a flexible printed circuit board and a semiconductor device. The transparent substrate with a wiring line terminal section is formed on one of surfaces of the transparent substrate in at least one of opposing ends of the transparent substrate. The light emitting section is provided in a display region in a center section on the surface on which the wiring line terminal section of the transparent substrate is formed. The sealing cap is provided for a sealing region to cover the light emitting section such that ends of the sealing cap does not reach the ends of the transparent substrate or the wiring line terminal section of the transparent substrate. The flexible printed circuit board is connected to the wiring line terminal section and extending along the sealing cap of the transparent substrate. The semiconductor device is mounted on the flexible printed circuit board for the light emitting section.

Abstract: Methods of forming a light emitting diode are provided by scoring a semiconductor substrate having a light emitting region formed thereon so as to provide score lines between individual ones of a plurality of light emitting diodes. The semiconductor substrate is then broken along selected ones of the score lines so as to provide a unitized subset of the plurality of light emitting diodes. The unitized subset includes at least two light emitting diodes. Electrical connections are provided to the light emitting diodes of the unitized subset of the plurality of light emitting diodes. The score lines may also define the individual ones of the light emitting diodes.

Abstract: A method is provided to fabricate a LCOS back plane structure. The present invention utilized a HV device such as HV CMOS transistor (high voltage complementary metal oxide semiconductor transistor) and a HV capacitor layer are applied to the substrate. Furthermore, the HV capacitor layer has a higher dielectric layer and coupling ratio to sustain the higher operating voltage, such that the operating capacitance can be raised. Moreover, the HV CMOS transistor is combined with a mirror layer which has a higher reflective property, such that the LCOS back-plate structure has the better contrast and chrominance output in per area unit, when the operating voltage range is increased.

Abstract: A method of fabricating a monolithic integrated semiconductor photonic device is provided. In this method, it is possible to remarkably reduce an optical loss in a passive waveguide by forming a non-doped clad layer around a passive layer. Thus, the passive waveguide can be effectively coupled with an active waveguide. Further, a current confinement layer is formed around an active layer, using the non-doped clad layer. Therefore, an expensive tool such as an ion implanter is not required, thereby decreasing manufacturing costs.

Abstract: A method of heat-treating a nitride compound semiconductor layer, comprising heating a nitride compound semiconductor layer doped with a p-type impurity at a temperature that is at least 200° C. but less than 400° C. for at least 100 minutes.

Abstract: The method of fabricating a nitride semiconductor of this invention includes the steps of forming, on a substrate, a first nitride semiconductor layer of AluGavInwN, wherein 0≦u, v, w≦1 and u+v+w=1; forming, in an upper portion of the first nitride semiconductor layer, plural convexes extending at intervals along a substrate surface direction; forming a mask film for covering bottoms of recesses formed between the convexes adjacent to each other; and growing, on the first nitride semiconductor layer, a second nitride semiconductor layer of AlxGayInzN, wherein 0≦x, y, z≦1 and x+y+z=1, by using, as a seed crystal, C planes corresponding to top faces of the convexes exposed from the mask film.

Abstract: A high efficiency light emitting diode (LED) with metal reflector and the method of making the same is disclosed. The metal reflector is composed of at least two layers with one transparent conductive layer and the other highly reflective metal layer. The transparent conductive layer allows most of the light passing through without absorption and then reflected back by the highly reflective metal layer. The transparent conductive layer is selected from one of the materials that have very little reaction with highly reflective metal layer even in high temperature to avoid the reflectivity degradation during the chip processing. With this at least two layer metal reflector structure, the light emitting diode with vertical current injection can be fabricated with very high yield.

Abstract: A process for the fabrication of devices that integrate protected microstructures, comprising the following steps: forming, in a body of semiconductor material, at least one microstructure having at least one first portion and one second portion which are relatively mobile with respect to one another and are separated from one another by at least one gap region, which is accessible through a face of the body; and sealing the gap. The sealing step includes depositing on the face of the body a layer of protective material, in such a way as to close the gap region, the protective layer being such as to enable relative motion between the first portion and the second portion of the microstructure.

Abstract: In an optical semiconductor integrated circuit device in which a vertical pnp transistor and a photodiode are formed, the preferred embodiments of the present invention eliminates difficulty in performance improvement of the two elements. In an illustrative optical semiconductor integrated circuit device, a vertical pnp transistor and a photodiode have been formed, and first and second epitaxial layers and are stacked without doping. This enables a depletion layer forming region to be remarkably increased in the photodiode, and high-speed response becomes possible. Additionally, in the vertical pnp transistor, an n+ type diffusion region surrounds the transistor forming region. This can remarkably improve voltage endurance of the vertical pnp transistor 21.

Abstract: A wafer-level packaging process for MEMS applications, and a MEMS package produced thereby, in which a SOI wafer is bonded to a MEMS wafer and the electrical feed-throughs are made through the SOI wafer. The method includes providing a first substrate having the functional element thereon connected to at least one metal lead, and providing a second SOI substrate having a recessed cavity in a silicon portion thereof with metal connectors formed in the recessed cavity. The non-recessed surfaces of the SOI substrate are bonded to the first substrate to form a hermetically sealed cavity. Within the cavity, the metal leads are bonded to respective metal connectors. Prior to bonding, the recessed cavity has a depth that is greater than the thickness of the functional element and less than the combined thickness of the metal leads and their respective metal connectors. After bonding, silicon from the SOI substrate is removed to expose the buried oxide portion of the SOI substrate.

Abstract: The present invention relates to a method of manufacturing an integrated circuit package, including providing a lead frame without a die attachment pad, the lead frame having a ridge portion protruding from a base portion, the ridge portion having an upper surface and defining an upper portion of a cavity, the base portion having a lead and a lower surface, attaching an adhesive strip to at least the lower surface of the base portion to seal a bottom portion of the cavity, encapsulating the cavity such that at least a portion of the upper surface of the ridge portion of the lead frame and at least a portion of the lower surface of the base portion are exposed, and removing the adhesive strip.

Abstract: A new method and package is provided for the packaging of semiconductor devices. The method and package starts with a semiconductor substrate, the substrate is pre-baked. In the first embodiment of the invention, a copper foil is attached to the substrate, in the second embodiment of the invention a adhesive film is attached to the substrate. Processing then continues by attaching the die to the copper foil under the first embodiment of the invention and to the film under the second embodiment of the invention. After this the processing continues identically for the two embodiments of the invention with steps of curing, plasma cleaning, wire bonding, optical inspection, plasma cleaning and providing a molding around the die and the wires connected to the die. For the second embodiment of the invention, the film is now detached and replaced with a copper foil.

Abstract: Thick film bond surfaces (8 ) on a support structure (10), such as a ceramic substrate or an IC package substrate, tend to deform during processing. A personality kit (16 ) having raised bosses (24 ) engages with and compresses the bond surfaces, resulting in a flatter, wider bond surface having improved reflectivity. The personality kit (16 ) is fit within a clamp (30 ) that can be used as a stand-alone unit or integrated into an existing machine, such as a wire bonder (46).

Abstract: A semiconductor device (21) can include, e.g., a recessed portion (25) on the reverse surface (224) of an insulating resin (22) which is the mounting surface of the semiconductor device (21). Additionally, on the outer peripheral surface of the recessed portion (25), the exposed region of leads (26) and the reverse surface (224) of the insulating resin (22) form generally the same plane. This allows, e.g., a QFN semiconductor device (21) according to preferred embodiments herein to place dust particles in the recessed portion (25) even in the presence of dust particles such as crushed burr particles of the leads (26) or plastic burrs, thereby avoiding mounting deficiencies when mounting the semiconductor device.

Abstract: A semiconductor device is manufactured in such a way that a semiconductor chip connected with leads whose internal ends are interconnected with bonding wires are completely sealed and enclosed in a resin corresponding to a package while external ends of leads are exposed from the surface of the package. In manufacture, a chip fixing member is used to fix the semiconductor chip in a prescribed position, while wire fixing members are used to fix the bonding wires in prescribed positions. Both the fixing members are retracted into the split mold so as to avoid formation of unfilled portions or voids in the resin in the cavity. In inspection, an electrical conduction is detected between the bonding wire(s) and an electrode layer formed inside of the cavity, so that a semiconductor device produced in the cavity is automatically removed from the manufacturing line.

Abstract: In one aspect, the present invention features a method of manufacturing an integrated circuit package including providing a substrate having a first surface, a second surface opposite the first surface, a cavity through the substrate between the first and second surfaces and a conductive via extending through the substrate and electrically connecting the first surface of the substrate with the second surface of the substrate, applying a strip to the second surface of the substrate, mounting a semiconductor die on the strip, at least a portion of the semiconductor die being disposed inside the cavity, encapsulating in a molding material at least a portion of the first surface of the substrate, and removing the strip from the substrate.

Abstract: A method of forming a non-volatile resistance variable device includes forming a patterned mass comprising elemental silver over a substrate. A layer comprising elemental selenium is formed over the substrate and including the patterned mass comprising elemental silver. The substrate is exposed to conditions effective to react only some of the elemental selenium with the elemental silver to form the patterned mass to comprise silver selenide. Unreacted elemental selenium is removed from the substrate. A first conductive electrode is provided in electrical connection with one portion of the patterned mass comprising silver selenide. A germanium selenide comprising material is provided in electrical connection with another portion of the patterned mass comprising silver selenide. A second conductive electrode is provided in electrical connection with the germanium selenide comprising material.

Abstract: A method of forming a SiGe layer having a relatively high Ge content includes preparing a silicon substrate; depositing a layer of SiGe to a thickness of between about 100 nm to 500 nm, wherein the Ge content of the SiGe layer is equal to or greater than 22%, by molecular weight; implanting H+ ions into the SiGe layer at a dose of between about 1·1016 cm−2 to 5·1016 cm−2, at an energy of between about 20 keV to 45 keV; thermal annealing the substrate and SiGe layer, to relax the SiGe layer, in an inert atmosphere at a temperature of between about 650° C. to 950° C. for between about 30 seconds and 30 minutes; and depositing a layer of tensile-strained silicon on the relaxed SiGe layer to a thickness of between about 5 mn to 30 nm.

Abstract: A method of fabricating a thin film includes: forming, on a substrate, a thin film with film properties varying from region to region on the substrate, by selectively heating the substrate; and patterning the thin film in a predetermined pattern by etching the thin film to selectively remove only a portion of the thin film with specified film properties. The method reduces the fabrication process temperature and the number of fabrication steps, while inhibiting degradation in device performance.

Abstract: A silicon-on-insulator (SOI) integrated circuit and a method of fabricating the SOI integrated circuit are provided. At least one isolated transistor active region and a body line are formed on an SOI substrate. The transistor active region and the body line are surrounded by an isolation layer which is in contact with a buried insulating layer of the SOI substrate. A portion of the sidewall of the transistor active region is extended to the body line. Thus, the transistor active region is electrically connected to the body line through a body extension. The body extension is covered with a body insulating layer. An insulated gate pattern is formed over the transistor active region, and one end of the gate pattern is overlapped with the body insulating layer.

Abstract: A photodetector is integrated on a single semiconductor chip with bipolar transistors including a high speed poly-emitter vertical NPN transistor. The photodetector includes a silicon nitride layer serving as an anti-reflective film. The silicon nitride layer and oxide layers on opposite sides thereof insulate edges of a polysilicon emitter from the underlying transistor regions, minimizing the parasitic capacitance between the NPN transistor's emitter and achieving a high frequency response. The method of manufacture is compatible with existing BiCMOS process technology, the silicon nitride layer of the anti-reflective film being formed over the photodetector as well as regions of the chip that include the vertical NPN transistor and other circuit elements.

Abstract: In the production of channel etch type bottom gate thin film transistors, etching damage in a channel etch step is prevented to improve the transistor performance. The channel etch is performed using non-ionic excited species, such as hydrogen radicals and fluorine radicals, generated by contact-decomposition reaction which utilizes a metal heated by electric resistance heating. Alternatively, in place of the channel etch, a portion of the source/drain semiconductor thin film immediately above the channel is nitrided by a non-ionic nitrogen-containing decomposition product that is produced by contacting molecules of a chemical substance containing nitrogen atoms with a metal heated by electric resistance heating to decompose the chemical molecules.

Abstract: An emitter includes an electron supply and a tunneling layer disposed on the electron supply. A cathode layer is disposed on the tunneling layer. A conductive electrode has multiple layers of conductive material. The multiple layers include a protective layer disposed on the cathode layer. The conductive electrode has been etched to define an opening thereby exposing a portion of the cathode layer.

Abstract: A method for eliminating polysilicon residue is provided by converting the polysilicon residue into silicon dioxide in two steps. A tilted ion implantation step is performed to implant oxygen ions into the polysilicon residue to rich oxygen containing of the polysilicon residue. An oxygen anneal step is subsequently performed to completely convert the rich oxygen containing polysilicon residue into silicon dioxide that can eliminate the conductivity of the polysilicon residue and prevent oxygen encroachment occurring.

Abstract: Methods of fabricating a stack-gate flash memory array are disclosed by the present invention, in which a self-aligned integrated floating-gate layer includes a major floating-gate layer formed on a thin tunneling dielectric layer and two extended floating-gate layers formed on planarized filed-oxides (FOX); a high-conductivity word line is formed by a composite conductive layer of metal or silicide/barrier-metal/doped polycrystalline- or amorphous-silicon as a control-gate layer and is encapsulated by the dielectric layers; a self-registered common-source/drain bus line is formed on a flat bed formed by common-source/drain diffusion regions and planarized field-oxides; a self-registered common-source/drain landing island is formed on a common-source/drain diffusion region to act as a self-aligned contact and a dopant diffusion source for forming a shallow heavily-doped commmon-source/drain diffusion region.

Abstract: In methods for fabricating MOS transistors with notched gate electrodes, a notched gate electrode may be readily fabricated using a damascene process for filling a stair-shaped opening formed in a multi-layered insulation layer. In this manner, the width and a height of the notch region of the gate electrode may be readily adjusted and controlled.