Abstract: A resistive film for use in a potentiometer. The film is in contact with a movable wiper. The film includes a cured polymer resin and a cured thermosetting resin. Conductive particles of carbon black and graphite are dispersed in the film. The conductive particles cause the resins to be electrically resistive. Carbon nanoparticles are also dispersed in the film. The nanoparticles increase the wear resistance of the resistive film and reduce electrical noise as the wiper moves across the film.

Abstract: A photochromic naphthopyran displays good color distribution when the naphthopyran has a central nucleus of the formula: 1

Abstract: Organic dye molecular materials prepared by coupling existing organic chromophore molecules to benzene or carbazole derivatives and nonlinear optical polymeric compounds having polyimide repeating units coupled with the organic dye molecular material are provided.

Abstract: This invention provides a multi-layer circuit board excellent in flame resistance, insulating property and adhesion and not generating detrimental substances when burnt, and a curable composition suitable for obtaining the multi-layer circuit board. The curable composition contains an insulating resin such as an alicyclic olefin polymer or an aromatic polyether polymer, a nitrogen-type curing agent such as 1,3-diallyl-5-glycidyl isocyanurate and a phosphorus-type flame retardant such as phosphoric acid ester amide, and is molded into a film by a solution casting method. The film so formed is laminated on an internal layer board and is cured to give the multi-layer circuit substrate.

Abstract: A multi-tiered assembly of leveler units with a vehicle wheel positional restraint is provided. The leveler units each comprise a planar body, with upper and lower surfaces circumscribed by edges. The body of each unit bears a plurality of pins upwardly extending from the upper surface and has a plurality of pockets formed in the lower surface to receive corresponding pins of other similar units. The pins are of slightly smaller size than the corresponding pockets. The positional restraint can interlock with the other leveler units and additionally provide an upper surface with an obstruction to prevent wheel movement.

Abstract: Fiber density and installation length are improved by enclosing optical fibers in a very small diameter metal jacket, resulting in increased cable stiffness and durability. The metal jacket consists of a small diameter, thin sidewall laser-welded steel tube that is loosely filled with optical fiber strands and a gel waterproofing material that provides a longitudinal water-barrier. The fibers are free to “float” within the steel jacket, and thus are decoupled from external mechanical forces and stresses that act on the cable during installation. When bundles of the steel-jacketed fiber optic cables are installed with pushing and blowing, about twice the installation length is reached as compared with pure blowing. Also, the number of cables and fiber density in each guide tube can be increased, thus increasing the fiber capacity of the feeding ducts and branch ducts of a fiber optic communications network.

Abstract: An improved structure manual tensioner in which: the primary member consists of a narrow plate of greater and lesser dimensions shaped into a pair of large and small parallel support arms. The large parallel support arm has a cylindrical handle formed contiguous to its free end and a protruding tab with a catch hole and a rivet hole are disposed in the parallel section of its surface to provide for the assembly to the small parallel support arm, thereby enabling the saving of both material and space, while also providing for extremely comfortable manual grasping in a simple structure that prevents slippage. As such, the fabrication procedures of the present invention are simple and convenient, assembly and installation efficiency is increased, and the spindle and the secondary member are structurally straightforward and not difficult to produce.

Abstract: A lifting column, preferably for height-adjustable articles of furniture, such as beds and tables, comprises a drive unit (13), wherein extension of the column takes place with at least one flexible element (9), such as a chain, belt or the like running over a pulley wheel. The column comprises two rigidly interconnected pulley wheels (16) and two additional pulley wheels (7) which are arranged such that the four wheels form two pairs and which are rigidly connected with a flexible link in the column. The flexible element runs over each of the two pairs of pulley wheels. One run of the flexible elements between two pulley wheels is fixed to a link in the column, while the other run is fixed to a subsequent link. When the column is subjected to moment loading, the forces will compensate each other fully or partly because of the rigid interconnection between the two sets of pulley wheels (16). The column is hereby very rigid.

Abstract: A portable and collapsible fence that can be conveniently stored and transported in a lightweight carrying case. The fence includes panels having telescopic rail sections and telescopic posts. The middle section of each fence panel includes a series of spaced “rail pairs.” The use of the rail pairs adds structural stability to the fence panels and allows the fence panels to utilize many identical parts, such that the panels can be manufactured efficiently and economically. The fence is also preferably formed of lightweight polymer so that it is resilient and easily transported by hand in a relatively small carrying case provided therefor.

Abstract: A method of forming resistance changing elements with improved operational characteristics for use in memory devices and the resulting structures are disclosed. A chalcogenide glass having the formula (Gex 1Se1−x1)1−y1Agy1, wherein 18≦xl≦28, or the formula (Gex2Sel−x2)1−y2Agy2 wherein 39≦x2≦42, and wherein in both the silver is in a concentration which maintains the germanium selenide glass in the glass forming region is used in a memory cell. The glass may also have a glass transition temperature (Tg) near or higher than typical temperatures used for fabricating and packaging memory devices containing the memory cell.

Abstract: An integrated circuit metal oxide semiconductor device comprises a gate region and a dielectric layer positioned therein, wherein the dielectric layer is substantially free of germanium diffused therein from a silicon germanium layer of the device. The method comprises depositing a dummy replacement gate, subjecting the device to high temperature processing, removing the dummy gate, and then depositing a dielectric material and a final gate material within the formed gate region. Because the dielectric material is deposited after high temperature processing of the device, there is negligible diffusion of germanium into the dielectric material.

Abstract: A finger SQUID qubit device and method for performing quantum computation with said device is disclosed. A finger SQUID qubit device includes a superconducting loop and one or more superconducting fingers, wherein the fingers extend to the interior of said loop. Each finger has a mesoscopic island at the tip, separated from the rest of the finger by a Josephson junction. A system for performing quantum computation with the finger SQUID qubit device includes a mechanism for initializing, entangling, and reading out the qubits. The mechanism may involve passing a bias current across the leads of the superconducting loop and a mechanism for measuring a potential change across the leads of the superconducting loop. Furthermore, a control system includes a mechanism for addressing specific qubits in a quantum register of finger SQUID devices.

Abstract: A finger SQUID qubit device and method for performing quantum computation with said device is disclosed. A finger SQUID qubit device includes a superconducting loop and one or more superconducting fingers, wherein the fingers extend to the interior of said loop. Each finger has a mesoscopic island at the tip, separated from the rest of the finger by a Josephson junction. A system for performing quantum computation with the finger SQUID qubit device includes a mechanism for initializing, entangling, and reading out the qubits. The mechanism may involve passing a bias current across the leads of the superconducting loop and a mechanism for measuring a potential change across the leads of the superconducting loop. Furthermore, a control system includes a mechanism for addressing specific qubits in a quantum register of finger SQUID devices.

Abstract: A method for producing quantum dots. The method includes cleaning an oxide substrate and separately cleaning a metal source. The substrate is then heated and exposed to the source in an oxygen environment. This causes metal oxide quantum dots to form on the surface of the substrate.

Abstract: In a method of manufacturing a Josephson junction, a first superconductive layer is formed on a substrate. An insulating film is formed on the first superconductive layer. The insulating film is etched to have an inclination portion. The first superconductive layer is etched using the etched insulating film as a mask, to have an inclination portion. A barrier layer is formed on a surface of the inclination portion of the first superconductive layer. A second superconductive layer is formed on the barrier layer and the inclination portion of the insulating layer.

Abstract: A semiconductor structure for providing an epitaxial zinc oxide layer having p-type conduction for semiconductor device manufacture and methods of depositing the p-type zinc oxide layer. A zinc oxide layer is deposited epitaxially by molecular beam epitaxy on a crystalline zinc oxide substrate. The zinc oxide layer incorporates a p-type dopant, such as nitrogen, in an atomic concentration adequate to provide p-type conduction. The p-type zinc oxide layer may further incorporate an atomic concentration of a compensating species, such as lithium, sufficient to electronically occupy excess donors therein so that the efficiency of the p-type dopant may be increased.

Abstract: To prevent data quality from being deteriorated by reflection from each of memory modules, a semiconductor memory device has a switching circuit located on a mother board in the vicinity of a branching point of the data bus. The switching circuit is controlled by a memory controller to selectively operate the memory modules without substantial reflection from a selected one of the memory modules. To this end, each of the memory modules and the memory controller is terminated with characteristic impedance of the data bus.

Abstract: A laser repair facilitated pixel structure and repair method. The pixel structure includes a thin film transistor, a pixel electrode, and a conductive line. Control of the pixel structure is carried out through signals passing to a scan line and a data distributing line. The conductive line is underneath the data distributing line. The conductive line has a connective section and a repair section at each end of the connective section. Each repair section occupies an area greater than the data distributing line. A broken data distributing line is repaired through the formation of an electrical connection between the repair sections at each end of the conductive line and the data distributing line.

Abstract: Multilayer anode structures (104) for electronic devices (100) such as polymer light-emitting diodes are described. The multilayer anodes include a high conductivity organic layer (114) adjacent to the photoactive layer (102) and a low conductivity organic layer (112) between the high conductivity organic layer and the anode's electrical connection layer (110). This anode structure provides polymer light emitting diodes which exhibit high brightness, high efficiency and long operating lifetime. The multilayer anode structure of this invention provides sufficiently high resistivity to avoid cross-talk in passively addressed pixellated polymer emissive displays; the multilayer anode structure of this invention simultaneously provides long lifetime for pixellated polymer emissive displays.

Abstract: A semiconductor configuration with an ohmic contact-connection includes a p-conducting semiconductor region made of silicon carbide. A p-type contact region serves for the contact-connection. The p-type contact region is composed of a material containing at least nickel and aluminum. A substantially uniform material composition is present in the entire p-type contact region. A method for contact-connecting p-conducting silicon carbide with a material containing at least nickel and aluminum is also provided. The two components nickel and aluminum are applied simultaneously on the p-conducting semiconductor region.

Abstract: A light emitting diode includes a lower electrode, a semiconductor substrate, a lower cladding layer, an action layer, an upper cladding layer, a window diffusion layer, and a composite upper electrode. The composite upper electrode includes an ohmic contact layer formed on a partial surface of the window diffusion layer, and a conductive transparent connecting oxidation layer coated on the ohmic contact layer and directly coated on a partial surface of the window diffusion layer to connect the ohmic contact layer and a wiring metal electrode layer.

Abstract: An objective is to increase the reliability of a light emitting device structured by combining TFTs and organic light emitting elements. A TFT (1201) and an organic light emitting element (1202) are formed on the same substrate (1203) as structuring elements of a light emitting device (1200). A first insulating film (1205) which functions as a blocking layer is formed on the substrate (1203) side of the TFT (1201), and a second insulating film (1206) is formed on the opposite upper layer side as a protective film. In addition, a third insulating film (1207) which functions as a barrier film is formed on the lower layer side of the organic light emitting element (1202). The third insulating film (1207) is formed by an inorganic insulating film such as a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, an aluminum oxide film, or an aluminum oxynitride film.

Abstract: A semiconductor optical integrated device 1 comprises a light-emitting element portion 110, modulation element portion 120, and separation portion 130 on a substrate 2. Light-emitting element portion 110 comprises a semiconductor laser element portion, and modulation element portion 120 comprises a modulation element portion. Separation portion 130 is formed between light-emitting element portion 110 and modulation element portion 120. In separation portion 130, a semiconductor embedded portion 80e is provided in a second clad layer 8m. Whereas second clad layer 8m consists of p-type InP, semiconductor embedded portion 80e consists of n-type InP. Hence semiconductor embedded portion 80e has the effect of impeding the leakage current flowing between electrodes 90a and 90b. As a result, the leakage current occurring between electrodes 90a and 90b via second clad layer 8m is reduced.

Abstract: A lower cladding layer is laminated on a substrate and constituted of at least one layer. A light absorption layer is laminated on the lower cladding layer. An upper cladding layer is laminated above the light absorption layer and constituted of at least one layer. A light incident end surface is provided on at least one of the substrate and the lower cladding layer, and, when a light is made incident at a predetermined angle, enables the light to be absorbed in the light absorption layer and to be output as a current. An equivalent refractive index of the at least one of the substrate and the lower cladding layer is larger than that of the upper cladding layer. The predetermined angle is an angle enabling a light incident into the light absorption layer to be reflected at a lower surface of the upper cladding layer.

Abstract: A solid-state, surface-emitting, optical device such as a light emitting diode (LED) or vertical cavity surface emitting laser (VCSEL) has a body of optical gain medium overlying a high reflectivity distributed BRAGG reflector (DBR) mirror which is carried on part of an underlayer. The gain layer is part of an epitaxial layered structure extending from the underlayer and over the mirror.

Abstract: A triplet light emitting device which has high efficiency and improved stability and which can be fabricated by a simpler process is provided by simplifying the device structure and avoiding use of an unstable material. In a multilayer device structure using no hole blocking layer conventionally used in a triplet light emitting device, that is, a device structure in which on a substrate, there are formed an anode, a hole transporting layer constituted by a hole transporting material, an electron transporting and light emitting layer constituted by an electron transporting material and a dopant capable of triplet light emission, and a cathode, which are laminated in the stated order, the combination of the hole transporting material and the electron transporting material and the combination of the electron transporting material and the dopant material are optimized.

Abstract: An AlGaInP layer is formed on a substrate made of GaAs, and an AlGaAs layer is formed on the AlGaInP layer via a buffer layer therebetween. The buffer layer has a thickness of about 1.1 nm and is made of AlGaInP whose Ga content is smaller than that of the AlGaInP layer. The buffer layer may alternatively be made of AlGaAs whose Al content is smaller than that of the AlGaAs layer.

Abstract: The present invention discloses an electrode structure of a light emitted diode and manufacturing method of the electrodes. After formed a pn-junction 2, 3 of a light emitted diode on a substrate 1, a layer of SiO2 is deposited on the periphery of the LED die near the scribe line of the wafer, then a transparent conductive layer 5 is deposited, then a layer of gold or AuGe etc 6, is formed with an opening on the center of the die. After forming alloy with the semiconductor by heat treatment to form ohmic contact, a strip of aluminum (Al) 7 is formed on one side of the die on the front side for wire bonding and to be the positive electrode of the LED. The negative electrode 10 is formed on the substrate by metal contact.

Abstract: A light shield film is provided adjacent to an anode of an EL element that consists of the anode, an EL layer, and a cathode. The anode and the cathode are transparent or semitransparent to visible light and hence transmit EL light. With this structure, ambient light is absorbed by the light shield film and does not reach an observer. This prevents an external view from appearing on the observation surface.

Abstract: A semiconductor component, in particular a micromechanical pressure sensor based on silicon, having a base layer, an at least largely self-supporting diaphragm and an overlayer situated on the diaphragm, the diaphragm and the base layer, at least from place to place, delimiting a void. Furthermore, at least from place to place, above the diaphragm a conducting region is provided in the overlayer which is electrically poorly conductive as compared to the conducting region, to which the surface of the diaphragm that faces the overlayer is able to be electrically contacted.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a concentration of a first material at a first depth, where the first material impedes the diffusion of a base dopant. For example, the first material can be carbon and the base dopant can be boron. The first material also causes a change in band gap at the first depth in the base. According to this exemplary embodiment, the base further comprises a concentration of a second material, where the concentration of second material increases at the first depth so as to counteract the change in band gap. For example, the second material may be germanium. The concentration of the second material, for example, may increase at the first depth by amount required to cause a decrease in band gap to be substantially equal to the increase in band gap caused by concentration of the first material.

Abstract: According to one exemplary embodiment, a heterojunction bipolar transistor comprises a base having a concentration of germanium, where the concentration of germanium decreases between a first depth and a second depth in the base. According to this exemplary embodiment, the base of the heterojunction bipolar transistor further comprises a concentration of a diffusion suppressant of a base dopant, where the concentration of the diffusion suppressant decreases between a third depth and a fourth depth so as to counteract a decrease in band gap in the base between the first depth and the second depth. For example, the diffusion suppressant can be carbon and the base dopant can be boron. For example, the concentration of diffusion suppressant may decrease between the third depth and fourth depth so as to counteract the decrease in band gap at approximately the second depth.

Abstract: A booster circuit for a non-volatile semiconductor memory device has a drive control circuit. At a power supply ON time or at a reset time, in response to an externally input power supply ON/reset signal ON/RS, the drive control circuit does not drive a weak charge pump but drives a strong charge pump, which has a greater current capacity than that of the weak charge pump, even in a standby mode. This arrangement enables a boosted voltage HV to quickly rise from 0 V to a standby voltage, thus desirably shortening an initial access permission time at the power supply ON time or at the reset time.

Abstract: Dielectric compositions comprised of porous polymeric matrices are prepared using nitrogen-containing polymers as pore-generating agents. The compositions are useful in the manufacture of electronic devices such as integrated circuit devices and integrated circuit packaging devices. The dielectric compositions are prepared by admixing a polymeric nitrogenous porogen with a high temperature, thermosetting host polymer in a suitable solvent, heating the admixture to cure the polymer and provide a vitrified matrix, and then decomposing the porogen using heat, radiation, or a chemical reagent effective to degrade the porogen. The highly porous dielectric materials so prepared have an exceptionally low dielectric constant on the order of 2.5 or less, preferably less than about 2.0. Integrated circuit devices and integrated circuit packaging devices manufactured so as to contain the dielectric material of the invention are provided as well.

Abstract: A phase-change memory cell may be formed by selectively depositing the lower electrode in the phase-change memory pore. Thereafter, an adhesion-promoting material may be selectively deposited on the selectively deposited lower electrode and the upper surface surrounding the pore. Through the use of selective deposition techniques, the adhesion-promoting material can be positioned where needed and the lower electrode may be defined in a fashion that may reduce shunting current, reduce device current requirements, and increase dynamic range in some embodiments.

Abstract: An organic light emitting device has a layer structure comprising: a first electrode layer (20); a second electrode layer (40) parallel to the first electrode layer (20); and, an electrically conductive and light transmissive layer (70) parallel to the second electrode layer. An electrically insulating layer (30) is disposed between the first and second electrode layers. A layer of organic material (50) is disposed between the second electrode layer and the conductive layer. An aperture (60) in the organic layer provides an electrical connection path between the conductive layer and one of the first and second electrode layers.

Abstract: A semiconductor integrated circuit makes use of nonvolatile memory cells of a fuse circuit connected to a dedicated signal line without using a nonvolatile memory intended for general purpose use, which is connected to a common bus, in order to store control information for defect relief and the like of circuit modules. The reliability of storage of the control information is not limited to the performance of storage of information in the nonvolatile memory intended for general purpose use, and the reliability of storage of the control information can be easily enhanced. Since a second wiring used in the transfer of the control information is of a wiring dedicated for its transfer, it needs not perform switching between connections to circuit portions used for actual operations in the circuit modules and their control. A circuit configuration for delivering the control information can be simplified.

Abstract: Floating-gate memory cells having a trench source-line contact are suited for increased packing densities without a need for low-resistance ground straps placed at regular intervals across a memory array. Such floating-gate memory cells have their drain regions and source regions formed in a first semiconductor region having a first conductivity type. This first semiconductor region is separated from the underlying substrate by an interposing second semiconductor region having a second conductivity type different from the first conductivity type. The source regions of the memory cells are coupled to the second semiconductor region as a common source line. Such memory cells can be programmed, read and erased by applying various potential levels to their control gates, their drain regions, the first semiconductor region, and the second semiconductor region.

Abstract: An integrated circuit having a gate region, a source drain region, and an electrically nonconductive spacer separating the gate region and the source drain region. A local interconnect electrically connects the gate region to the source drain region across the electrically nonconductive spacer. The local interconnect is formed of a semiconducting material reacted with a metal. The local interconnect may be formed by implanting a precursor species into the electrically nonconductive spacer. A metal layer is deposited over at least the electrically nonconductive spacer, and the integrated circuit is heated to form an electrically conductive local interconnect from the metal layer and the precursor species implanted in the electrically nonconductive spacer.

Abstract: There is provided a method of fabricating a gate electrode, including the steps of (a) forming a gate oxide film at a surface of a semiconductor substrate, (b) forming a multi-layered structure on the gate oxide film, the multi-layered structure including a polysilicon layer formed on the gate oxide film, a refractive metal silicide layer formed on the polysilicon layer, and a silicon nitride layer formed on the refractive metal silicide layer, (c) thermally annealing the multi-layered structure in a nitrogen atmosphere to thereby form a silicon nitride film on sidewalls of the polysilicon layer and the refractive metal silicide layer, and (d) oxidizing the semiconductor substrate and the multi-layered structure.

Abstract: Disclosed is a method of manufacturing a semiconductor device capable of improving the reliability of the semiconductor device, which has a field effect transistor having a source-drain structure with a shallow junction. In the process for realizing the reduction of the resistance in a diffusion layer for a source and drain with a shallow junction, in which a part of an amorphous layer formed by the ion implantation for forming a diffusion layer for a source and drain is selectively melted and recrystallized by the use of laser irradiation, in order to prevent the occurrence of defects such as short circuit at a portion where a region to be melted and a gate electrode are overlapped with each other, ion implantation is performed after the formation of a first gate sidewall insulator on a sidewall of the gate electrode so as to obtain a structure in which the amorphous layer is not overlapped with the gate electrode.

Abstract: The invention relates to improving the switching reliability of a magnetic memory cell in a magnetic random access memory (MRAM). Embodiments of the invention add an antiferromagnet to a magnetic memory cell. An antiferromagnetic layer can be formed adjacent to a soft layer in the MRAM on a side of the soft layer that is opposite to a hard layer of the MRAM. One embodiment further includes an additional interlayer of non-antiferromagnetic material between the antiferromagnetic layer and the soft layer.

Abstract: A memory cell of a stacked type is formed by a MOS transistor and a ferroelectric capacitor. The MOS transistor is formed in an active region of a substrate of semiconductor material and comprises a conductive region. The ferroelectric capacitor is formed on top of the active region and comprises a first and a second electrodes separated by a ferroelectric region. A contact region connects the conductive region of the MOS transistor to the first electrode of the ferroelectric capacitor. The ferroelectric capacitor has a non-planar structure, formed by a horizontal portion and two side portions extending transversely to, and in direct electrical contact with, the horizontal portion.

Abstract: A memory module, in particular a DRAM, has a memory cell array with memory cells disposed in a matrix form. Dummy memory cells are formed in an edge region of the memory cell array, which dummy memory cells are not used for storing items of information. First electrodes of the dummy memory cells are connected to a reference potential. A counter electrode of the dummy memory cells is electrically connected to the counter electrode of the memory cells. A charge capacitance of the counter electrode of the memory cells is increased in this way. Consequently, there is an overall increase in the voltage stability of the memory module with respect to a large entry of charge into the memory cells.

Abstract: A semiconductor device that quickly saves data stored in an area to which power is supplied intermittently. Power is supplied intermittently to a first area. Power is supplied continuously to a second area. A memory is located in the second area. A save circuit saves data used in the first area in the memory before the supply of power being stopped. A restoration circuit restores data which has been saved in the memory to a predetermined circuit in the first area. A power supply control circuit supplies power to the memory if data has been saved in the memory. Otherwise the power supply control circuit stops the supply of power to the memory.

Abstract: The invention relates to an electronic device provided with an electronic component which comprises an integrated circuit arrangement including a semiconducting substrate, active components, and passive components such as capacitors and resistors. The resistors comprise materials of a high resistivity and can be manufactured with resistance values which lie within a narrow tolerance range.

Abstract: The present invention alleviates stiction between a suspended beam or microstructure and an underlying substrate by providing a patterned passivation layer on the substrate underneath the beam. The passivation layer is patterned to provide a substrate surface that differs substantially from the bottom surface of the beam. The difference between these two surfaces reduces the potential contact area between the beam and the substrate when the beam is pulled down, thereby reducing adhesive forces between the beam and the substrate and reducing the likelihood of stiction. In one embodiment, the passivation layer is patterned to form a substrate surface comprising a plurality of protuberances. In another embodiment, the passivation layer is patterned to form a substrate surface having a mesh pattern.

Abstract: The scalable multi-bit flash memory cell includes three regions: the first-side region, the gate region, and the second-side region, in which the gate region includes two stack-gate transistors and one select-gate transistor. The first-side/second-side region comprises a sidewall-oxide spacer formed over the gate region and from top to bottom comprises a planarized thick-oxide layer, a silicided conductive layer formed on a flat bed, and a common-diffusion region. The stack-gate transistor comprises from top to bottom a sidewall dielectric spacer, an elongated control-gate layer formed over an intergate dielectric layer, and an integrated floating-gate layer. The select-gate transistor comprises a planarized conductive island formed over a gate-dielectric layer and is connected to a word line. A plurality of scalable multi-bit flash memory cells are alternately arranged to form a scalable multi-bit flash memory cell array.

Abstract: The present invention discloses a floating gate for memory of high gate coupling ratio and the method of manufacturing the same. It utilizes a continuously concave-convex surface formed on the floating gate, and by virtue of the increase of the surface area of which to increase the gate coupling ratio with a control gate and further to reduce the working voltages for programming and erasing.

Abstract: A semiconductor nonvolatile memory device improving reproducibility and reliability of insulation breakage of a silicon oxide film and capable of reducing the manufacturing cost and a method for production of the same, wherein each of the memory cells arranged in a matrix form has an insulating film breakage type fuse comprising an impurity region of a first conductivity type formed on a semiconductor substrate, a first insulating film formed on the semiconductor substrate while covering the impurity region, an opening formed in the first insulating film so as to reach the impurity region, and a first semiconductor layer of a first conductivity type, a second insulating film, and a second semiconductor layer of a second conductivity type successively stacked in the opening from the impurity region side, or has an insulating film breakage type fuse comprising an impurity region of a first conductivity type in the first semiconductor layer having an SOI structure, a first insulating film on the SOI layer, an op