Patents Issued in August 7, 2003
-
Publication number: 20030146468Abstract: A method of manufacturing a bipolar transistor in a P-type substrate, including the steps of forming in the substrate a first N-type area; forming by epitaxy a first silicon layer; forming in this first layer, and substantially above the first area a second heavily-doped P-type area separate from the second area; forming at the periphery of this second area a third N-type area; forming by epitaxy a second silicon layer; forming a deep trench crossing the first and second silicon layers, penetrating into the substrate and laterally separating the second area from the third area; and performing an anneal such that the dopant of the third area is in continuity with that of the first area.Type: ApplicationFiled: March 4, 2003Publication date: August 7, 2003Applicant: STMicroelectronics S.AInventors: Yvon Gris, Thierry Schwartzmann
-
Publication number: 20030146469Abstract: A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.Type: ApplicationFiled: December 2, 2002Publication date: August 7, 2003Applicant: Hitachi, Ltd.Inventors: Hideyuki Matsuoka, Kiyoo Itoh, Motoyasu Terao, Satoru Hanzawa, Takeshi Sakata
-
Publication number: 20030146470Abstract: In semiconductor devices which include an insulated trench electrode (11) in a trench (20), for example, trench-gate field effect power transistors and trenched Schottky diodes, a cavity (23) is provided between the bottom (25) of the trench electrode (11) and the bottom (27) of the trench (20) to reduce the dielectric coupling between the trench electrode (11) and the body portion at the bottom (27) of the trench in a compact manner. In power transistors, the reduction in dielectric coupling reduces switching power losses, and in Schottky diodes, it enables the trench width to be reduced.Type: ApplicationFiled: December 3, 2002Publication date: August 7, 2003Applicant: KONINKLIJKE PHILIPS ELECTRONICS N.V.Inventors: Erwin A. Hijzen, Michael A.A. In 't Zandt, Raymond J.E. Hueting
-
Publication number: 20030146471Abstract: A charge coupled device of the present invention includes a charge transfer region layer and a gate insulation film that are formed in the stated order on a semiconductor substrate, first gate electrodes formed at predetermined spaces on the gate insulation film, and second gate electrodes arranged between the first gate electrodes with at least silicon oxide films being interposed therebetween. Each silicon oxide film has constricted portions where the silicon oxide film is in contact with the gate insulation film, and electric insulation films are formed on the constricted portions so as to form sidewalls. This configuration decreases the charge transfer efficiency and increases a dielectric breakdown voltage between gate electrodes. Thus, a charge coupled device having high performance and high dielectric strength is provided.Type: ApplicationFiled: January 29, 2003Publication date: August 7, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroshi Tanaka, Ken Henmi
-
Publication number: 20030146472Abstract: A method and apparatus thereof for fabricating an integrated circuit on a laminate having a gate electrode layer over a silicon dioxide layer. Detection of the gate etch endpoint signal is improved by maximizing the use of a faster etching dopant material (e.g., n-type dopant) and minimizing the use of a slower etching dopant material (e.g., p-type dopant) in the gate electrode layer. In one embodiment, a first portion of the gate electrode layer, substantially corresponding only to the location at which a gate is to be formed, is doped with the slower etching dopant material. The remaining portion of the gate electrode layer is doped with the faster etching dopant material; thus, more of the gate electrode layer is doped with the faster etching dopant material than with the slower etching dopant material. A gate mask is aligned over the gate electrode layer, and the unmasked portions of the gate electrode layer are removed using an etchant.Type: ApplicationFiled: February 11, 2003Publication date: August 7, 2003Inventors: Calvin Todd Gabriel, Tammy D. Zheng, Emmanuel de Muizon, Linda A. Leard
-
Publication number: 20030146473Abstract: A semiconductor layer 30 of a graded SiGe-HDTMOS is constructed of an upper Si film 12, an Si buffer layer 13, an Si1−xGex film 14 and an Si cap layer 15. The region between a source region 20a and drain region 20b of the semiconductor layer 30 includes a high concentration n-type Si body region 22 and an n Si region 23, an Si cap region 25 and an SiGe channel region 24. A Ge composition ratio x of the Si1−xGex film 14 is made to increase from the Si buffer layer 13 to the Si cap layer 15. For the p-type HDTMOS, the electron current component of the substrate current decreases.Type: ApplicationFiled: December 13, 2002Publication date: August 7, 2003Inventors: Akira Inoue, Takeshi Takagi, Yoshihiro Hara, Minoru Kubo
-
Publication number: 20030146474Abstract: A silicon-on-isolator CMOS integrated circuit device includes a semiconductor substrate, an isolation layer formed over the semiconductor substrate, an n-type MOS transistor having a gate, a drain region, and a source region formed over the isolation layer, and a p-type MOS transistor having a gate, a drain region, and a source region formed over the isolation layer and contiguous with the n-type MOS transistor, wherein the n-type MOS transistor and the p-type MOS transistor form a silicon controlled rectifier to provide electrostatic discharge protection.Type: ApplicationFiled: February 5, 2002Publication date: August 7, 2003Applicant: Industrial Technology Research InstituteInventors: Ming-Dou Ker, Kei-Kang Hung, Chyh-Yih Chang
-
Publication number: 20030146475Abstract: A pixel structure comprising a thin film transistor, a pixel electrode, a scan line, a data line and an alignment mark. The alignment mark is formed beneath the data line. Misalignment is assessed through the degree of shifting between the alignment mark and the data line relative to each other. In addition, misalignment is also gauged through the degree of shifting between the alignment mark and the channel layer within the thin film transistor relative to each other.Type: ApplicationFiled: January 17, 2003Publication date: August 7, 2003Inventor: Han-Chung Lai
-
Publication number: 20030146476Abstract: A semiconductor device for a charge pump device suitable for providing large current capacity and preventing a latch up from occurring is offered. An N-type epitaxial silicon layer is formed on a P-type single crystalline silicon substrate, and a P-type well region is formed in the N-type epitaxial silicon layer. A P+-type buried layer abutting on a bottom of the P-type well region and an N+-type buried layer partially overlapping with the P+-type buried layer and electrically isolating the P-type well region from the single crystalline silicon substrate are formed. And then, an MOS transistor is formed in the P-type well region.Type: ApplicationFiled: December 26, 2002Publication date: August 7, 2003Inventors: Satoru Kaneko, Toshiyuki Ohkoda, Takao Myono
-
Publication number: 20030146477Abstract: Complementary bipolar transistors are fabricated on a semiconductor wafer by forming, on an upper surface of the semiconductor wafer, a first electrode corresponding to a first transistor, and a second electrode corresponding to a second transistor which is complementary to the first transistor. A first impurity is selectively introduced into the first and second electrodes. Then, a third electrode corresponding to the first transistor if formed, the third electrode being self-aligned with and electrically isolated from the first electrode, and a fourth electrode is formed corresponding to the second transistor, the fourth electrode being self-aligned with and electrically isolated from the second electrode. A second impurity is selectively introduced into the third and fourth electrodes.Type: ApplicationFiled: February 1, 2002Publication date: August 7, 2003Inventor: Thomas J. Krutsick
-
Publication number: 20030146478Abstract: A MOS device with dual gate insulators has a first gate insulator formed on a predetermined area of a semiconductor substrate, and a second gate insulator formed outside the predetermined area of the semiconductor substrate to surround the first gate insulator. The second gate insulator is thicker than the first gate insulator. In addition, a gate electrode layer is patterned on the dual gate insulators. The bottom center of the gate electrode layer covers the first gate insulator, and the bottom edge of the gate electrode layer extends to cover the second gate insulator.Type: ApplicationFiled: March 7, 2003Publication date: August 7, 2003Applicant: SILICON INTEGRATED SYSTEMS CORP.Inventors: Wen Ping Yen, Yun Hsiu Chen, Hung-Cheng Weng
-
Publication number: 20030146479Abstract: An insulated gate field effect transistor (FET) of a particular conductivity type, has as a gate electrode, a non-semiconductive material with a work function that approximates the work function of a semiconductive material that is doped to be of the same conductivity type.Type: ApplicationFiled: November 20, 2002Publication date: August 7, 2003Applicant: Intel CorporationInventors: John P. Barnak, Robert S. Chau, Chunlin Liang
-
Publication number: 20030146480Abstract: A metal gate MISFET comprises a metal gate electrode on a semiconductor substrate, a side wall insulation film, and a source-drain region which is formed on the surface of the semiconductor substrate on both sides of the side wall insulation film. Then, a cobalt silicide film is formed on the source-drain region. In this step of manufacturing the MISFET, since the cobalt silicide film is sealed with the silicon nitride film at the time of oxidizing the surface of the substrate of a gate portion, the property of the cobalt silicide film will never be deteriorated. As a consequence, the metal-gate field effect transistor having a low parasitic resistance of the source-drain region can be obtained.Type: ApplicationFiled: February 10, 2003Publication date: August 7, 2003Applicant: NEC CORPORATIONInventor: Hitoshi Abiko
-
Publication number: 20030146481Abstract: An object of the invention is to achieve a wider passband and reduction in size of a surface acoustic wave device.Type: ApplicationFiled: January 14, 2003Publication date: August 7, 2003Inventors: Kenji Inoue, Katsuo Sato, Hiroki Morikoshi, Jun Sato
-
Publication number: 20030146482Abstract: Compositions and methods are provided whereby printed wiring boards may be produced that comprise a) a substrate layer, and b) a solid, substantially planar optical wave-guide laminated onto the substrate layer. The printed wiring board further comprises at least one of a laminating material or a cladding material coupled to the wave-guide, and at least one additional layer coupled to the laminating material or the cladding material.Type: ApplicationFiled: December 19, 2002Publication date: August 7, 2003Inventor: Yutaka Doi
-
Publication number: 20030146483Abstract: A metal pad of a semiconductor element is disposed in an opening of a passivation layer of the semiconductor element and is connected to a metal interconnect layer of the semiconductor element through a plurality of metal plugs. The metal pad comprises a first aluminum alloy layer, a laser stop layer and a second aluminum alloy layer. The first aluminum alloy layer is disposed above the metal plugs; the laser stop layer is disposed on the upper surface of the first aluminum alloy layer and is made of a metal having a high melting point and a high laser reflection coefficient and has a thickness between 500 Å and 5000 Å; and the second aluminum alloy layer is disposed on the upper surface of the laser stop layer and has a thickness between 1000 Åand 20000 Å.Type: ApplicationFiled: January 15, 2003Publication date: August 7, 2003Applicant: VIA Technologies, Inc.Inventor: Ray Chien
-
Publication number: 20030146484Abstract: An SiGe device configured to exhibit high velocity saturation resistance characteristic for buffering large voltages at low currents, wherein for circuit applications, the SiGe device is connected in series with a circuit element for protection of the circuit element. Advantageously, the device may be exploited as a buffer element providing ESD circuit protection for receiver devices, power supply clamp circuits and I/O driver circuits.Type: ApplicationFiled: January 28, 2003Publication date: August 7, 2003Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventor: Steven Howard Voldman
-
Publication number: 20030146485Abstract: A method of manufacturing a compound layer, containing a nitrified metal as a major component thereof and having a predetermined microstructure pattern, includes: an ion implantation step for implanting hydrogen ions into a predetermined region of a compound layer formed on a substrate to form an implanted region; and an etching step for selectively etching the implanted region by using a gas containing at least oxygen, to remove the implanted region of the compound layer while maintaining the other region as a microstructure pattern. By introducing a halogen element like fluorine in addition to hydrogen, fabrication of the pattern can be executed more reliably and more easily. As a result, volatility of reaction products produced upon etching the compound layer is enhanced, and micro-loading effects are suppressed.Type: ApplicationFiled: January 15, 2003Publication date: August 7, 2003Applicant: KABUSHIKI KAISHA TOSHIBAInventor: Mizunori Ezaki
-
Publication number: 20030146486Abstract: In the semiconductor device according to the present invention having a plurality of function macro formation regions on the principal face of a semiconductor substrate, the plurality of the function macro formation regions include at least a first function macro formation region where a first function macro is formed and a second function macro formation region where a second function macro different from the first function macro is formed, each function macro formation region has an element formation region where an element is formed, a plurality of dummy semiconductor regions where no element is formed and isolation trenches filled with a predetermined insulating material mutually isolating between the plurality of dummy semiconductor regions, and the dummy semiconductor region in one function macro formation region has mutually identical plane shape and identical area and the area of the first dummy semiconductor region included in the first function macro formation region and the area of the second dummyType: ApplicationFiled: February 3, 2003Publication date: August 7, 2003Applicant: NEC Electronics CorporationInventor: Masahiro Ikeda
-
Publication number: 20030146487Abstract: A semiconductor device of the present invention comprises: an epitaxial layer formed on a P type silicon substrate; a P+ diffusion layer for dividing the epitaxial layer into an N− epi layer, which constitutes a device formation region, and an N− epi layer, which constitutes an invalid area; and an aluminum wire for electrically connecting the N− epi layer (invalid area) to the P+ diffusion layer. Since the potential of the N− epi layer (invalid area) can be made equal to that of the P+ diffusion layer, it is possible to prevent the electron supply from the P+ diffusion layer to the invalid area even when electrons are supplied to the device formation region by a counterelectromotive force produced by a load having an inductance L.Type: ApplicationFiled: July 10, 2002Publication date: August 7, 2003Inventors: Keiichi Furuya, Fumitoshi Yamamoto, Tomohide Terashima
-
Publication number: 20030146488Abstract: A semiconductor device includes a first semiconductor region having a buried oxide layer formed therein, a second semiconductor region in which the buried oxide layer does not exist, a trench formed to such a depth as to reach at least the buried oxide layer in a boundary portion between the first and second semiconductor regions, and an isolation insulating layer buried in the trench.Type: ApplicationFiled: February 10, 2003Publication date: August 7, 2003Inventors: Hajime Nagano, Takashi Yamada, Tsutomu Sato, Ichiro Mizushima, Osamu Fujii
-
Publication number: 20030146489Abstract: A semiconductor device provided with an isolation oxide film formed by a trench isolation technique is described. The device prevents the development of crystal defects from the corners of a trench and secures stable operating characteristics. The semiconductor device is provided with an isolation oxide film formed so that boundaries between an active region and the isolation oxide film extend in a direction inclined at an angle in the range of 45°±10° to the cleavage plane of a silicon substrate. The isolation oxide film has a interior wall oxide film of a thickness in the range of 50 Å to 1000 Å coating the side walls and the bottom wall of a trench, and a filling oxide film filling up the trench coated with the interior wall oxide film. The edges of the active region contiguous to the isolation oxide film are rounded properly.Type: ApplicationFiled: February 14, 2003Publication date: August 7, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Satoshi Shimizu
-
Publication number: 20030146490Abstract: A semiconductor device (2) includes a semiconductor substrate (12) having a surface (13) formed with a first recessed region (20). A first dielectric material (60) is deposited in the first recessed region and formed with a second recessed region (76), and a second dielectric material (100) is grown over the first dielectric material to seal the second recessed region.Type: ApplicationFiled: February 7, 2002Publication date: August 7, 2003Applicant: Semiconductor Components Industries, LLC.Inventors: Guy E. Averett, Keith G. Kamekona, Chandrasekhara Sudhama, Weizhong Cai, Gordon L. Bratten, Bladimiro Ruiz
-
Publication number: 20030146491Abstract: A semiconductor integrated circuit device has: a layer insulating film formed on a semiconductor substrate; a fuse portion which is configured by an uppermost metal wiring layer that is formed on the layer insulating film; an inorganic insulating protective film which is formed on the metal wiring layer and the layer insulating film; and an organic insulating protective film which is formed on the inorganic insulating protective film. An opening is formed in the organic insulating protective film so that the inorganic insulating protective on the fuse portion is exposed. According to this configuration, it is not required to etch away the layer insulating film in order to form an opening above the fuse portion. Therefore, the time period required for forming the opening can be shortened and the whole production time period can be shortened.Type: ApplicationFiled: February 21, 2003Publication date: August 7, 2003Inventor: Katsuhiko Tsuura
-
Publication number: 20030146492Abstract: A multilayer semiconductor device that includes a metal-insulator-metal (MIM) capacitor including a first metal plate, a dielectric layer, and a second metal plate, a nitride etchstop layer formed above the MIM capacitor, a first interlayer dielectric formed on the nitride etchstop layer, and a first via and a second via that extend through at least the first interlayer dielectric to contact the nitride etchstop layer.Type: ApplicationFiled: November 25, 2002Publication date: August 7, 2003Applicant: International Business Machines CorporationInventors: John Chester Malinowski, Matthew David Moon, Vidhya Ramachandran, Kimball M. Watson
-
Publication number: 20030146493Abstract: A semiconductor device has a first IGBT (1) for controlling a principal current and a second IGBT (2) for preventing an over-current of the first IGBT (1). A diode portion (11) is disposed between the emitter (5) of the first IGBT (1) and the emitter (6) of the second IGBT (2) so as to be in parallel with a sensing resistor (8). The diode portion (11) is composed of a first diode (9) and a second diode (10), which are connected in reverse series to each other. In order to prevent the over-current of the first IGBT (1) and the destruction of the second IGBT (2), each of the diodes (9, 10) has a breakdown voltage in the reverse voltage direction, which is lower than the endurance voltage between the emitters (5, 6) and is higher than the upper limit of the voltage sensed by the sensing resistor (8).Type: ApplicationFiled: August 12, 2002Publication date: August 7, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventor: Yoshifumi Tomomatsu
-
Publication number: 20030146494Abstract: A method for fabricating a semiconducting device on a substrate, where the improvement includes forming a strained silicon germanium channel layer on the substrate. A gate insulation layer is formed on top of the strained silicon germanium channel layer, at a temperature that does not exceed about eight hundred centigrade. A gate electrode is formed on top of the gate insulation layer, and the gate electrode is patterned. A low dose drain dopant is impregnated into the substrate, and activated with a first laser anneal. A source-drain dopant is impregnated into the substrate, and activated with a second laser anneal. After the step of activating the low dose drain dopant with the first laser anneal, an insulating layer is formed around the gate electrode, at a temperature that does not exceed about eight hundred centigrade, and a spacer is formed around the gate electrode. The spacer is formed of a material that is reflective to the second laser anneal.Type: ApplicationFiled: February 18, 2003Publication date: August 7, 2003Applicant: LSI Logic CorporationInventors: Helmut Puchner, Gary K. Giust
-
Publication number: 20030146495Abstract: A semiconductor device of this invention includes a first interconnect pattern formed on a semiconductor substrate and a second interconnect pattern formed above the first interconnect pattern with an interlayer insulating film sandwiched therebetween. The first interconnect pattern includes a dummy pattern insulated from the first interconnect pattern, and the dummy pattern includes a plurality of fine patterns adjacent to each other and air gaps formed between the adjacent fine patterns.Type: ApplicationFiled: March 10, 2003Publication date: August 7, 2003Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Eiji Tamaoka, Hideo Nakagawa
-
Publication number: 20030146496Abstract: A method of manufacturing a semiconductor device including the steps of: (a) forming an interlayer insulating film over a semiconductor substrate; (b) forming a first mask on the interlayer insulating film, the first mask having a plurality of stripe patterns parallel to a first direction, and etching the interlayer insulating film from a surface thereof to a first intermediate depth to form a groove; and (c) forming a second mask on the interlayer insulating film, the second mask having a plurality of stripe patterns parallel to a second direction crossing the first direction, and etching the interlayer insulating film by a remaining thickness thereof in an area corresponding to the groove and not covered with the second mask to form an opening, and in an area other than the area corresponding to the groove to form a second groove reaching a second intermediate depth from a surface of the interlayer insulating film.Type: ApplicationFiled: March 3, 2003Publication date: August 7, 2003Applicant: FUJITSU, LTD.Inventor: Shunji Nakamura
-
Publication number: 20030146497Abstract: A leadframe for use with integrated circuit chips comprising a base metal having a plated layer of nickel fully covering said base metal; a plated layer of pure tin on said nickel layer, selectively covering areas of said leadframe intended for attachment to other parts; and a plated layer of palladium on said nickel layer, selectively covering areas of said leadframe intended for bonding wire attachment.Type: ApplicationFiled: February 1, 2002Publication date: August 7, 2003Inventors: Donald C. Abbott, Douglas W. Romm
-
Publication number: 20030146498Abstract: It is an object of the present invention to provide a composite material having low thermal expansivity, high thermal conductivity, and good plastic workability, which is applied to semiconductor devices and many other uses.Type: ApplicationFiled: February 12, 2003Publication date: August 7, 2003Inventors: Yasuo Kondo, Junya Kaneda, Tasuhisa Aono, Teruyoshi Abe, Masahisa Inagaki, Ryuichi Saito, Yoshihiko Koike, Hideo Arakawa
-
Publication number: 20030146499Abstract: It is an object of the present invention to provide a composite material having low thermal expansivity, high thermal conductivity, and good plastic workability, which is applied to semiconductor devices and many other uses.Type: ApplicationFiled: February 12, 2003Publication date: August 7, 2003Inventors: Yasuo Kondo, Junya Kaneda, Tasuhisa Aono, Teruyoshi Abe, Masahisa Inagaki, Ryuichi Saito, Yoshihiko Koike, Hideo Arakawa
-
Publication number: 20030146500Abstract: A package for a semiconductor device, comprising a leadframe on which at least one semiconductor chip is arranged, the semiconductor chip being connected to the leadframe by conducting leads and at least one ground lead; the ground lead is connected between the top of the semiconductor chip and a recessed region of the leadframe.Type: ApplicationFiled: February 4, 2002Publication date: August 7, 2003Applicant: STMicroelectronics S.R.L.Inventors: Battista Vitali, Roberto Tiziani, Loic Renard
-
Publication number: 20030146501Abstract: In a semiconductor device, a lead frame is adhered to a base substrate for heat dissipation via an insulating layer, and an outward guided terminal portion is formed by perpendicularly upwardly bending an end of the lead frame after the mounting of one or more of power semiconductor elements on the lead frame. A recessed portion is formed beforehand in a portion of the lead frame to be bent, and it is ensured that the lead frame does not adhere to the surface of the base substrate in this recessed portion when the lead frame is adhered to the base substrate via the insulating layer before the bending of the lead frame. By virtue of this structure, manufacturing is simplified and manufacturing costs are reduced.Type: ApplicationFiled: March 11, 2003Publication date: August 7, 2003Inventors: Yasushi Sasaki, Shogo Tani, Yoshihiro Uchino, Kiyotaka Tomiyama, Yutaka Maeno
-
Publication number: 20030146502Abstract: A high temperature hybrid-circuit structure includes a temperature sensitive device which comprises SiC, AlN and/or AlxGa1−xN(x>0.69) connected by electrodes to an electrically conductive mounting layer that is physically bonded to an AlN die. The die, temperature sensitive device and mounting layer (which can be W, WC or W2C) have temperature coefficients of expansion within 1.06 of each other. The mounting layer can consist entirely of a W, WC or W2C adhesive layer, or an adhesive layer with an overlay metallization having a thermal coefficient of expansion not greater than about 3.5 times that of the adhesive layer. The device can be encapsulated with a reacted borosilicate mixture, with or without an upper die which helps to hold on lead wires and increases structural integrity. Applications include temperature sensors, pressure sensors, chemical sensors, and high temperature and high power electronic circuits.Type: ApplicationFiled: June 20, 2002Publication date: August 7, 2003Applicant: HetronInventor: James D. Parsons
-
Publication number: 20030146503Abstract: Electrically, thermally and mechanically enhanced ball grid array (BGA) packages are described. An IC die is mounted on a first surface of a stiffener. A first surface of a substrate is attached to a second surface of the stiffener that is opposed to the first surface of the stiffener. A bond pad of the IC die is coupled to a contact pad on the first surface of the substrate with a wire bond. The wire bond is coupled over a recessed step region in the first surface of the stiffener and through a through-pattern in the stiffener that has an edge adjacent to the recessed step region. The through-pattern in the stiffener is one of an opening through the stiffener, a recessed portion in an edge of the stiffener, or other through-pattern.Type: ApplicationFiled: October 31, 2002Publication date: August 7, 2003Applicant: Broadcom CorporationInventors: Reza-ur Rahman Khan, Sam Ziqun Zhao
-
Publication number: 20030146504Abstract: A chip-size semiconductor package includes a semiconductor chip; a metal pad formed on the semiconductor chip; a wafer coat formed over the semiconductor chip; a conductive wiring pattern formed on the wafer coat, in which the metal pad is electrically connected to the conductive pattern; a molding resin formed over the conductive wiring pattern; a conductive post which is formed in the molding resin and is connected to the conductive wiring pattern; and a terminal which is formed on the molding resin and is connected to the conductive post. A connecting portion (boundary portion) of the conductive wiring pattern and conductive post is provided with a slit to disperse stress to be applied to the connecting portion.Type: ApplicationFiled: February 5, 2002Publication date: August 7, 2003Inventor: Tae Yamane
-
Publication number: 20030146505Abstract: Electronic contacts, including spherical cores and attachment layers on the cores, are provided for attaching a semiconductor package substrate to a printed circuit board. The spherical cores are made of high-melting-temperature copper, and the attachment layers are made of a low-melting-temperature eutectic. The attachment layers melt in a reflow process. The spherical cores do not melt, and thereby control movement or “collapsing” of the package substrate toward the printed circuit board.Type: ApplicationFiled: February 4, 2002Publication date: August 7, 2003Inventors: Edward L. Martin, L. Todd Biggs
-
Publication number: 20030146506Abstract: A system and method of assembling a ball grid array (BGA) package with IC die support is described. A stiffener is attached to a substrate that includes a centrally located opening with an integrated circuit (IC) die support structure removably held therein. An IC die is mounted to a central region of the stiffener. Further assembly process steps may be performed on the BGA package with IC die support. The IC die support structure is removed from the centrally located opening. In aspects of the invention, the IC die support structure is removably held in the opening by an adhesive tape or by one or more substrate tabs.Type: ApplicationFiled: October 31, 2002Publication date: August 7, 2003Applicant: Broadcom CorporationInventors: Reza-ur Rahman Khan, Sam Ziqun Zhao
-
Publication number: 20030146507Abstract: A thermally-enhanced ball grid array package structure is provided that includes an integrated circuit chip, a heat spreader and a substrate. The integrated circuit chip has a specified surface area. The heat spreader is coupled to the integrated circuit chip. The substrate is coupled to the heat spreader. The substrate has a specified surface area. The heat spreader covers a specified portion of the surface area of the substrate that is greater than the surface area of the integrated circuit chip. The heat spreader is operable to dissipate heat from the integrated circuit chip over the specified portion of the surface area of the substrate.Type: ApplicationFiled: February 1, 2002Publication date: August 7, 2003Applicant: STMicroelectronics, Inc.Inventors: Tiao Zhou, Michael J. Hundt
-
Publication number: 20030146508Abstract: A cavity-down ball grid array package includes a substrate having a through cavity provided therein. A heat sink is attached to the substrate and a semiconductor chip in the cavity is attached to the heat sink and electrically connected to the substrate. A ball grid array is on the substrate and on the semiconductor chip.Type: ApplicationFiled: June 14, 2002Publication date: August 7, 2003Inventors: Eing-Chieh Chen, Shiu-Tai Tzung, Ting-Ke Chai, Jeng-Yuan Lai, Candy Tien
-
Publication number: 20030146509Abstract: In a ball grid array (BGA) package, a first stiffener is attached to a surface of a substrate. A second stiffener is attached to the surface of the substrate to be co-planar with the first stiffener. The second stiffener is separated from the first stiffener by a channel therebetween. An integrated circuit (IC) die is mounted to a surface of the second stiffener.Type: ApplicationFiled: October 31, 2002Publication date: August 7, 2003Applicant: Broadcom CorporationInventors: Sam Ziqun Zhao, Reza-Ur Rahman Khan
-
Publication number: 20030146510Abstract: An elastomer interposer employed between a package and a printed circuit board and the method of manufacturing the same are disclosed. The elastomer interposer includes an elastomer, a plurality of conductive wires, Cu pads, solder resistant blocks and Ni/Au plated pads. The elastomer has two contact surfaces. The conductive wires are arranged inside the elastomer at a certain interval and tilted toward one of the contact surfaces with an inclined angle. The Cu pads are formed on both of the surfaces at a space, and electrically connected to the corresponding conductive wires. Also, the Ni/Au plated pads are formed over the Cu pads.Type: ApplicationFiled: November 14, 2002Publication date: August 7, 2003Inventor: Ray Chien
-
Publication number: 20030146511Abstract: Electrically, thermally and mechanically enhanced ball grid array (BGA) packages are described. An IC die is mounted to a first surface of a first stiffener. A peripheral edge portion of a second surface of the first stiffener is attached to a first surface of a second stiffener to cover an opening through the second stiffener that is open at the first surface and a second surface of the second stiffener. The second surface of the second stiffener is attached to a first surface of a substantially planar substrate that has a plurality of contact pads on the first surface of the substrate. The plurality of contact pads are electrically connected through the substrate to a plurality of solder ball pads on a second surface of the substrate.Type: ApplicationFiled: October 31, 2002Publication date: August 7, 2003Applicant: Broadcom CorporationInventors: Sam Ziqun Zhao, Reza-Ur Rahman Khan
-
Publication number: 20030146512Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A device dielectric layer is formed on the semiconductor substrate. A channel dielectric layer on the device dielectric layer has an opening formed therein. A barrier layer lines the channel opening. A conductor core fills the opening over the barrier layer. By using a polishing solution having a high selectivity from the conductor core to the barrier layer in conjunction with a grooved polyurethane polish pad, a very thin barrier layer may be used without the conductor core and dielectric layer being subject to erosion and the conductor core being subject to dishing.Type: ApplicationFiled: February 26, 2003Publication date: August 7, 2003Inventors: Kai Yang, Kashmir S. Sahota, Steven C. Avanzino
-
Publication number: 20030146513Abstract: A method used during the manufacture of a semiconductor device comprises providing at least first, second, and third spaced conductive structures, where the second conductive structure is interposed between the first and third conductive structures. A first dielectric is formed over these conductive structures, then a portion of the first dielectric layer is removed which forms a hole in the dielectric layer to expose the second conductive structure. Subsequently, the second conductive structure is removed to leave a void or tunnel in the dielectric layer where the second conductive structure had previously existed. Finally, a second dielectric layer is provided to fill the hole but to leave the void or tunnel in the dielectric layer subsequent to the formation of the second dielectric layer. An inventive structure resulting from the inventive method is also described.Type: ApplicationFiled: February 7, 2002Publication date: August 7, 2003Inventor: Philip J. Ireland
-
Publication number: 20030146514Abstract: An uppermost interlayer isolation film is provided on a semiconductor substrate. An uppermost wire is provided on the uppermost interlayer isolation film. A silicon oxide film is provided to cover the upper surface and the side wall of the uppermost wire. A nitride film is provided on the uppermost interlayer isolation film to cover the uppermost wire through the silicon oxide film. A polyimide film is provided on the nitride film. A portion of the uppermost interlayer isolation film other than a portion located under the uppermost wire is downwardly scooped. The nitride film covers the scooped portion of the uppermost interlayer isolation film. According to the present invention, a semiconductor device improved to be capable of improving coverage of a silicon nitride passivation film is obtained.Type: ApplicationFiled: July 25, 2002Publication date: August 7, 2003Applicant: Mitsubishi Denki Kabushiki Kaisha and Ryoden Semiconductor System Engineering CorporationInventors: Shinya Nakatani, Heiji Kobayashi
-
Publication number: 20030146515Abstract: A semiconductor device includes a first wiring line having a first through hole, and a first connection member which extends through the first through hole at an interval from the first wiring line.Type: ApplicationFiled: February 4, 2003Publication date: August 7, 2003Inventor: Takeshi Kajiyama
-
Publication number: 20030146516Abstract: A semiconductor device including an interconnection structure having superior electrical characteristics and allowing higher speed of operation and lower power consumption even when miniaturized, manufacturing method thereof and a method of designing a semiconductor circuit used in the manufacturing method are provided. In the semiconductor device, a conductive region is formed on a main surface of a semiconductor substrate. A first interconnection layer is electrically connected to the conductive region, has a relatively short line length, and contains a material having relatively high electrical resistance. A first insulator is formed to surround the first interconnection layer and has a relatively low dielectric constant. A second interconnection layer is formed on the main surface of the semiconductor substrate, contains a material having low electrical resistance than the material contained in the first interconnection layer, and has longer line length than the first interconnection layer.Type: ApplicationFiled: March 7, 2003Publication date: August 7, 2003Applicant: MITSUBISHI DENKI KABUSHIKI KAISHAInventors: Hiroyuki Amishiro, Motoshige Igarashi
-
Publication number: 20030146517Abstract: A chip-on-chip module and associated method of formation. First and second semiconductor chips are coupled together. The first chip comprises a first wiring layer and a first electrically conductive substrate on first and second sides, respectively, of the first chip. A supply voltage VDD is adapted to be electrically coupled to the second side of the first chip. The second chip comprises a second wiring layer and a second electrically conductive substrate on first and second sides, respectively, of the second chip. A ground voltage GND is adapted to be electrically coupled to the second side of the second chip. The first side of the first chip is electrically coupled to the first side of the second chip. The supply voltage VDD and the ground voltage GND are adapted to provide power to the first and second chips.Type: ApplicationFiled: February 6, 2002Publication date: August 7, 2003Applicant: International Business Machines CorporationInventors: Jerome B. Lasky, Edward J. Nowak, Edmund J. Sprogis