Abstract: A phase-change memory cell may be formed by selectively depositing the lower electrode in the phase-change memory pore. Thereafter, an adhesion-promoting material may be selectively deposited on the selectively deposited lower electrode and the upper surface surrounding the pore. Through the use of selective deposition techniques, the adhesion-promoting material can be positioned where needed and the lower electrode may be defined in a fashion that may reduce shunting current, reduce device current requirements, and increase dynamic range in some embodiments.

Abstract: A novel tunnel structure is described that enables tunnel diode behavior to be exhibited even in material systems in which extremely heavy doping is impossible and only moderate or light doping levels may be achieved. In one aspect, the tunnel heterostructure includes a first semiconductor layer, a second semiconductor layer, and an intermediate semiconductor layer that is sandwiched between the first and second semiconductor layers and forms first and second heterointerfaces respectively therewith. The first and second heterointerfaces are characterized by respective polarization charge regions that produce a polarization field across the intermediate semiconductor layer that promotes charge carrier tunneling through the intermediate semiconductor layer. In another aspect, the invention features a semiconductor structure having a p-type region, and the above-described heterostructure disposed as a tunnel contact between the p-type region of the semiconductor structure and an adjacent n-type region.

Abstract: A semiconductor laser device has an n-type AlGaAs first cladding layer 2, a multiple quantum well active layer 3, and a p-type AlGaAs second cladding layer 4 formed in this order and supported by an n-type GaAs substrate 1. The multiple quantum well active layer 3 has two quantum well layers 3a and barrier layers 3b provided on both sides of each quantum well layer 3a. The quantum well layers 3a are each made of In1−v1Gav1As1−w1Pw1, while the barrier layers 3b are each made of In1−v2Gav2As1−w2Pw2. Here, v1 and v2 satisfy v1<v2, while w1 and w2 satisfy w1<w2. The barrier layers have a tensile strain with respect to the GaAs substrate, while the well layers have a compressive strain with respect to the GaAs substrate.

Abstract: A light emitting device includes an active layer, having a multiple quantum well structure, sandwiched between an n-type semiconductor layer and a p-type semiconductor layer. The active layer includes first and second well layers made of a nitride compound semiconductor containing In, where the second well layer emits light having a main peak wavelength which is longer than that of the first well layer. The active layer also includes an intervening barrier layer disposed between the first and second well layers, and first and second barrier layers. The first well layer isg sandwiched between the first barrier layer and the intervening barrier layer, and the second well layer is sandwiched between the second barrier layer and the intervening barrier layer. A thickness of said first barrier layer is different than a thickness of said second barrier layer.

Abstract: A superjunction device has a plurality of equally spaced P columns in an N− epitaxial layer. The concentration of the P type columns is made greater than that needed for maintaining charge balance in the N− epi region and the P columns thereby to increase avalanche energy. An implant dose of 1.1E13 or greater is used to form the P columns.

Abstract: Test probe pads are located lateral to, and spaced from, the emitter, base or collector region of a bipolar transistor, preferably on separate pedestals, and connected to their respective transistor regions by air bridges. The probe pads, transistor contacts and air bridges are preferably formed as common metallizations. In the case of an HBT, a gap in the subcollector below the air bridges insulates the test transistor from capacitor loading by the probe pads. The test transistors can be used to characterize both themselves and functional circuit transistors fabricated with the same process on the same wafer by testing at an intermediate stage of manufacture, thus allowing wafers to be discarded without completing the manufacture if their transistors do not meet specifications.

Abstract: A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.

Abstract: The invention includes a method of forming semiconductor circuitry. A monocrystalline silicon substrate is provided, and a mask is formed which covers a first portion of the substrate and leaves a second portion uncovered. A trench is formed in the uncovered portion and at least partially filled with a semiconductive material that comprises at least one atomic percent of an element other than silicon. The mask is removed and a first semiconductor circuit component is formed over the first portion of the substrate. Also, a second semiconductor circuit component is formed over the semiconductive material that at least partially fills the trench. The invention also includes semiconductor constructions.

Abstract: A polysilicon film is formed in a predetermined region on a glass substrate, and then a gate insulating film and a gate electrode, whose width is narrower than the gate insulating film, are formed thereon. Then, an interlayer insulating film and an ITO film are formed on an overall surface. Then, n-type source/drain regions having an LDD structure are formed by implanting the n-type impurity into the polysilicon film. Then, an n-type TFT forming region and a pixel-electrode forming region are covered with a resist film, and then p-type source/drain regions are formed by implanting the p-type impurity into the polysilicon film in a p-type TFT forming region. Then, the resist film is left only in the pixel-electrode forming region and the resist film is removed from other regions. A pixel electrode is formed by etching the ITO film while using the remaining resist film as a mask.

Abstract: A method of using a pinned photodiode pixel for high-speed motion-capture CMOS image sensors uses a pinned photodiode in a five-transistor pixel so that the channel region of the photodiode is completely voided of charge after reset and readout operations. An exemplary method includes applying an exposure control clock signal to a gate electrode of an exposure control transistor of a five-transistor pixel, applying a pixel preset voltage to a drain of the exposure control transistor, and switching the exposure control clock signal. The exposure control transistor is coupled between a pinned photodiode of the pixel and the pixel preset voltage. The switching the exposure control clock signal turns off the exposure control transistor at a beginning of an integration cycle after substantially all signal charge has drained out of the pinned photodiode and across the exposure control transistor so that the pinned photodiode is fully voided of majority carriers.

Abstract: The present invention discloses and claims the silicon carbide based silicon structure comprising: (1) a silicon carbide substrate, (2) a silicon semiconductor material having a top surface, and either bonded to the silicon carbide substrate via the bonding layer, or epitaxially grown on the silicon carbide substrate; and (3) at least one separation plug formed in the silicon semiconductor material. The separation plug extends from the top surface of the silicon semiconductor material into the silicon carbide substrate at a separation plug depth level, and is configured to block the coupling between at least two adjacent active/passive structures formed in the silicon semiconductor material.

Abstract: A semiconductor light receiving element has an n electrode, an n-type semiconductor doped layer or a non-doped layer provided above the n electrode, a semiconductor light absorbing layer provided above the n-type semiconductor doped layer or the non-doped layer, a p-type semiconductor doped layer provided above the semiconductor light absorbing layer, and a p electrode provided above the p-type semiconductor doped layer. The semiconductor light absorbing layer has at least two layer portions doped to p-type, and a spacer layer for acceleration which is formed from a semiconductor material sandwiched by the two layer portions and which makes electrons and positive holes generated by incident light being absorbed at the semiconductor light absorbing layer accelerate and run.

Abstract: A set (50) of laser pulses (52) is employed to sever a conductive link (22) in a memory or other IC chip. The duration of the set (50) is preferably shorter than 1,000 ns; and the pulse width of each laser pulse (52) within the set (50) is preferably within a range of about 0.1 ps to 30 ns. The set (50) can be treated as a single “pulse” by conventional laser positioning systems (62) to perform on-the-fly link removal without stopping whenever the laser system (60) fires a set (50) of laser pulses (52) at each link (22). Conventional IR wavelengths or their harmonics can be employed.

Abstract: The present invention provides a method for automatically defining a part model for a semiconductor component. An image of the component is provided. The automatic method may be any of a trial and error method, systematic method or a method based on distance-angle signatures. The trial and error method is described in the context of defining a part model for a ball grid array. The systematic approach is described in the context of a leaded semiconductor and the distance angle signature approach is described in the context of defining a part model for an odd form semiconductor component.

Abstract: A semiconductor device for supplying a signal to an electro-optical device which displays a two-dimensional image, includes first terminals which are formed along a first side of the semiconductor device in a longitudinal direction and have a length L1 in a direction intersecting the longitudinal direction at right angles; and second terminals which are formed along a second side intersecting the first side at right angles and have a length L2 which is greater than the length L1 in the longitudinal direction.

Abstract: It is considered that in the fabricating steps of a TFT substrate, a color filter layer is prepared at the same alignment accuracy. However, since the heat resistance temperature is about 200° C., it could not withstand the process temperature of about 450° C. in the TFT.

Abstract: A semiconductor light receiving element has a semiconductor portion. The semiconductor portion includes a substrate, a light detecting portion, and a filter portion. The substrate, the light detecting portion, and the filter portion are provided sequentially in a direction of a predetermined axis. The light detecting portion has a light absorbing layer including a III-V semiconductor layer, a window layer including a III-V semiconductor layer, and an anode semiconductor region. The light absorbing layer is an n or i conductivity type semiconductor layer. The light absorbing layer is provided between a III-V semiconductor layer and the window layer. The light detecting portion is provided on one face of the semiconductor substrate with the III-V semiconductor layer interposed therebetween. The filter portion includes InGaAsP semiconductor layers and III-V semiconductor layers.

Abstract: A process of forming separation grooves for separating a semiconductor wafer into individual light-emitting devices, a process for thinning the substrate, process for adhering the wafer to the adhesive sheet to expose a substrate surface on the reverse or backside of the wafer, a scribing process for forming split lines in the substrate for dividing the wafer into light-emitting devices, and a process of forming a mirror structure comprising a light transmission layer, a reflective layer, and a corrosion-resistant layer, which are laminated in sequence using sputtering or deposition processes. Because the light transmission layer is laminated on the adhesive sheet, gases normally volatilized from the adhesion materials are sealed and do not chemically combine with the metal being deposited as the reflective layer. As a result, reflectivity of the reflective layer can be maintained.

Abstract: A semiconductor laser element is fixed onto a submount by forming a metallic thin film at a region on a surface of a p-side electrode of the semiconductor laser element. A periphery of the thin metallic thin film is recessed from a periphery of the p-side electrode by a predetermined width. The metallic thin film is thermally processed together with the p-side electrode for increasing a size of the grains and connected through a solder layer to the submount. Parts of the p-side electrode and the submount, the metallic thin film and the solder layer include Au for improving a cushion function of the semiconductor laser device.

Abstract: A fuse (43) is formed overlying a passivation layer (35) and under a packaging material (55, 70). In one embodiment, a fuse (43) is blown before the packaging material (55, 70) is formed. In some embodiments, the fuse (43) may be formed of metal (47), a metal nitride (42) or a combination thereof.

Abstract: An insulating element insulates a contact area of an electronic component from other contact areas of the component. In order to ensure an assembly that is as trouble-free as possible as well as a trouble-free operation, the insulation element has at least on a first section, which is accommodated inside a contact recess of a contact during operation, is provided with an outer contour that enables an accommodation with the utmost smallest amount of play inside the contact recess.

Abstract: An apparatus detecting motion in image data by compressing and encoding and a method thereof. The motion detecting apparatus has a separation unit, an operation unit and a comparison unit. The separation unit separates a bit stream in relation to a motion predicted image from a compressed encoded image bit stream. The operation unit calculates an average value of the bit stream in relation to the motion predicted image separated at the separation unit. The comparison unit detects a motion when the average value is greater than a predetermined threshold after comparing the average value and the threshold. Thus, because a motion in an input image can be detected by using a compressed encoded image bit stream, a separate circuit or input image processing is not required to detect the motion and adverse affects of camera noise on the detection results can be reduced.

Abstract: To provide a semiconductor device which makes it possible to avoid deterioration in step coverage property at a gate electrode provided on an operating region, and decrease a leakage current between the operating region and the gate electrode. The semiconductor device arranged as a HEMT is made to include operating region composed of multilayer films such as a channel layer, an electron supplying layer and other semiconductor layer and having an island structure independently mesa-isolated from one another. The semiconductor device also includes a gate electrode and an impurity diffusion layer provided on the surface of the operating region, the impurity diffusion layer being doped with an impurity having a conductivity type inverse to the impurity doped into the electron supplying layer.

Abstract: An object of the present invention is to improve, in a group III nitride semiconductor device, the productivity, the heat diffusion characteristic and the device performance in high-speed operation, and, therefor, in a group III nitride semiconductor device of the present invention, an epitaxial growth layer 13 of a group III nitride semiconductor with a buffer layer 12 laid under it is formed on a sapphire substrate 11 in which an A plane (an (11-20) plane) is set to be the principal plane, and thereon a gate electrode 16, a source electrode 15 and a drain electrode 17 are formed, wherein a thickness of the single crystalline sapphire substrate is specifically set to be 100 &mgr;m or less.

Abstract: An AlN film as an underlayer is epitaxially grown on a substrate having a dislocation density of 1011/cm2 or below and a crystallinity of 90 seconds or below in full width at half maximum (FWHM) of an X-ray rocking curve at (002) reflection. Then, on the AlN film an n-GaN film is epitaxially grown as a conductive layer having a dislocation density of 1010/cm2 or below and a crystallinity of 150 seconds or below in full width at half maximum (FWHM) of an X-ray rocking curve at (002) reflection, to fabricate a semiconductor element.

Abstract: A thin InGaAs contact layer is provided for the collector of a heterojunction bipolar transistor (HBT) above an InP sub-collector. The contact layer provides a low resistance contact mechanism and a high thermal conductivity path for removing device heat though the sub-collector, and also serves as an etch stop to protect the sub-collector during device fabrication. A portion of the sub-collector lateral to the remainder of the HBT is rendered electrically insulative, preferably by an ion implant, to provide electrical isolation for the device and improve its planarity by avoiding etching through the sub-collector.

Abstract: The present invention prepares a member having a conductor-circuit-forming copper foil 21 formed on a protrusion-forming copper layer 23 via an etching-barrier layer 22 formed of a different metal. Etching is selectively performed for the protrusion-forming copper foil 21 by using etchant that does not etch the etching-barrier layer, and protrusions 25 are thereby formed. Then, the etching-barrier layer 22 is removed using etchant that does not etch the copper foil 23 and using the protrusions as masks. An interlayer-insulating layer 27 is formed on a surface of the copper foil 23, on which the protrusions 25 are formed, so that the protrusions are connected to the conductor circuit. Thereby, heights of the protrusions are uniformed, and the reliability of connections can be improved.

Abstract: A semiconductor memory includes a silicon substrate having a cell array region wherein plural rectangular silicon pillars are formed in rows and columns by a trench having a width of la and formed in a lattice form, a storage node formed on at least a surface of a lower portion of the silicon pillar, a well region formed in an upper half above the storage node, a diffusion layer formed on an upper surface of the well region, a capacitor dielectric formed on the storage node to surround the lower portion of the silicon pillar, a plate electrode buried in the lower portion of the trench to substantially the same level as the upper end of the storage node, and a first gate electrode formed on the channel portion via a first gate insulator.

Abstract: A semiconductor device comprises a memory cell array portion and peripheral circuit portion, wherein a first insulation film including elements as main components other than nitrogen fills between the memory cell gate electrodes of the memory cell array portion, the first insulation film is formed as a liner on a sidewall of a peripheral gate electrode of the peripheral circuit portion simultaneously with the memory cell portion, and a second insulation film including nitrogen as the main component is formed on the sidewall of the peripheral gate electrode via the first insulation film, thus enabling not only the formation of the memory cell portion having high reliability, but also the formation of a peripheral circuit with good efficiency, simultaneously, and avoiding gate offset of a peripheral gate.

Abstract: A rising time period detection circuit detects a rising time period between a power supply ON time or a reset time and a time when a boosted voltage HV reaches a standby voltage (5.0 V), and outputs a detection signal PWUP representing a result of the detection. An oscillation circuit generates and outputs a clock signal OSCK having a constant frequency Ha, which is lower than a frequency Hr in an ordinary state, while the detection signal PWUP is at a high level (in an active state). A charge pump circuit boosts a power source voltage Vdd in response to the input clock signal OSCK of the frequency Ha and causes the boosted voltage HV to gently rise from the power source voltage Vdd. This arrangement of the present invention desirably eliminates the effects of a parasitic capacitance at the power supply ON time or the reset time and thereby effectively interferes with an increase in reference voltage accompanied by the increase in boosted voltage HV.

Abstract: A memory system that includes a dynamic random access memory (DRAM) cell including an access transistor and a capacitor structure fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity in a shallow trench isolation region, thereby exposing a sidewall region of the substrate below the upper surface of the substrate. A dielectric layer is formed over the upper surface and the sidewall region of the substrate. A polysilicon layer is formed over the dielectric layer and patterned to form a capacitor electrode of the capacitor structure that extends over the upper surface and the sidewall region of the substrate. The capacitor electrode is partially recessed below the upper surface of the substrate. The polysilicon layer is also patterned to form the gate electrode of the access transistor.

Abstract: A memory system that includes a dynamic random access memory (DRAM) cell including an access transistor and a capacitor structure fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity in a shallow trench isolation region, thereby exposing a sidewall region of the substrate below the upper surface of the substrate. A dielectric layer is formed over the upper surface and the sidewall region of the substrate. A polysilicon layer is formed over the dielectric layer and patterned to form a capacitor electrode of the capacitor structure that extends over the upper surface and the sidewall region of the substrate. The capacitor electrode is partially recessed below the upper surface of the substrate. The polysilicon layer is also patterned to form the gate electrode of the access transistor.

Abstract: A method and structure for an improved DRAM (dynamic random access memory) dielectric structure, whereby a new high-k material is implemented for both the support devices used as the gate dielectric as well as the capacitor dielectric. The method forms both deep isolated trench regions used for capacitor devices, and shallow isolated trench regions for support devices. The method also forms two different insulator layers, where one insulator layer with a uniform high-k dielectric constant is used for the deep trench regions and the support regions. The other insulator layer is used in the array regions in between the shallow trench regions.

Abstract: Insulated gate field effect transistors having gate electrodes with at least two layers of materials provide gate electrode work function values that are similar to those of doped polysilicon, eliminate the poly depletion effect and also substantially prevent impurity diffusion into the gate dielectric. Bi-layer stacks of relatively thick Al and thin TiN for n-channel FETs and bi-layer stacks of relatively thick Pd and thin TiN, or relatively thick Pd and thin TaN for p-channel FETs are disclosed. Varying the thickness of the thin TiN or TaN layers between a first and second critical thickness may be used to modulate the work function of the gate electrode and thereby obtain the desired trade-off between channel doping and drive currents in FETs.

Abstract: A honeycomb CCD, whose light receiving portion and a certain light receiving portion 105 adjoining thereto are arranged at a position to be shifted by half a pixel pitch in line and row directions, has charge transfer electrodes 111-114 formed of double-layered polysilicon electrode, a metal wiring 125, having smaller resistivity thereto, which is arranged in the longitudinal direction along each VCCD to intersect and cross over the charge transfer electrodes 111-114 being connected by a contact hole 126, by which electrical resistance of the polysilicon layer of the charge transfer electrodes can be lowered without increasing thickness thereof.

Abstract: An image sensor having a photo diode with improved sensitivity, junction leakage and electron capacity, and a method for manufacturing the image sensor, are provided. The provided image sensor includes a semiconductor substrate and a p-type photo diode region formed on a selected region of the semiconductor substrate. A first n-type photo diode region is formed underneath the p-type photo diode region, contacting an interface of the p-type photo diode region, and a second n-type photo diode region is formed to surround the first n-type photo diode region. Here, impurities composing the first n-type photo diode region have smaller projection distance and diffusivity than impurities composing the second n-type photo diode region.

Abstract: A vertical double gate semiconductor device (10) having separate, non-contiguous gate electrode regions (62, 64) is described. The separate gate electrode regions can be formed by depositing a gate electrode material (28) and anisotropically etching, planarizing or etching back the gate electrode material to form the separate gate electrode regions on either side of the vertical double gate semiconductor device. One (66) or two (68, 70) contacts are formed over the separate gate electrode regions that may or may not be electrically isolated from each other. If formed from polysilicon, the separate gate electrode regions are doped. In one embodiment, the separate gate electrode regions are doped the same conductivity. In another embodiment, an asymmetrical semiconductor device is formed by doping one separate gate electrode region n-type and the other separate gate electrode region p-type.

Abstract: The ferroelectric film of the invention is made from a ferroelectric material represented by a general formula, Bi4−x+yAxTi3O12 or (Bi4−x+yAxTi3O12)z+(DBi2E2O9)1−z, wherein A is an element selected from the group consisting of La, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb, Lu and V; D is an element selected from the group consisting of Sr, Ba, Ca, Bi, Cd, Pb and La; E is an element selected from the group consisting of Ti, Ta, Hf, W, Nb, Zr and Cr; and 0≦x≦2, 0≦y≦(4−x)×0.1 and 0.5<z<1.

Abstract: A self-aligned magnetic clad bit line structure (274) for a magnetic memory element (240a) and its method of formation are disclosed, wherein the self-aligned magnetic clad bit line structure (274) extends within a trench (258) and includes a conductive material (264), magnetic cladding sidewalls (262) and a magnetic cladding cap (252). The magnetic cladding sidewalls (262) at least partially surround the conductive material (264) and the magnetic cladding cap (252) is substantially recessed within the trench with respect to the top of the trench.

Abstract: A method of forming FLASH memory circuitry having an array of memory cells and having FLASH memory peripheral circuitry operatively configured to at least read from the memory cells of the array, includes forming a plurality of spaced isolation trenches within a semiconductor substrate within a FLASH memory array area and within a FLASH, peripheral circuitry area peripheral to the memory array area. The forming includes forming at least some of the isolation trenches within the FLASH memory array to have maximum depths which are different within the substrate than that of at least some of the isolation trenches within the FLASH peripheral circuitry area.

Abstract: Fabrication of memory cell capacitors in an over/under configuration facilitates increased capacitance values for a given die area. A pair of memory cells sharing a bit-line contact include a first capacitor below the substrate surface. The pair of memory cells further include a second capacitor such that at least a portion of the second capacitor is underlying the first capacitor. Such memory cell capacitors can thus have increased surface area for a given capacitor height versus memory cell capacitors formed strictly laterally adjacent one another. The memory cell capacitors can be fabricated using silicon-on-insulator (SOI) techniques. The memory cell capacitors are useful for a variety of memory arrays, memory devices and electronic systems.

Abstract: A semiconductor memory device and manufacturing method, including a bit line connector and a lower electrode connector that respectively connect a bit line and a capacitor lower electrode of the device to active areas of a semiconductor substrate. The connectors are formed using a line-type self-aligned photoresist mask pattern positioned on an interlevel dielectric layer formed on the substrate, which exposes only a portion of the dielectric layer corresponding to a source region and which extends in a direction which a gate electrode extends, to provide a misalignment margin. The bit line connector and the lower electrode connector are respectively formed by one-time mask processes. A contact hole for the bit line connector in a cell area, and a contact hole for a metal wiring plug in a peripheral area are simultaneously formed, alleviating etching burden during subsequent forming of a metal wiring pad.

Abstract: The present invention relates to a structure of a capacitor, in particular using niobium pentoxide, of a semiconductor capacitor memory device. Since niobium pentoxide has a low crystallization temperature of 600° C. or less, niobium pentoxide can suppress the oxidation of a bottom electrode and a barrier metal by heat treatment. However, according to heat treatment at low temperature, carbon incorporated from CVD sources into the film is not easily oxidized or removed. Therefore, a problem that leakage current increases arises. As an insulator film of a capacitor, a layered film composed of a niobium pentoxide film and a tantalum pentoxide film, or a layered film composed of niobium pentoxide films is used. By the use of the niobium pentoxide film, the dielectric constant of the capacitor can be made high and the crystallization temperature can be made low. By multiple-stage formation of the dielectric film, leakage current can be decreased.

Abstract: This disclosure provides cells of nonvolatile memory devices with floating gates and methods for fabricating the same. The cell of the nonvolatile memory device includes device isolation layers in parallel with each other on a predetermined region of a semiconductor substrate that define a plurality of active regions. Each device isolation layer has sidewalls that project over the semiconductor substrate. A plurality of word lines crosses over the device isolation layers. A tunnel oxide layer, a floating gate, a gate interlayer dielectric layer, and a control gate electrode are sequentially stacked between each active region and each word line. The floating gate and the control gate electrode have sidewalls that are self-aligned to the adjacent device isolation layers.

Abstract: A semiconductor memory device of the present invention having sense amplifier transistors connected to complementary bit lines of a memory cell array and sense amplifier driver transistors driving the sense amplifier transistors, wherein the sense amplifier transistors and the sense amplifier driver transistors have gate electrodes dividing a common diffusion layer region formed on the surface of a semiconductor substrate into two, respectively, the gate electrodes being arranged on the boundary of the diffusion layer region.

Abstract: A semiconductor device is provided which includes a diode formed of a MISFET and having a current-voltage characteristic close to that of an ideal diode. Negatively charged particles (e.g. electrons: 8a) are trapped on the drain region (2) side of a silicon nitride film (4b) sandwiched between films of silicon oxide (4a, 4c). When a bias voltage is applied between the drain and source with the negatively charged particles (8a) thus trapped and in-channel charged particles (9a) induced by them, the MISFET exhibits different threshold values for channel formation depending on whether it is a forward bias or a reverse bias. That is to say, when a reverse bias is applied, the channel forms insufficiently and the source-drain current is less likely to flow, while the channel forms sufficiently and a large source-drain current flows when a forward bias is applied. This offers a current-voltage characteristic close to that of the ideal diode.

Abstract: A compensation component and a process for production thereof includes a semiconductor body having first and second electrodes, a drift zone disposed therebetween, and areas of a first conductivity type and a second conductivity type opposite the first conductivity type disposed in the drift zone. Higher doped zones of the first type are inlaid in a weaker doped environment of the second type closer to the first electrode and higher doped zones of the second type are inlaid in a weaker doped environment of the first type closer to the second electrode. The drift zone is complementary so that, in a direction between the electrodes, a more highly doped zone of the first type adjoins a more weakly doped environment of the first type, and a more weakly doped environment of the second type adjoins a more highly doped zone of the second type.

Abstract: Within both a lateral double diffused metal oxide semiconductor (LDMOS) device, and a method for fabrication thereof, there is formed a buried layer of polarity equivalent with a well region within which is formed a drain region. The buried layer is formed laterally aligned with respect to the well region, and separated therefrom by a portion of an epitaxial layer. The lateral double diffused metal oxide semiconductor (LDMOS) device exhibits enhanced electrical performance.

Abstract: The present invention provides a system for efficiently producing versatile, high-precision MOS device structures in which straight regions dominate the device's behavior, providing minimum geometry devices that precisely match large devices, in an easy, efficient and cost-effective manner. The present invention provides methods and apparatus for producing double diffused semiconductor devices that minimize performance impacts of end cap regions. The present invention provides a MOS structure having a moat region (404, 516, 616), and an oxide region (414, 512, 608) overlapping the moat region. A double-diffusion region (402, 504, 618) is formed within the oxide region, having end cap regions (406, 502, 620) that are effectively deactivated utilizing geometric and implant manipulations.

Abstract: The invention disclosed a power MOSFET with reduced snap-back and being capable increasing avalanche-breakdown current endurance, which has sequentially a drain with N+ silicon substrate, an N31 epitaxial layer formed on said N+ silicon substrate, a source contact region formed of N+ doped well and P+ doped well implanted after etching in a P− well formed on said N− epitaxial layer, and a gate electrode with deposition of polysilicon above a channel between said N− epitaxial layer and N+ source contact region, said device is characterized in that: Said source contact region is formed by etching into said P− well first and implanting P+ dopant to the interface between said N− epitaxial layer and P− well, and the source contact region of said N+ well and that of said P+ well are not at the same level, by which it is possible to increase the avalanche-breakdown current endurance of the power MOSFET device.