Abstract: An electrically conductive layer or layer sequence preferably includes a metal-containing layer applied to a metal silicide or a polysilicon layer to reduce the resistance of buried bit lines. The layer or layer sequence has been patterned in strip form so as to correspond to the bit lines and is arranged on the source/drain regions of memory transistors having an ONO memory layer sequence and gate electrodes that are arranged in trenches. The metal silicide is preferably cobalt silicide, and the metal-containing layer is preferably tungsten silicide or WN/W. .

Abstract: The invention disclosed a power MOSFET with reduced snap-back and being capable increasing avalanche-breakdown current endurance, which has sequentially a drain with N+ silicon substrate, an N− epitaxial layer formed on said N+ silicon substrate, a source contact region formed of N+ doped well and P+ doped well implanted after etching in a P− well formed on said N− epitaxial layer, and a gate electrode with deposition of polysilicon above a channel between said N− epitaxial layer and N+ source contact region, said device is characterized in that: Said source contact region is formed by etching into said P− well first and implanting P+ dopant to the interface between said N− epitaxial layer and P− well, and the source contact region of said N+ well and that of said P+ well are not at the same level, by which it is possible to increase the avalanche-breakdown current endurance of the power MOSFET device.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A device isolation region made up of a silicon oxide film, which is perfectly isolated up to the direction of the thickness of an SOI silicon layer, and an activation region of the SOI silicon layer, whose only ends are locally thinned, are formed on an SOI substrate. A source diffusion layer and a drain diffusion layer of a MOS field effect transistor in the activation region are provided so that according to the silicidization of the SOI silicon layer subsequent to the formation of a high melting-point metal, a Schottky junction is formed only at each end of the activation region and a PN junction is formed at a portion other than each end thereof.

Abstract: A thin film transistor array substrate includes a substrate, a gate wire with a gate line and a gate electrode formed on the substrate, a gate insulating layer covering the gate wire, and a semiconductor pattern formed on the gate insulating layer. A data wire is formed on the gate insulating layer and the semiconductor pattern with a data line, and a source electrode and a drain electrode. The data wire bears a multiple-layered structure having a metallic layer and an intermetallic compound layer. A protective layer is formed on the data wire and the semiconductor pattern. A pixel electrode is formed on the protective layer while contacting the drain electrode through a contact hole.

Abstract: The invention provides semiconductor devices having an output circuit in which transistors do not fail to achieve their original capability, and electrostatic breakdown is difficult to occur.

Abstract: A semiconductor device and a method for manufacturing the same are provided. The structure of a semiconductor device includes gate electrodes having a T-shaped structure comprised of first and second gate electrodes having low gate resistance and low parasitic capacitance and a halo ion-implanted region in which a short channel effect can be effectively suppressed. The method for manufacturing the device is capable of performing high angle ion implantation without extending gate-to-gate space.

Abstract: By forming a doped polysilicon layer (PS2) containing boron through the CVD method in a material gas including a compound containing boron such as BCl3 (boron trichloride), an opening left after removing a gate electrode (11) in a region (PR) is filled with the doped polysilicon layer (PS2). In the doped polysilicon layer (PS2), boron atoms are uniformly distributed with high activation rate. Thus provided is a method of manufacturing a semiconductor device, which is capable of suppressing depletion of a gate electrode of a P-channel MOS transistor and suppressing penetration of impurity in a CMOS transistor of dual-gate structure.

Abstract: A semiconductor device and a manufacturing method thereof permitting the quality of gate insulating films to be prevented from deteriorating and thereby permitting electrical characteristics of the device to be prevented from deteriorating are provided. In a semiconductor device including a plurality of field effect transistors, an oxidation protection film 21 is formed on a side of one gate electrode 19.

Abstract: A semiconductor integrated circuit device, which is intended to prevent the characteristic degradation, includes multiple limiter circuits which are laid out by being scattered across a semiconductor substrate to produce an internal power voltage of a certain voltage level. Each limiter circuit is laid out so as to have its transistor formation area located just beneath the formation area of a bump electrode which puts in an externally supplied power voltage. The scattered layout of limiter circuits avoids the concentration of current to one limiter circuit and alleviates the harmful heat-up of the limiter circuits and their periphery. The shorter wiring length from the bump electrode to the transistor results in a smaller wiring resistance, alleviating the power voltage drop on the wiring.

Abstract: A high voltage insulated gate field-effect transistor includes an insulated gate field-effect device structure having a source and a drain, the drain being formed with an extended well region having one or more buried layers of opposite conduction type sandwiched therein. The one or more buried layers create an associated plurality of parallel JFET conduction channels in the extended portion of the well region. The parallel JFET conduction channels provide the HVFET with a low on-state resistance.

Abstract: A photo-EMF sensor and a method of making same has a substrate with a semiconducting layer; a plurality of sensing regions in the layer, each sensing region including (i) a pair of electrodes disposed in, on or above the layer and (ii) an active region in the layer disposed adjacent said pair of electrodes; and a plurality of inactive regions in said the arranged between adjacent sensing regions. The inactive regions and the sensing regions are dosed with a desensitizing agent, the inactive regions receiving a relatively higher dose of the desensitizing agent and the sensing regions receiving a relatively lower dose of the desensitizing agent. The active layer is preferably placed in a monolithic Fabry-Perot cavity to enhance the optical efficiency and performance of the sensor.

Abstract: A small and thin pressing direction sensor that can continually detect pressing directions in the angle range of 360 degrees is provided. This pressing direction sensor includes a ring-like resistive film pattern, a first electrode pattern, and a conductive member that electrically connects the resistive film pattern and the first electrode pattern when pressed. The voltage of the first electrode pattern represents the pressing direction. This pressing direction sensor may further include a second electrode pattern. A signal representing the pressing force can be obtained from the second electrode pattern when the pressed conductive member is brought into contact with the second electrode pattern.

Abstract: A method of making a micro electromechanical switch or tunneling sensor. A cantilevered beam structure and a mating structure are defined on a first substrate or wafer; and at least one contact structure and a mating structure are defined on a second substrate or wafer, the mating structure on the second substrate or wafer being of a complementary shape to the mating structure on the first substrate or wafer. At least one of the mating structures includes a protrusion extending from a major surface of at least one of said substrates. A bonding layer, preferably a eutectic bonding layer, is provided on at least one of the mating structures. The mating structure of the first substrate is moved into a confronting relationship with the mating structure of the second substrate or wafer. Pressure is applied between the two substrates so as to cause a bond to occur between the two mating structures at the bonding or eutectic layer.

Abstract: An electrostatic electroacoustical transducer contains an electrically conductive fixed electrode plate having an active surface with recesses. A conductive or semiconductive flexible diaphragm is disposed at a distance from the active surface of the electrode plate and within the recesses. An insulating device is disposed between the electrode plate and the diaphragm.

Abstract: The present invention provides a semiconductor device including a silicon substrate; a heat insulating layer including a silicon oxide film; and a heat detecting portion, in which the heat insulating layer includes a closed cavity and/or a hole, an interior of the hole has a greater diameter than an opening of the hole, and at least a portion of the closed cavity or the hole is formed within the silicon oxide film. The invention also provides a method of manufacturing this semiconductor device.

Abstract: This invention relates an optoelectronic material comprising a uniform medium with a controllable electric characteristic; and semiconductor ultrafine particles dispersed in the medium and having a mean particle size of 100 nm or less, and an application device using the same.

Abstract: An image sensor of this invention includes a substrate, a photosensitive chip, an encapsulant, and a transparent layer. The photosensitive chip is arranged on the substrate and is electrically connected to the substrate via a plurality of wires. The encapsulant is adhered or coated onto the substrate and at the periphery of the photosensitive chip to surround the photosensitive chip. The height of the encapsulant is slightly greater than the thickness of the photosensitive chip. The transparent layer is placed on the encapsulant to cover the photosensitive chip. A method for packaging the image sensor is also disclosed. According to the structure and method, the manufacturing processes can be simplified, the yield can be increased, and the manufacturing costs can be lowered.

Abstract: A MISFET capable of a high speed operation includes a metal silicide layer in a high concentration region aligned with a gate side wall layer on a self-alignment basis. A MISFET which can be driven at a high voltage includes an LDD portion having a width greater than the width of the side wall layer, a high concentration region in contact with the LDD portion and a metal silicide layer in the high concentration region.

Abstract: A high-voltage transistor with a low specific on-state resistance and that supports high voltage in the off-state includes one or more source regions disposed adjacent to a multi-layered extended drain structure which comprises extended drift regions separated from field plate members by one or more dielectric layers. With the field plate members at the lowest circuit potential, the transistor supports high voltages applied to the drain in the off-state. The layered structure may be fabricated in a variety of orientations. A MOSFET structure may be incorporated into the device adjacent to the source region, or, alternatively, the MOSFET structure may be omitted to produce a high-voltage transistor structure having a stand-alone drift region.

Abstract: A system for and a method of integrating SRAM cells and flash EPROM cells onto a single silicon substrate includes an area on the silicon substrate where a local oxidation of silicon (LOCOS) isolation technique is implemented and another area on the same silicon substrate where a shallow trench isolation (STI) technique is implemented. Further, this system and method also include flash EPROM cells implemented within the area of the substrate utilizing the LOCOS isolation technique and SRAM cells implemented within the area of the substrate utilizing the STI technique. Preferably, the LOCOS isolation technique is first implemented to define a flash area of the silicon substrate on which the flash EPROM cell is implemented. Before the LOCOS isolation technique is implemented, an SRAM area is masked.

Abstract: A semiconductor device includes first and second semiconductor layers and first and second MOS transistors. The first semiconductor layer is provided on and electrically connected to the semiconductor substrate. The second semiconductor layer is provided near the first semiconductor layer and formed above the semiconductor substrate via one of an insulating film and a cavity. The first and second MOS transistors are respectively provided on the first and second semiconductor layers, and each has a gate electrode arranged parallel to a boundary between the first and second semiconductor layers.

Abstract: There is provided a semiconductor device capable of properly processing RF signals even though the number of electrodes as well as terminals for external connection is large while pitches at which the electrodes are juxtaposed are narrower than those for the terminals for external connection. A reference electrode connected with a reference voltage line of integrated circuits is increased in number to plurality, and each of the reference electrodes is disposed on top of the semiconductor piece, and on opposite sides of the respective signal electrodes connected with the signal lines of the integral circuits while short circuited at a conductor layer. Further, a conductor layer is extended from the respective reference electrodes or the conductor layer towards both sides of the respective signal electrodes.

Abstract: There is provided by this invention a novel and unique configuration for combining multiple die such as metal oxide field effect transistors (MOSFETS) in high power high frequency applications to prevent internal oscillation. A first embodiment of this invention comprises a split gate design wherein the gate distribution network for multiple semiconductor devices is split to provide individual gate feeds to each device. A second embodiment provides a plurality of semiconductors devices arranged in a configuration such that the reference terminals are connected together at a common point at the approximate center of the configuration that allows external connections to the semiconductor devices' input and output terminals positioned on the outer periphery of the configuration design.

Abstract: The present invention is related to a semiconductor device that forms an inductor on the same semiconductor substrate together with other active elements and a manufacturing method thereof. The semiconductor device of the present invention comprises a substrate, a semiconductor layer (high-resistance semiconductor layer) formed on this substrate that has an impurity concentration lower than the impurity concentration of the substrate or a first semiconductor layer (high-resistance semiconductor layer) of a first conducting type with an impurity concentration lower than the substrate and a second semiconductor layer of a second conducting type on the first layer, an insulating film formed on this high-resistance semiconductor layer (semiconductor layer, first semiconductor layer), and an inductor formed on this insulating film.

Abstract: A semiconductor structure that includes at least one circuit element of a fuse, a diffusion barrier or a capacitor that is formed by refractory metal-silicon-nitrogen is disclosed. A method for fabricating such semiconductor structure that includes a fuse element, a diffusion barrier, a resistor or a capacitor by a refractory metal-silicon-nitrogen material is further disclosed. A suitable refractory metal-silicon-nitrogen material to be used is TaSiN which provides a wide range of resistivity by changing the ratio of Ta:Si:N. The invention provides the benefit that the various components of diffusion barriers, fuses, capacitors and resistors may be formed by a single deposition process of a TaSiN layer, the various components are then selectively masked and treated by either heat-treating or ion-implantation to vary their resistivity selectively while keeping the other shielded elements at the same resistivity.

Abstract: Layered germanium polymers that are semiconductive and demonstrate a strong red or infrared luminescence are produced through the topochemical conversion of calcium digermanide. Furthermore, silicon/germanium layer polymers can also be produced in this manner. These layer polymers can be produced epitaxially on substrates comprising crystalline germanium, and can be used to construct light-emitting optoelectronic components such as light-emitting diodes or lasers.

Abstract: In various embodiments, the invention is directed to aperture mask deposition techniques for use in creating integrated circuits or integrated circuit elements. In other embodiments, the invention is directed to different apparatuses that facilitate the deposition techniques. The techniques generally involve sequentially depositing material through a number of aperture masks formed with patterns that define layers or portions of various layers of a circuit. In this manner, circuits can be created using aperture mask deposition techniques, without requiring any etching or photolithography, which is particularly useful when organic semiconductors are involved. The techniques can be useful in creating circuit elements for electronic displays, low-cost integrated circuits such as radio frequency identification (RFID) circuits, and other circuits.

Abstract: To a provide a method of forming a layered film of a silicon nitride film and a silicon oxide film on a glass substrate in a short time without requiring a plurality of film deposition chambers. In a thin film transistor, a layered film including a silicon nitride oxide film (12) is formed between a semiconductor layer (13) and a substrate (11) using the same chamber. The silicon nitride oxide film has a continuously changing composition ration of nitrogen or oxygen. An electric characteristic of the TFT is thus improved.

Abstract: A lead frame of a plastic integrated circuit package is fabricated in two steps. First, from a rectangular sheet of metal, lead fingers of the lead frame are formed. Second, the die pad of the lead frame is clamped and is simultaneously separated and downset from the lead fingers of the lead frame by shearing the lead frame with a mated punch die pair. Performing the separation and downset of the die pad from the lead fingers results in essentially no horizontal gap between the lead fingers and the die pad. The downset of the die pad with respect to the lead fingers results in a vertical separation between the die pad and the lead fingers.

Abstract: In a surface-mounted optical transmission module, a laser diode serving as a light emitting device that converts an electric signal into an optical signal, and an optical waveguide serving as an optical transmission line that transmits and outputs the optical signal from the laser diode are placed on a substrate. A driving device for controlling the driving of the laser diode is placed at a predetermined position on the upper surface of the optical waveguide element, which is on the same side as an optical waveguide element (on the downstream side in the optical-signal transmitting direction) relative to the laser diode. This configuration eliminates the necessity of placing the driving device at a position distanced from the laser diode, whereby the size of the optical transmission module can be reduced, and this allows the optical transmission module to transmit optical signals at high speed.

Abstract: A semiconductor device (10) includes a semiconductor die (14) having first and second circuit regions (30, 32) formed on a first surface (24). The semiconductor die is housed in a semiconductor package (20) whose lid (40) is formed with a projection (67) that electrically contacts the first surface of the semiconductor die to shield the first circuit region from the second circuit region. Also, inactive components, such as a capacitor can be formed in lid (40).

Abstract: A package for packaging a semiconductor die is provided that increases the reliability of packaged semiconductor circuits in particular in high frequency applications where both analog and digital signals are used. The package comprises a first die attach paddle which is connectable to a first part of a bottom surface of the semiconductor die, and a second die attach paddle which is connectable to a second part of the bottom surface of the semiconductor die. The first and second die attach paddles are each made of an electrically conductive material, and are electrically separated from each other. Further, a corresponding semiconductor device and a method of fabricating a package and packaging a semiconductor die are provided. When packaging dies having analog and digital circuits, separate grounds not only on the chip but also in the package can be achieved so that cross talking problems can be effectively reduced.

Abstract: An integrally packaged optronic integrated circuit device (310) including an integrated circuit die (322) containing at least one of a radiation emitter and radiation receiver and having top and bottom surfaces formed of electrically insulative and mechanically protective material, at least one of the surfaces (317) being transparent to radiation, and electrically insulative edge surfaces (314) having pads.

Abstract: The present invention provides a kind of multi-application type IC card that can be accessed by an external terminal of a file system type IC card. There are installed, on a multi-application type IC card, emulator programs that can process commands from an external terminal for a file system type IC card. This will enable an external terminal for a file system type IC card to access a multi-application type IC card.

Abstract: In a pressure sensor module according to the prior art, which is intended for detecting the pressure of a corrosive medium, the conventional sensor cell with a pressure sensor chip is modified in order to protect it from corrosion, which results in a large volume for a pressure-transmitting fluid. This is disadvantageous for the calibration and for a high degree of measurement precision.

Abstract: To realize a semiconductor device with a highly reliable three-dimensional mounting module using a flexible circuit substrate which is easy to assemble a high density three-dimensional mounting module and is excellent in the workability in repair work (or re-work), a flexible circuit substrate 11 has mounting regions 111, 112 and 113 on which electronic components 121, 122 and 123 are mainly mounted, respectively, and other electronic components 124 and 125 are also mounted. The flexible circuit substrate 11 is structured in such a manner that the mounting regions 111˜113 are folded on top of the other over the base region 110 in a predetermined order (f1˜f3). An integrated spacer 13 is superposed and affixed to the flexible circuit substrate as indicated by arrows with broken lines, and supports the electronic components 121˜125 when the mounting regions 111˜113 are folded on top of the other. The integrated spacer 13 has thick regions 131 and thin regions 132.

Abstract: The present invention has an object to provide a more compact semiconductor device that can be assembled with reduced parts and tasks. The semiconductor device includes a housing having a top and bottom surfaces. Surrounded within the housing is an insulating substrate with metal layers formed on both sides thereof. Also a semiconductor chip is mounted on one of the metal layer of the insulating substrate. A terminal connector extends along the top surface of the housing and is bent towards the bottom surface thereof for supplying power to the semiconductor chip. The housing has a housing through-hole extending from the top surface to the bottom surface through the housing, and the terminal connector has a terminal through-hole which are aligned with and formed coaxially with the housing through-hole.

Abstract: A method and apparatus for thermally conducting heat from a semiconductor device, namely, a flip-chip assembly. In one embodiment, a heat sink, such as a diamond layer having openings therein, is provided over a surface of a semiconductor device. Conductive pads are formed in the openings to be partially contacting the diamond layer and to electrically communicate with the semiconductor device. The heat produced from the semiconductor device and thermally conducting through the conductive pads is thermally conducted to the heat sink or diamond layer and away from the interconnections, i.e., solder bump connections, between a semiconductor device and a carrier substrate in a flip-chip assembly. As a result, thermal fatigue is substantially prevented in a flip-chip assembly.

Abstract: Provided is a water cooling type cooling block for a semiconductor chip which can increase heat transfer efficiency by inducing turbulent flow even if a coolant flows at low speed. The cooling block includes a heat transfer plate contacting the semiconductor chip, a case connected to the heat transfer plate to enclose the heat transfer plate so as to accommodate a coolant for cooling heat from the heat transfer plate and having a coolant inlet port at its first end and a coolant outlet port at its second end so as to allow movement of the coolant, and a sealing means hermetically sealing the heat transfer plate and the case.

Abstract: A thermally coupling electrically decoupling cooling device is described. The cooling device may be thermally disposed between a self-heating electrically conductive line and a semiconductor substrate to cool the line by transferring heat from the line to the substrate while blocking flow of current from the line to the substrate. The cooling device may contain a thermally conductive structure, such as a stack of vias and lines, to conduct heat away from the electrically conductive line, and a current blocking structure, such as a reverse biased diode or a capacitor, to block current flow into the substrate. Specific current blocking structures include a reverse biased diode containing an n-doped region and a p-doped region disposed between the thermally conductive structure and the substrate, and a capacitor containing a dielectric layer disposed between the thermally conductive structure and the semiconductor substrate.

Abstract: A microelectronic die and a method of packaging the die. A thermally conductive material, such as copper, is placed in an inner region located between a die substrate, such as a silicon wafer, and a dielectric, such as a subsequent silicon layer. A microelectronic circuit is provided on at least one of the die substrate and the dielectric. Thermal contact is established between an outer region located outside of the inner region and the thermally conductive material placed in the inner region to effect a dissipation of heat away from the microelectronic circuit.

Abstract: A laminate multilayer ball-grid-array package is suitable for millimeter-wave circuits. The frequency bandwidth of the package is DC to 40 GHz. The package is made using laminate circuit board materials to match the temperature expansion coefficients of the package to the host PCB. Electrical connection between the package and the host PCB on which the package is mounted is achieved using ball-grid-array technology. The package can be sealed, covered, or encapsulated, and is suitable for high-volume production.

Abstract: A chip mounting method is proposed which considers facilitating the testing of semiconductor chips when a plurality of semiconductor chips are sealed in a single resin sealing body. This method also considers its application to a variety of MCPs and system LSIs. In a single package, one signal output terminal of the first semiconductor chip and a first external terminal of the semiconductor device are internally connected independently. One signal input terminal of the second semiconductor chip and a second external terminal of the semiconductor device are internally connected independently. The first and second external terminals of the semiconductor device are connected outside the semiconductor device to complete the connection between the signal output terminal and the signal input terminal.

Abstract: After a trench 54 is formed in a conductive foil 60, the circuit elements are mounted, and the insulating resin is applied on the conductive foil 60 as the support substrate. After being inverted, the conductive foil 60 is polished on the insulating resin 50 as the support substrate for separation into the conductive paths. Accordingly, it is possible to fabricate the circuit device in which the conductive paths 51 and the circuit elements 52 are supported by the insulating resin 50, without the use of the support substrate. And the interconnects L1 to L3 requisite for the circuit are formed, and can be prevented from slipping because of the curved structure 59 and a visor 58.

Abstract: A wide bandwidth mixer has a low temperature co-fired ceramic substrate. The substrate has a top layer, a bottom layer and inner layers. Vias extend through the substrate. A local oscillator balun and an RF balun are located on the inner layers and connected to the vias. An intermediate frequency balun is mounted to the top layer and connected to the vias. Field effect transistors are mounted on the top layer and connected to the local oscillator balun, the RF balun and the intermediate frequency balun through the vias. A matching network is mounted to the top layer and is connected to the vias. The matching network matches the impedance of the field effect transistors to that at the LO port.

Abstract: A semiconductor chip is mounted on a wiring board that has a two-layer lead structure. One of the leads used for receiving input signals is disposed on the lower layer and runs underneath the semiconductor chip forming an U-shaped wiring line while other leads are disposed on the upper layer. Because one of the upper layer leads for receiving input signals is disposed in the U-shaped pocket of the U-shaped wiring line of the lower layer, the relative positioning of corresponding terminals can be changed into a reversal of the positioning of the electrode pads of the chip connected to the terminals. Furthermore, one of the upper layer lead for receiving control signals is placed between the chip and the lower layer lead underneath the chip to prevent high frequency signal interference.

Abstract: A circuit arrangement includes a programmable memory element mounted on a circuit board, with programming contacts of the memory element connected to conductor paths of the circuit board. Data and/or programming codes stored in the memory element determine the functions of the circuit arrangement. To prevent unauthorized reprogramming of the memory element, at least one programming contact of the memory element and each conductor path connected thereto are covered or enclosed, so it is impossible to electrically contact this programming contact or the associated conductor paths without destroying the circuit arrangement. The circuit board is adhesively bonded to a board carrier, with the memory element and conductor paths sandwiched or encased therebetween. The circuit arrangement may be an engine controller for a motor vehicle, with security against unauthorized reprogramming for altering the performance of the engine.

Abstract: In a semiconductor device including a metal substrate having one surface on which a semiconductor chip is mounted and the other surface on which solder balls are mounted, the semiconductor chip is electrically connected to the solder balls through through-holes formed in the substrate and bonding wires. An insulating film is formed on a whole surface of the substrate including inner surface of the through-holes and the solder balls are supported by the through-holes, so that a wiring connected to the electrically conductive through-holes and the semiconductor chip are electrically connected by the bonding wires. Diameter of the through-hole in the other surface of the substrate on which the solder ball is supported is larger than diameter of the through-hole in the one surface of the substrate.

Abstract: A columnar bump formed of copper etc. is formed on a wiring film of a semiconductor chip through an interconnected film and an adhesive film in a wafer unit by electrolytic plating in which package formation is possible. An oxidation prevention film is formed of such as gold on an upper surface or a part of the upper surface and side surface. A wet prevention film of such as an oxide film is formed on the columnar bump side as needed. If this bump is soldered to the pad on a packaging substrate, solder gets wet in the whole region of the columnar bump upper surface and only a part of the side surface. Stabilized and reliable junction form can be thus formed. Moreover, since the columnar bump does not fuse, the distance between a semiconductor board and a packaging board is not be narrowed by solder.