Abstract: A screen printed light emitting polymer device is fabricated by depositing an electroluminescent polymer layer between a transparent electrode and an air stable screen printed top electrode. Screen printing a conductive electrode on top of a light emitting polymer layer typically results in a short circuit because metal conductive particles poke through the polymer layer. We have found three ways to prevent this. One is to screen print an organic conductor on top of the light emitting polymer layer so that metal conductive particles cannot penetrate to the transparent electrode. Another way is to decrease the particle size in the conductive metal paste in addition to using a solvent that does not soften the light emitting polymer layer being printed on. A third way is to print a sol-gel conductive layer where the conductive metal particles precipitate after the layer is printed. In addition, additives to the screen printed top electrode can be used to improve device efficiency.

Abstract: A polysilicon film is formed with enhanced selectivity by flowing chlorine during the formation of the film. The chlorine acts as an etchant to insulative areas adjacent polysilicon structures on which the film is desired to be formed. Bottom electrodes for capacitors are formed using this process, followed by an anneal to create hemishperical grain (HSG) polysilicon. Multilayer capacitor containers are formed in a non-oxidizing ambient so that no oxide is formed between the layers. The structure formed is planarized to form separate containers made from doped and undoped amorphous silicon layers. Selected ones of undoped layers are seeded in a chlorine containing environment and annealed to form HSG. A dielectric layer and second electrode are formed to complete the cell capacitor.

Abstract: A method for forming an oxidation barrier including at least partially immersing a semiconductor device structure in an electroless plating bath that includes at least one metal salt and at least one reducing agent. The reaction of the at least one metal salt with the at least one reducing agent simultaneously deposits metal and a dopant thereof. The oxidation barrier may be used to form conductive structures of semiconductor device structures, such as a capacitor electrode, or may be formed adjacent conductive or semiconductive structures of semiconductor device structures to prevent oxidation thereof. The oxidation barrier is particularly useful for preventing oxidation during the formation and annealing of a dielectric structure from a high dielectric constant material, such as Ta2O5 or BST.

Abstract: A method for conditioning or repairing a dielectric structure of a semiconductor device structure with selectivity over an adjacent conductive or semiconductive structure of the semiconductor device structure, such as a capacitor dielectric and an adjacent bottom electrode of the capacitor. The method includes exposing the dielectric structure and at least an adjacent surface of the conductive or semiconductive structure to an oxidizing atmosphere that includes at least one oxidant and hydrogen species. The at least one hydrogen species adsorbs to a surface of the conductive or semiconductive structure so as to substantially prevent passage of the at least one oxidant into or through the conductive or semiconductive structure. The oxidant oxidizes or repairs voids or other defects that may be present in the dielectric structure. Semiconductor device structures fabricated by employing the method are also disclosed.

Abstract: Disclosed is a capacitor construction for a more uniformly thick capacitor dielectric layer, and a method for fabricating the same. The method has special utility where the bottom electrode comprises composite layers over which the capacitor dielectric demonstrates differential growth during deposition. Exposed portions of an underlying first electrode layer, are covered either by a conductive or dielectric spacer, or by a dielectric padding. For the preferred embodiments, in which the bottom electrode comprises titanium carbonitride over rough polysilicon, a dielectric padding may be formed during a rapid thermal nitridation step, which causes silicon nitride to grow out of an exposed polysilicon sidewall. Alternatively, a sidewall spacer may be formed by deposition an additional layer of titanium nitride over the original titanim nitride strap, and performing a spacer etch.

Abstract: In a method for forming capacitors of semiconductor devices, a contact plug penetrating an interlayer dielectric (ILD) is formed on a semiconductor substrate. A supporting layer, an etch stop layer, and a molding layer are sequentially formed on the semiconductor substrate where the contact plug is formed. The molding layer is patterned to form a molding pattern. At this time, the molding pattern has an opening exposing an etch stop layer over the contact plug. Next, an adhesive spacer is formed on sidewalls of the opening. The etch stop layer and the supporting layer, which are exposed through the opening where the adhesive spacer is formed, are successively patterned. Thus, the etch stop pattern and the supporting pattern are formed to expose the contact plug. A lower electrode and a sacrificial pattern are formed to sequentially fill a hole region surrounded by sidewalls of the adhesive spacer, the etch stop pattern, and the supporting pattern.

Abstract: An operational margin of a memory of a semiconductor integrated circuit device including an SRAM is improved. In order to set the Vth of driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance QL forming memory cells of an SRAM, relatively and intentionally higher than the Vth of predetermined MISFETs of SRAM peripheral circuits and logic circuits such as microprocessor, an impurity introduction step is introduced to set the Vth of the driving MISFETs Qd, transfer MISFETs Qt and MISFETs for load resistance, separately from an impurity introduction step for setting the Vth of the predetermined MISFETs.

Abstract: A method for fabricating a gate of a flash memory is described. A tunneling oxide layer, a first polysilicon layer and a silicon nitride layer are sequentially formed on a substrate. A photo-resist layer is formed on the silicon nitride layer and then the photo-resist layer, the silicon nitride layer, the polysilicon layer, the tunneling oxide layer and the substrate are patterned to form a plurality trenches in the substrate. An active area defined by every two trenches is simultaneously formed. The photo-resist layer is removed. A plurality of shallow trench isolation (STI) structures is formed in the trenches by filling the trenches with silicon oxide up to the top of the silicon nitride layer. The top portion of the shallow trench isolation structures is removed to expose the sidewall of the silicon nitride layer and the top portion of the sidewall of the first polysilicon layer. Part of the silicon nitride layer is removed by wet etching.

Abstract: The floating gate, or the oxide between the floating and control gates, or both are nitrided before the control gate layer is deposited.

Abstract: The floating gate, or the oxide between the floating and control gates, or both are nitrided before the control gate layer is deposited.

Abstract: Provided is a memory device formed using quantum devices and a method for manufacturing the same. A memory device comprises a substrate; a source region and a drain region formed in the substrate so as to be separated from each other by a predetermined interval; a memory cell which is formed on the surface of the substrate to connect the source region and the drain region, and has a plurality of nano-sized quantum dots filled with material for storing electrons; and a control gate which is formed on the memory cell and controls the number of electrons stored in the memory cell. It is possible to embody a highly efficient and highly integrated memory device by providing a memory device having nano-sized quantum dots and a method for manufacturing the same.

Abstract: A method of forming an electrically erasable non-volatile memory cell array. Each memory cell includes a floating gate, a block of insulation material over the floating gate, and a control gate disposed laterally adjacent to and over the floating gate. The insulation material block is formed with a planarized upper surface (using a dummy poly layer as a planarization etch stop). The control gate is formed with a planarized upper surface (using the insulation material block upper surface as a planarization etch stop).

Abstract: According to embodiments of the invention, a first gate insulating pattern and a mask pattern are sequentially stacked on a semiconductor substrate. Subsequently an impurity region is formed in the semiconductor substrate. Next, the mask pattern is removed to expose the first gate insulating pattern and a second gate insulating layer is formed on the entire surface thereof. The mask pattern is preferably formed of an anti-reflecting pattern and a photoresist pattern that are sequentially stacked. The anti-reflecting pattern is preferably formed of a material layer without etching selectivity with respect to the photoresist pattern. For this, the anti-reflecting pattern is preferably formed of organic materials including hydrocarbonic compounds. In addition, removing a mask pattern is performed with an etch recipe having an etch selectivity with respect to the first gate insulating pattern.

Abstract: A manufacturing method of this invention has an ion-implantation process for threshold voltage adjustment of an MOS transistor, including a process to form a first well of an opposite conductivity type in a substrate of one conductivity type, to form a second well of the opposite conductivity type having higher impurity concentration than that in the first well, under a region where a thin gate insulation film is formed, to form gate insulation films on the first well and the second well, each having a different thickness, to ion-implant first impurities of the one conductivity type into the wells of the opposite conductivity type under the condition that the impurities penetrate the gate insulation films of different thicknesses and to ion-implant second impurities of the one conductivity type into the second well of the opposite conductivity type under the condition that the second impurities penetrate the thin gate insulation film but do not penetrate the thick gate insulation film.

Abstract: Field-effect transistors, and methods of their fabrication, having channel regions formed separately from their source/drain regions and having monocrystalline material interposed between the channel regions and the source/drain regions. The monocrystalline material includes monocrystalline silicon and silicon-germanium alloy.

Abstract: A monotonic dynamic-static pseudo-NMOS logic circuit comprises a dynamic logic circuit having a clock input and having an output configured to be pre-charged high when a low clock signal is provided to the clock input; and a static logic circuit having a clock bar input and having an output configured to be precharged low when a high value of the complement of the clock signal is provided to the clock bar input. A logic gate array comprises a plurality of vertical ultrathin transistors coupled together.

Abstract: A method comprising introducing a crystalline film with silicon germanium over the surface of a semiconductor substrate, and introducing a junction region by an implant of a dopant into the crystalline film. An apparatus comprising a semiconductor substrate having an active region and comprising a crystalline film comprising germanium in the active region, a gate electrode overlying the crystalline layer, and junction regions formed in the substrate adjacent opposite sides of the gate electrode.

Abstract: A method for increasing area of a trench capacitor. First, a first oxide layer and a first nitride layer are sequentially formed on a substrate. An opening is formed through the first oxide layer and the first nitride layer into the substrate. A part of the first oxide layer exposed in the opening is removed to form a first recess, and then a second nitride layer is formed therein. A second oxide layer is formed in the lower portion of the opening. After a third nitride layer is formed in the upper portion of the opening, the second oxide layer is removed. The substrate in the opening is etched using the first nitride layer, the second nitride layer and the third nitride layer as a mask to form a second recess in the lower portion of the opening. The second nitride layer and the third nitride layer are then removed.

Abstract: An integrated circuit includes electrical components that include one or more electrical elements on one or more dielectric layers. The electrical element has a geometric shape that exceeds prescribed integrated circuit manufacturing limits in at least one dimension. To achieve compliance with foundry rules, the electrical element is fabricated to include a non-conducting region that negligibly effects the electrical characteristics. The non-conducting region includes a hole, a series of holes, a slot and/or a series of slots spaced within the electrical element at dimensions that are less than the integrated circuit manufacturing limits.

Abstract: The thermomechanical stress sensitivity of ball grid array (BGA) solder connections is significantly reduced, when the solder connections solidify in column-like contours after the reflow process—a result achieved by using the solder material in tapered openings of a thick sheet-like elastic polymer adhered to the BGA substrate and selected for its characteristics of non-wettability to solder and volumetric shrinkage greater than solder.

Abstract: A method for fabricating a strained Si based layer, devices manufactured in this layer, and electronic systems comprising such layers and devices are disclosed. The method comprises the steps of growing epitaxially a SiGe layer on a substrate, and creating a varying Ge concentration in this SiGe layer. The Ge concentration in the SiGe layer includes a unique Ge overshoot zone, where the Ge concentration is abruptly and significantly increased. The Si based layer is epitaxially deposited onto the SiGe layer, whereby is becomes tensilely strained. It is also disclosed that the strained Si based layer, typically Si or SiGe, can be transferred to a different bulk substrate, or to an insulator.

Abstract: The present invention provides a method for producing a bonded wafer comprising at least an ion implantation process where at least either hydrogen ions or rare gas ions are implanted into a first wafer from its surface to form a micro bubble layer (implanted layer) in the first wafer, a bonding process where the surface subjected to the ion implantation of the first wafer is bonded to a surface of a second wafer, and a delamination process where the first wafer is delaminated at the micro bubble layer, wherein the ion implantation process is performed in divided multiple steps, and a bonded wafer. Thus, there are provided a method for producing a bonded wafer, which is for reducing micro-voids generated in the ion implantation and delamination method and a bonded wafer free from micro-voids.

Abstract: Processes that may be used in producing electronic, opotoelectronic, or optical components may be provided. The processes may involve preparing a reusable donor wafer for donating a thin layer of semiconductor material by assembling a donor layer of a semiconductor material having a thickness of plural thin layers onto a support layer of. The semiconductor material for the support layer may be selected to be less precious or to have a lower quality than the donor layer. The support layer may have sufficient mechanical characteristics for supporting the donor layer during desired semiconductor processing treatments.

Abstract: A method of regenerating a semiconductor wafer which allows a used wafer, even if the wafer contains a crystal defect such as a COP, to be regenerated into a high-quality semiconductor wafer is provided. A used silicon wafer is polished in a step S1. Next, the used silicon wafer is immersed in mixed acids including at least two kinds of acids in a step S2. A surface treatment is performed on the used silicon wafer to planarize the surface of the used silicon wafer in a step S3. Then, a high temperature annealing process is performed in a step S4, to ultimately obtain a regenerate wafer. The high temperature annealing process includes either a first high temperature annealing process which is performed at a high temperature of 1200° C. or higher in an argon atmosphere for 30 to 60 minutes, or a second high temperature annealing process which is performed at a high temperature of 1200° C. or higher in a hydrogen atmosphere for 30 to 60 minutes.

Abstract: The method of the present invention is a method of forming a silicon-based semiconductor layer by introducing a source gas into a vacuum vessel and forming a silicon-based semiconductor layer containing a microcrystal on a substrate introduced into the vacuum vessel by plasma CVD, which comprises a first step of forming a first region with a source gas containing halogen atoms, and a second step of forming a second region on the first region under a condition where the source gas containing halogen atoms in the second step is lower in gas concentration than that of the first step, thereby providing a method of forming a silicon-based semiconductor layer having an excellent photoelectric characteristic at a film forming rate of an industrially practical level and a photovoltaic element using the silicon-based semiconductor layer formed by the method.

Abstract: The present invention provides an improved surface P-channel transistor and a method of making the same. A preferred embodiment of the method of the present invention includes providing a semiconductor substrate, forming a gate oxide layer over the semiconductor substrate, subjecting the gate oxide layer to a remote plasma nitrogen hardening treatment followed by an oxidative anneal, and forming a polysilicon layer over the resulting gate oxide layer. Significantly, the method of the present invention does not require nitrogen implantation through the polysilicon layer overlying the gate oxide and provides a surface P-channel transistor having a polysilicon electrode free of nitrogen and a hardened gate oxide layer characterized by a large concentration of nitrogen at the polysilicon electrode/gate oxide interface and a small concentration of nitrogen at the gate oxide/semiconductor substrate interface.

Abstract: A laser processing process which comprises laser annealing a silicon film 2 &mgr;m or less in thickness by irradiating a laser beam 400 nm or less in wavelength and being operated in pulsed mode with a pulse width of 50 nsec or more, and preferably, 100 nsec or more.

Abstract: Provided is an excellent p-type nitride type 3-5 group compound semiconductor having escellent electrical properties such as a low contact resistance to an electrode metal, a low ohmic property, etc., by heat-treating a nitride type 3-5 group compound semiconductor doped with p-type dopant in an hydrogen-containing gas atmosphere of a specific concentration.

Abstract: A method and apparatus for forming a relatively thin releasable layer of copper on a carrier substrate. First, a separation facilitating layer is provided on the carrier substrate. A layer of vapor-deposited copper is then formed over the separation facilitating layer to protect the separation facilitating layer during subsequent processing. Thereafter, the thickness of the copper layer is increased by the electrodeposition of copper onto the vapor-deposited layer. The copper layer is applied to a dielectric and is released from the carrier substrate at the separation facilitating layer.

Abstract: A sidewall of a CVD oxide film is formed on a side face of a gate electrode formed on a semiconductor substrate. Then, with the sidewall exposed, the semiconductor substrate is cleaned such that the CVD oxide film has an etch selectivity of 5 or less with respect to a thermal oxide film.

Abstract: A structure for improving electrical performance and interconnection reliability of an integrated circuit in a Wafer Level Packaging (WLP) application comprises an air pad located under an interconnection metal solder pad. Using a low dielectric material such as air underlying the interconnection pad, pad capacitance is reduced, thereby improving the speed of associated electrical signal transitions. By configuring the structure to have interconnection pad supports at only a limited number of pad periphery points, a cured soldered connection can absorb mechanical stresses associated with divergent movement between a connecting wire and the interconnection pad. Such a structure can be manufactured using the steps of: 1) depositing a soluble base material in a cavity on an IC substrate, 2) depositing a metal pad layer on the soluble base layer, and 3) dissolving the soluble base layer, leaving an air gap under the metal pad layer which is supported by the periphery supports.

Abstract: The corrosion of a pad portion on TEG is prevented, and the wettability of a solder and the shear strength after solder formation of a pad portion of an actual device are improved. A third layer wiring M3 on a chip area CA of a semiconductor wafer and a third layer wiring M3 on a scribe area SA are respectively comprised of a TiN film M3a, an Al alloy film M3b, and a TiN film M3c. A second pad portion PAD2 as the top of a rewiring 49 on the chip area CA is cleaned. Alternatively, an Au film 53a is formed thereon by an electroles splating method. Further, after the formation of the Au film 53a, a retention test is carried out. Thereafter, further, an Au film 53b is formed and a solder bump electrode 55 is formed. As a result, it is possible to prevent the corrosion of a first pad portion PAD1 of the third layer wiring M3 on the scribe area SA which is TEG due to a plating solution or the like by the TiN film M3c.

Abstract: A method of forming a top-metal fuse structure comprising the following steps. A structure having an intermetal dielectric layer is formed thereover the structure including a fuse region and an RDL/bump/bonding pad region. A composite metal layer is formed over the intermetal dielectric layer. The composite metal layer including a second metal layer sandwiched between upper and lower first metal layers. The upper first metal layer is patterned to form an upper metal layer portion within the RDL/bump/bonding pad region. The second metal layer and the lower first metal layer are patterned: (1) within the RDL/bump/bonding pad region to form an RDL/bump/bonding pad; the RDL/bump/bonding pad having a patterned second metal layer portion/lower first metal portion with a width greater than that of the upper metal layer portion and forming a step profile; and (2) within the fuse region to form the top-metal fuse structure. The RDL/bump/bonding pad structure includes a step profile.

Abstract: Methods of making a paste of materials used in forming bumps for semiconductor applications wherein the distribution of trace elements is substantially uniform are provided. The methods of making a paste for a semiconductor package process comprises heating and fusing several materials to alloy the materials, rapidly cooling the fused alloy composition to improve conformity of the composition, processing the cooled alloy composition into a fine powder, and processing the alloy powder to be a paste-shape.

Abstract: In a double metal process for forming conductive contacts to integrated circuit structures, a method for preventing the sputtering of non-conductive aluminum compounds onto via sidewalls during the anisotropic oxide etch. A layer of nitride is deposited atop aluminum buried first metal pads before deposited of the silicon dioxide layer. A selective anisotropic oxide etch which selectively stops on the nitride is used to form the via through the oxide layer. Then an isotropic low-powered dry nitride etch extends the via through the nitride to the aluminum pad without producing unwanted sputtering.

Abstract: A Cu interconnection is formed above a semiconductor substrate. An SIC:H film and a silicon nitride film covering the Cu interconnection are formed in this order as protective films of the Cu interconnection. An interlayer insulating film is formed on the silicon nitride film. A via hole is formed in the interlayer insulating film with using the silicon nitride film as a stopper. An upper layer portion of the interlayer insulating film is processed in a portion aligned with the via hole. The silicon nitride film and the SiC:H film are so etched as to be aligned with the via hole. A Cu film is buried in the via hole. This interconnection structure formation method can reliably prevent Cu diffusion from the Cu interconnection to the interlayer insulating film and prevent peeling of the Cu interconnection. In this method, high oxidation resistance is obtained.

Abstract: In one embodiment of the present inventions, an exhaust outlet in a vacuum processing chamber includes a nonsealing flow restrictor which can facilitate rapid opening and closing of the flow restrictor in some applications. Because the flow restrictor is a nonsealing flow restrictor, the conductance of the flow restrictor in the closed position may not be zero. However, the flow restrictor can restrict the flow of an exhaust gas from the chamber to permit the retention of sufficient processing gas in the chamber to deposit a film on the substrate or otherwise react with the substrate. After a film has been deposited, typically in a thin atomic layer, the exhaust flow restrictor may be opened such that the flow restrictor conductance is significantly increased to a second, higher flow rate to facilitate exhausting residue gas from the chamber. The nonsealing flow restrictor may be closed again to deposit a second layer, typically of a different material onto the substrate.

Abstract: A method of fabricating a vertically profiled electrode like a T-gate 40 on a semiconductor substrate 20 is described. The method comprises providing a resist structure 34 on the substrate 20, the resist structure 34 containing at least a first resist pattern 24′ arranged on the substrate 20 and having a first opening 26, the first resist being negative resist, and a second resist pattern 32 having a second opening 30 surrounding the first opening 26. The vertical profile of the gate electrode 40 is defined by the contours and the relative location of the first and the second opening 26, 30. On the resist structure 34 a metal 38 is deposited and lift-off is performed to remove the second resist 32 together with the metal 38 deposited thereon.

Abstract: An apparatus and method for scribing a semiconductor wafer coated with a substantially opaque material using vision recognition is disclosed. The apparatus includes a stage configured to hold a wafer, an imaging unit configured to generate an image of the wafer, and a computer configured to identify the coordinates of the scribe lines on the wafer from the image. During operation, the wafer is imaged using the imaging unit. The computer then identifies the coordinates of the scribe lines on the wafer from the image. Thereafter the coordinates are provided to a dicing machine which performs the dicing of the wafer. Accuracy is therefore improved since the dicing machine relies on the coordinates of the scribe lines as opposed to attempting to recognize the scribe lines through the opaque material. According to various embodiments of the invention, the imaging unit may use infrared, X-ray or ultrasound waves to generate the image of the wafer.

Abstract: A vacuum chamber the inside of which can be maintained in a substantially vacuum condition is used; a wafer in which a semiconductor wiring film is to be formed is held by a wafer substrate holder disposed in the vacuum chamber; the material of the semiconductor wiring film is evaporated by an evaporation source disposed in the vacuum chamber; and a high frequency electric power for generating a plasma in the vacuum chamber, making use of the substrate holder as an electrode is supplied from a high frequency power source.

Abstract: A method of forming a composite tungsten film on a substrate is described. The composite tungsten film comprises sequentially deposited tungsten nucleation layers and tungsten bulk layers. Each of the tungsten nucleation layers and the tungsten bulk layers have a thickness less than about 300 Å. The tungsten nucleation layers and the tungsten bulk layers are formed one over the other until a desired thickness for the composite tungsten film is achieved. The resulting composite tungsten film exhibits good film morphology. The tungsten nucleation layers may be formed using a cyclical deposition process by alternately adsorbing a tungsten-containing precursor and a reducing gas on the substrate. The tungsten bulk layers may be formed using a chemical vapor deposition (CVD) process by thermally decomposing a tungsten-containing precursor.

Abstract: Each region, which should be left on a substrate after patterning, of a semiconductor film is grasped in accordance with a mask. Then, each region to be scanned with laser light is determined so that at least the region to be obtained through the patterning is crystallized, and a beam spot is made to hit the region to be scanned, thereby partially crystallizing the semiconductor film. Each portion with low output energy of the beam spot is shielded by a slit. In the present invention, the laser light is not scanned and irradiated onto the entire surface of the semiconductor film but is scanned such that at least each indispensable portion is crystallized to a minimum. With the construction described above, it becomes possible to save time taken to irradiate the laser light onto each portion to be removed through the patterning after the crystallization of the semiconductor film.

Abstract: The object of the present invention is to provide a process for chemical mechanical polishing of semiconductor substrate that is particularly useful for chemical mechanical polishing a wafer having a wiring pattern and an insulating layer having a low dielectric constant is formed between wiring patterns, interlayers in the case of a multi-layer wiring and the like in the process of producing a semiconductor device, and an aqueous dispersion for chemical mechanical polishing which is used in this process.

Abstract: The invention provides a system for polishing one or more layers of a multi-layer substrate that includes a first metal layer and a second layer comprising (i) a liquid carrier, (ii) at least one oxidizing agent, (iii) at least one polishing additive that increases the rate at which the system polishes at least one layer of the substrate, (iv) at least one stopping compound with a polishing selectivity of the first metal layer:second layer of at least about 30:1, wherein the stopping compound is a cationically charged nitrogen containing compound selected from compounds comprising amines, imines, amides, imides, and mixtures thereof, and (v) a polishing pad and/or an abrasive. The invention also provides a method of polishing a substrate comprising contacting a surface of a substrate with the system and polishing at least a portion of the substrate therewith.

Abstract: A plating apparatus is provided to allow the whole area of a target plating surface of a wafer to be subjected to more uniform plating treatment and moreover enables a target plating surface of a wider area to be subjected to positive and uniform plating treatment. In the plating apparatus which has a stirring bar within a plating tank and which performs plating treatment of a target plating surface of the wafer while stirring a plating solution near the target plating surface of the wafer by moving the stirring bar, the stirring bar is rotated while being oscillated in a motion plane substantially parallel to the target plating surface of the wafer. By this operation, the occurrence of an eddy flow of the plating solution is suppressed during stirring and it becomes possible to positively carry out more uniform plating treatment of a wider region.

Abstract: Chemical generator and method for generating a chemical species at a point of use such as the chamber of a reactor in which a workpiece such as a semiconductor wafer is to be processed. The species is generated by creating free radicals, and combining the free radicals to form the chemical species at the point of use.

Abstract: In order to provide an anticorrosive technique for metal wirings formed by a chemical mechanical polishing (CMP) method, a process for manufacturing a semiconductor integrated circuit device according to the invention comprises the steps of: forming a metal layer of Cu (or a Cu alloy containing Cu as a main component) over the major face of a wafer and then planarizing the metal layer by a chemical mechanical polishing (CMP) method to form metal wirings; anticorroding the planarized major face of the wafer to form a hydrophobic protective film over the surfaces of the metal wirings; immersing the anticorroded major face of the wafer or keeping the same in a wet state so that it may not become dry; and post-cleaning the major face, kept in the wet state, of the wafer.

Abstract: The present invention provides an LSI device polishing composition containing water, abrasive grains, an organic acid, and an oxidizing agent, and having a pH of 5.5-10.0 adjusted by an alkaline substance, the LSI device polishing composition being used for polishing a copper-containing metal wiring layer in which copper is deposited on an insulating film via barrier metal formed of Ta or TaN; and a method for producing LSI devices by use of the polishing composition. During polishing of a barrier metal such as Ta or TaN and a copper wiring layer, the rate of polishing Ta or TaN can be enhanced, to thereby prevent dishing and erosion.

Abstract: Methods and compositions are provided for planarizing substrate surfaces with low dishing. Aspects of the invention provide methods of using compositions comprising an abrasive selected from the group consisting of alumina and ceria and a surfactant for chemical mechanical planarization of substrates to remove polysilicon.

Abstract: A semiconductor processing method includes forming an antireflective coating comprising Ge and Se over a substrate to be patterned. Photoresist is formed over the antireflective coating. The photoresist is exposed to actinic radiation effective to pattern the photoresist. The antireflective coating reduces reflection of actinic radiation during the exposing than would otherwise occur under identical conditions in the absence of the antireflective coating. After the exposing, the substrate is patterned through openings in the photoresist and the antireflective coating using the photoresist and the antireflective coating as a mask. In one implementation, after patterning the substrate, the photoresist and the antireflective coating are chemically etched substantially completely from the substrate using a single etching chemistry.