Abstract: An article for delivery of a chemical reactant includes a liquid or solvated chemical reactant pre-moistened into an applicator. A chemical reactant impervious package has a pouch adapted to enclose the applicator for storage. The chemical reactant delivery article is based on capillary action to wick the continuing supply of chemical reactant to the substrate contacting portion of the applicator and as such is operative independent of chemical reactant gravitational flow.

Abstract: Coded microparticles for use in chemical or biological library synthesis are produced by delineating particles in a plastics sheet supported on a substrate and removing the particles from the substrate.

Abstract: A one-step diagnostic device for simultaneously detecting and distinguishing between a normal pregnancy and an ectopic pregnancy and methods for preparing the device are disclosed. Utilizing the device and principles of the present invention, normal pregnancy and ectopic pregnancy can be rapidly and accurately determined at an early stage by immunologically detecting the morphological differences between human chorionic gonadotropin (hCG) and modified forms thereof, which are secreted into the body fluid of a pregnant female.

Abstract: A multi-array membrane strip biosensor device (10, 20) using a fluid mobile conductive polymer as reporter is described. The biosensor device (20) is designed to detect multiple analytes at low concentrations in near real-time with an electronic data collection system. The biosensor device can be small. The device can be used to detect pathogens, proteins, and other biological materials of interest in food, water, and environmental samples. The device can also be used for on-site diagnosis and against potential bioterrorism. Potential users include food processing plants, meat packaging facilities, fruit and vegetable packers, restaurants, food and water safety inspectors, food wholesalers and retailers, farms, homes, medical profession, import border crossing personnel, and the police force, military, space habitation and national security.

Abstract: An experimental space is determined comprising n factors and a first factor in M number of factor level intervals and in a range of Amin to Amax where A is a proportion of the factor level to total factor levels. An experiment is conducted on the first factor sampled in a range of levels determined according to a relationship (Amin+(Amax−Amin)/(n(M−1))) to (Amax−(Amax−Amin)/(n(M−1))). A system comprises a reactor for effecting a CHTS method on an experimental space to produce results and a programmed controller for the reactor that defines an experimental space comprising a lattice of points representing increments of reaction factor levels from a minimum level value to a maximum level value according to the relationship (Amin+(Amax−Amin)/(n(M−1))) to (Amax−Amin)/(n(M−1))) where M is a number of intervals for the factor levels of the range, n is a number of mixture components and A is a proportion of the factor level to total factor levels.

Abstract: A water-soluble reference standard is useful for immunoassays of a lipophilic drugs.

Abstract: Methods for identifying agents that can increase or decrease the isopeptidase activity of a COP9 signalsome (CSN) are provided, as are agent identified using such screening assays. In addition, methods of ameliorating a pathologic condition such as a cancer or an autoimmune disease in a subject by modulating the CSN isopeptidase activity are provided, as are medicaments useful for treating a subject having such a condition.

Abstract: Internet communication technology is combined with global position systems (GPS) to provide anyone with access to the Internet or web to locate and determine conditions relating to a specific unit or vehicle or fleet of units or vehicles anywhere in the world. The unit or vehicle may communicate directly with the web for location based or location valuable information. Communication between units and/or vehicles is also provided. A transceiver device is located onboard the vehicle/unit and can be accessed by a local Internet interface via common carrier such as cellular telephone or the like. The transceiver includes an integral GPS signal generator and other identifying data. Once the transceiver is accessed by the Internet, the identifying data and the GPS signal are transmitted via the transceiver to the web, where it may be reviewed by any party having authorized access to the web site containing the information.

Abstract: A method of adding a thermally conductive, electrically nonconductive filler to a flexible substrate such as a polyimide core. The substrate may be used, for example, as a part of a polyimide core for a tape or an interposer in a BGA or similar integrated circuit package. The resulting substrate has a higher thermal conductivity as compared to conventional substrates without fillers, thereby increasing the thermal dissipation through the substrate and enabling the device to cool more efficiently. The filler also reduces the coefficient of thermal expansion of the substrate to more closely match the die and reduce stresses. Furthermore, the filler increases the rigidity of the substrate, thereby enabling the device to be handled and carried more easily, for example, without a metal frame carrier.

Abstract: This invention provides a process for producing PZT films by specifying a Ti material having a broad allowable temperature range for giving a predetermined film composition, easily thermally deposited from Ti(OiPr)2(dpm)2 even at a low substrate temperature of 450° C. or less in CVD where starting materials are fed in a solution vaporization system. Ti(OiPr)2(dibm)2 is used as a Ti source, and a solution of a combination of Pb(dpm)2-Zr(OiPr)(dpm)3-Ti(OiPr)2(dibm)2 in n-butyl acetate is vaporized and supplied at 200° C., and subjected to CVD at a substrate temperature of 420° C. at 1 Torr in an oxygen atmosphere, whereby excellent PZT films can be produced.

Abstract: A surface treatment method includes: a plasma conversion step of using plasma to convert a substance into the form of plasma, thereby generating a first plasma substance and a second plasma substance; a step of beginning introduction of the first plasma substance, which is generated by using the plasma, into a substratum; a step of ending introduction of the first plasma substance into the substratum; a step of observing the state of the second plasma substance, which is generated by using the plasma, prior to the ending step; and a step of controlling a plasma process time, which represents a time interval from the beginning step to the ending step, based on the observation result obtained at the observation step, such that a total dosage of the first plasma substance, which represents a total quantity of the first plasma substance introduced into the substratum, becomes equal to a desired total dosage.

Abstract: A method for automated monitoring and controlling of a semiconductor wafer plasma etching process including collecting data versus time during a plasma etching process said data including information representative of a concentration of at least one pair of reactant and product species present during the course of the plasma etching process; calculating a selected ratio of at least one reactant species and one product species at selected time intervals in the plasma etching process to create real-time reactant-product ratio data; retrieving pre-determined reactant-product ratio data for the at least one reactant species and one product species for comparison with the real-time reactant-product ratio data; comparing the pre-determined reactant-product ratio data with the real-time reactant-product ratio data to determine a difference; and, adjusting at least one plasma process operating parameter to minimize the difference.

Abstract: A bond pad structure comprising two bond pads, methods of forming the bond pad structure, an integrated circuit die incorporating the bond pad structure, and methods of using the bond pad structure are provided. Each of the bond pads comprise stacked metal layers, at least one lower metal layer and an upper metal layer. When the two pads are connected by a conductive material, they function as a single pad. The lower metal layer of one of the bond pads forms an extension that extends beneath the upper metal layer of the other of the bond pad. The lower metal extension functions to block the etching of a dielectric layer that is put down over the upper metal layers and the underlying substrate, for example, during a passivation etch to form the bond pad opening, to protect the substrate from damage.

Abstract: A system for regulating spacer deposition is provided. At least one spacer deposition component deposits spacer on a portion of a wafer. A spacer deposition controller regulates the at least one spacer deposition component. A system for directing light directs light to the at least one spacer and collects light reflected from the portion of the wafer. A measuring system measures thickness parameters associated with the deposited spacer. A processor is operatively coupled to the measuring system and the spacer deposition controller, wherein the processor receives the measured data from the measuring system, analyzes the measured data by comparing the measured data to stored acceptable spacer thickness values to determine necessary adjustments to the spacer deposition component via the spacer deposition controller to facilitate regulating spacer thickness on the portion of the wafer and on subsequent portions of wafers.

Abstract: Wafer level testing is accomplished by using a visual indicator (43) in lieu of a probe machine. Before singulation, each die (52) in a wafer (50) is placed into a test mode and BIST circuitry (39) in each die performs predetermined tests of the other circuits on the die. A pass/fail signal is communicated to a visual indicating device, such as an LED, on the wafer. Each die has a corresponding visual indicator. The LED may be contained either on the die or in the scribe area. Multiple LEDs may be used for multiple circuit modules under test. The test permits easy detection of failures without using probing. Testing such as burn-in may be performed to determine whether a part will survive a range of operating conditions. In one form, a CMOS implementation of an LED may be used in conjunction with a CMOS wafer.

Abstract: Method for determining the location of a droplet of liquid placed on a surface of a semiconductor wafer. In one embodiment the method includes establishing first and second reference axes that intersect at a point and superimposing the point over the droplet on the semiconductor wafer surface. A first reference coordinate indicative of the position of the point along the first axis and a second reference coordinate indicative of the position of the point along the second axis are generated.

Abstract: A method for reworking integrated circuit (IC) wafers having copper-metallized bond pads exposed in protective overcoat openings and one or more bondable metal layers deposited onto the bond pads by a technology which may produce some parts with off-spec or missing depositions. After identifying the wafer with off-spec metal layers, a layer of glass buffer is deposited over those wafers, which also fill any missing depositions at least partially. The glass-covered surface is then chemically-mechanically polished until the off-spec metal layers and at least portion of the protective overcoat are removed, without damaging the copper metallization. Finally, a fresh layer of protective overcoat is deposited, selectively opened to expose the bond pads, and provided anew with one or more bondable metal layers.

Abstract: There is provided a flexible circuit module, including at least one rigid carrier, at least one solid state device mounted over a first side of the at least one rigid carrier, a flexible base supporting a second side of the at least one rigid carrier, a conductive interconnect pattern on the flexible base, and a plurality of feed through electrodes extending from the first side to the second side of the at least one rigid carrier and electrically connecting the conductive interconnect pattern with the at least one of a plurality of the solid state devices. The solid state devices may be LED chips to form an LED array module.

Abstract: A method of making an organic layer from an organic material on a substrate which will form part of an organic light-emitting device, including the steps of providing a sublimable organic material in a powder form; providing a thermally conductive and non-sublimable ceramic material in a powder form; forming a mixture of the sublimable organic material powder and thermally conductive and non-sublimable ceramic material powder; placing such mixture into a die and using a punch to apply sufficient pressure to the heated mixture to cause the mixture of powders to consolidate into a solid pellet; and removing the pellet from the die.

Abstract: A thin film transistor substrate including a semiconductor layer having a source region and a drain region, an insulating film and a gate electrode which are formed on the semiconductor layer, an interlayer insulating film which is a film stack with mutually different dielectric constants and which covers the gate electrode, a source region contact hole and a drain region contact hole which are formed on the interlayer insulating film, a pixel electrode connected to the source region through the source region contact hole, a first conductive film connected to the drain region through the drain region contact hole and formed of the same film as that of the pixel electrode, and a second conductive film connected to the drain region through the first conductive film.

Abstract: A data holding control signal for each data line is supplied to a plurality of source followers that are connected together in parallel. The parallel-connected source followers are a combination of at least one first follower that is illuminated with laser light only once and at least one second follower that is illuminated twice. A width of the laser light illumination for crystallization is equal to a pitch of the source followers multiplied by an integer that is not less than 3.

Abstract: A method for manufacturing a light-emitting device which using group III nitride group semiconductors and a quantum well structure, comprising forming a well layer (e.g. an InGaN layer), forming a cap layer on the well layer, the cap layer having almost the same compositions as the well layer at a temperature similar to that at which the well layer was formed. Further, and the cap layer is formed at a crystal growth rate which is faster than the crystal growth rate of the well layer and removing the cap layer using a thermal cracking (or decomposition) process during the temperature ramp up associated with the formation of the next group III nitride compound semiconductor layer. After the cap layer is removed, the group III nitride compound semiconductor layer is formed on the exposed well layer.

Abstract: A method is disclosed for forming an image sensor. In a semiconductor wafer containing a p-type region an n-type connection region is formed within the p-type region. An n-type photodiode region is formed in the p-type region connected to the connection region. A field oxide isolation region is formed, having a part that is over portions of the n-type connection region and the n-type photodiode region. This part of the field oxide region covers the area where these regions are connected and extends into these regions. The edges of this part of the field oxide region fall within these regions, while leaving a distance between these edges and pn junctions formed by the connection region and the p-type region and the n-type photodiode region and p-type region. A gate oxide is formed over regions not covered by field oxide.

Abstract: There is disclosed a manufacturing method for exposure mask, which comprises acquiring a first information showing surface shape of surface of each of a plurality of mask substrates, and a second information showing the flatness of the surface of each of mask substrates before and after chucked on a mask stage of an exposure apparatus, forming a corresponding relation of each mask substrate, the first information and the second information, selecting the second information showing a desired flatness among the second information of the corresponding relation, and preparing another mask substrate having the same surface shape as the surface shape indicated by the first information in the corresponding relation with the selected second information, and forming a desired pattern on the above-mentioned another mask substrate.

Abstract: A micromachined structure having electrically isolated components is formed by thermomigrating a dopant through a substrate to form a doped region within the substrate. The doped region separates two portions of the substrate. The dopant is selected such that the doped region electrically isolates the two portions of the substrate from each other via junction isolation.

Abstract: This invention comprises a process for fabricating a MEMS microstructure in a sealed cavity wherein the etchant entry holes are created as a by-product of the fabrication process without an additional step to etch holes in the cap layer. The process involves extending the layers of sacrificial material past the horizontal boundaries of the cap layer. The cap layer is supported by pillars formed by a deposition in holes etched through the sacrificial layers, and the etchant entry holes are formed when the excess sacrificial material is etched away, leaving voids between the pillars supporting the cap.

Abstract: The present invention relates to an optical integrated circuit device, a fabrication method of the same and a module of an optical communication transmission and receiving apparatus using the same. The optical integrated circuit device comprises a semiconductor substrate, an active layer formed on an upper surface of the semiconductor substrate, a first current disconnection layer formed on an upper surface of the semiconductor substrate at both sides of the active later, a second current disconnection layer formed on an upper surface of the first current disconnection layer, and a convex portion formed on an upper portion of the active layer and an upper surface of the second current disconnection layer.

Abstract: A polysilicon FET is built atop a SiC diode to form a MOSgated device. The polysilicon FET includes an invertible layer of polysilicon atop the surface of a SiC diode which has spaced diode diffusions. A MOSgate is formed on the polysilicon layer and the energization of the gate causes an inversion channel in the invertible layer to form a majority carrier conduction path from a top source electrode to a bottom drain electrode. Forward voltage is blocked in part by the polysilicon FET and in larger part by the depletion of the silicon carbide area between the spaced diode diffusions.

Abstract: An integrated circuit package includes at least one semiconductor die embedded in a substrate made of a heat deformable material such as plastic or a combination of plastics. The at least one die is embedded so that the top surface of the at least one die, which contains a plurality of bonding pads, is exposed, and, in certain embodiments, substantially coplanar with the top surface of the substrate. A layer of conductive material is then formed on the top surface of the substrate and on the top surfaces(s) of at least one semiconductor die. This layer is formed into a plurality of electrically conductive paths each path beginning at a selected bonding pad and terminating in an electrically conductive land on the top surface of the substrate.

Abstract: The invention concerns a manufacturing process for a contactless smart card (or ticket) which includes the following steps:

Abstract: A semiconductor package production method containing a step in which a bond layer made of a single-layer film thermoset bond is provided on the back of a wafer on which many semiconductor devices are formed, a dicing tape is pasted onto its bond layer side, and the bond layer and the wafer are diced simultaneously in order to obtain semiconductor devices with the bond layer, and a step in which the semiconductor devices with the bond layer are detached from the dicing tape and die-attached to interposing substrates serving as bodies to which they are bonded; wherein, the aforementioned film thermoset bond contains an epoxy resin, an epoxy resin hardener, and a phenoxy resin as well as 50-80 wt % of spherical silica, and the bond layer is 100 &mgr;m or thicker. A semiconductor device made by this method and a wafer for use with this method.

Abstract: An improved stacked-die package includes an interposer which improves the manufacturability of the package. A semiconductor package includes a package substrate having a plurality of bond pads; a first semiconductor device mounted on the package substrate, the first semiconductor device having a plurality of bond pads provided thereon; an interposer mounted on the first semiconductor device, the interposer having a first interposer bond pad and a second interposer bond pad, wherein the first and second interposer bond pads are electrically coupled; a second semiconductor device mounted on the interposer, the second semiconductor device having a plurality of bond pads provided thereon; a first bond wire connected to one of the plurality of bond pads on said first semiconductor and to the first interposer bond pad; and a second bond wire connected to the second interposer bond pad and to one of the plurality of bond pads on the semiconductor device.

Abstract: A semiconductor package and a fabrication method thereof are provided. A plurality of first chips are mounted on and electrically connected to a substrate plate. A shielding structure including a shielding portion and a supporting portion is mounted on the substrate plate, wherein the supporting portion abuts against the substrate plate, and the shielding portion is formed with a plurality of openings corresponding in position to the first chips. An adhesive is applied through the openings to form adhesive layers respectively on the first chips. After removing the shielding structure from the substrate plate, a plurality of second chips are respectively stacked on the adhesive layers and electrically connected to the substrate plate. By performing molding and singulating processes, the packaged structure is singulated to form individual semiconductor packages. It is a characteristic advantage of forming the adhesive layers in a batch manner, making fabrication costs and time significantly reduced.

Abstract: The invention enhances reliability and achieves higher speeds for semiconductor devices with a stacked structure. A semiconductor device includes a die pad, a plurality of semiconductor chips stacked on one surface of the die pad, leads extending toward the die pad, first wires that are bonded to first pads of a first semiconductor chip among the plurality of semiconductor chips and to second pads of a second semiconductor chip among the plurality of semiconductor chips, second wires that are bonded to the leads and to the first pads or the second pads, and a sealing material that seals the plurality of semiconductor chips and exposes another surface of the die pad.

Abstract: When a semiconductor device having an element isolation structure is formed, first, a trench is formed in a wafer from a principal surface of the wafer, and the trench is filled with an insulating film. Then, the back surface of the wafer is polished so that the insulating film is exposed on the back surface. Accordingly, the insulating. film penetrates the wafer from the principal surface to the back surface, thereby performing element isolation of the wafer. It is not necessary to use a bonding wafer. Thus, the method for manufacturing the semiconductor device is simplified.

Abstract: A mask (118) and method for patterning a semiconductor wafer. The mask (118) includes apertures (122) and assist lines (124) disposed between apertures (122). The assist lines (124) reduce the diffraction effects of the lithographic process, resulting in improved depth of focus and resolution of patterns on a semiconductor wafer.

Abstract: Techniques are provided for preventing occurrence of damage to the top surface of a semiconductor chip at the time of die bonding the semiconductor chip by use of a contact collet. A protection tape is pasted to the top surface of the semiconductor chip before die bonding of the semiconductor chip is executed by pressing the back surface (underside) of the semiconductor chip sucked and securely held by the contact collect against respective chip-mounting regions of a multi-wiring board. The contact collect is, for example, substantially cylindrical in outside shape, and a bottom part (suction head) thereof is made of a soft synthetic rubber, and so forth. The protection tape pasted to pasted to the top surface of the semiconductor chip can prevent the top surface of the semiconductor chip from coming in direct contact with the contact collet even at the time of vacuum suction by pressing the suction head of the contact collect against the top surface of the semiconductor chip.

Abstract: A semiconductor device is disclosed in which a heat sink is difficult to warp and which is inexpensive.

Abstract: A method for fabricating a leadframe structure comprising a chip mount pad and a plurality of lead segments, each having a first end near the mount pad and a second end remote from said mount pad. The structure is formed from a sheet-like starting material. In a first plating system, the leadframe is plated with a layer of nickel. Next, the second segment ends are selectively masked and a layer of palladium is selectively plated on the nickel layer on the exposed chip pad and first segments ends in a thickness suitable for wire bonding attachment. In a second plating system, the chip pad and first segment ends are selectively masked and a pure tin layer is selectively plated on the nickel layer on the exposed second segment ends in a thickness suitable for parts attachment.

Abstract: At the time of performing a resin molding for a matrix frame in the fabrication of a semiconductor integrated circuit device, a predetermined amount of air is fed into each of first cavities in a first row and second cavities in a second row, the first and second cavities being formed in a matrix arrangement in a lower mold of a molding die, to pressurize the interiors of the cavities, and a sealing resin is charged into the cavities in such a manner that the charging speeds of the sealing resin become equal in all of the cavities, whereby it is possible to stabilize the quality of product obtained.

Abstract: A conductive plastic lead frame and method of manufacturing the same suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: A conductive plastic lead frame and method of manufacturing the same suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: A conductive plastic lead frame and method of manufacturing the same suitable for use in IC packaging. In a preferred embodiment, the lead frame is constructed of a plastic or polymer based lead frame structure with an intrinsic conductive polymer coating. In a second embodiment the lead frame is a composite plastic or polymeric material intermixed with an intrinsic conductive polymer coating.

Abstract: A method for manufacturing a semiconductor device including providing first and second semiconductor chips each having a main surface having a semiconductor element and a plurality of external terminals, and a lower surface respectively opposing the main surface. A first lead frame is provided which has a frame body which supports outer portions and inner portions extending from the outer portions, and a second lead frame is provided which has a frame body which supports outer portions and inner portions extending from the outer portions. After electrically connecting the external terminals to the inner portions of the lead frames and resin-sealing the first and second semiconductor chips so that the first and second lead frames are superimposed, the frame body of the second lead frame is removed and a first processing fluid is applied to the outer portions of the first lead frame and the second lead frame.

Abstract: A fabrication method for forming a semiconductor device having a fuse is provided. A substrate includes a cell array area, a peripheral circuit area and a global step difference between the cell array area and the peripheral circuit area. The substrate comprises a fuse formed in the peripheral circuit of the substrate. An interlayer insulating layer is formed on the global step difference. The global step difference is reduced by a cell open process. A multilevel metal interconnection including an intermetal insulating layer is formed on the resultant structure. During the cell open process and/or the process for forming the multilevel metal interconnection, the interlayer insulating layer and/or the intermetal insulating layer is partially removed to form a recess. A passivation layer is formed on the multilevel metal interconnection. A fuse opening is formed through the recess to expose the fuse.

Abstract: The invention relates to improvements in a method of manufacturing a semiconductor device in which deterioration in a transistor characteristic is avoided by preventing a channel stop implantation layer from being formed in an active region. After patterning a nitride film (22), the thickness of an SOI layer 3 is measured (S2) and, by using the result of measurement, etching conditions (etching time and the like) for SOI layer 3 are determined (S3). To measure the thickness of SOI layer 3, it is sufficient to use spectroscopic ellipsometry which irradiates the surface of a substance with linearly polarized light and observes elliptically polarized light reflected by the surface of a substance. The etching condition determined is used and a trench TR2 is formed by using patterned nitride film 22 as an etching mask (S4).

Abstract: This invention concerns a process of forming a polarizable layer in a buried oxide layer of a silicon-on-insulator substrate for the fabrication of non-volatile memory. This process comprises implanting, through the active silicon layer, Si ions into the buried oxide layer at an ion implantation energy selected so that the implanted ion has its peak concentration between 5-50 nm from the silicon/buried oxide interface. The implantation step can occur while externally heating the silicon-on-insulator substrate at a temperature between 25-300 degrees Celsius. After implantation, an annealing step may be completed to repair any damage the implantation may have created in the silicon-on-insulator substrate.

Abstract: Semiconductor processing methods of forming integrated circuitry are described. In one embodiment, memory circuitry and peripheral circuitry are formed over a substrate. The peripheral circuitry comprises first and second type MOS transistors. Second type halo implants are conducted into the first type MOS transistors in less than all of the peripheral MOS transistors of the first type. In another embodiment, a plurality of n-type transistor devices are formed over a substrate and comprise memory array circuitry and peripheral circuitry. At least some of the individual peripheral circuitry n-type transistor devices are partially masked, and a halo implant is conducted for unmasked portions of the partially masked peripheral circuitry n-type transistor devices. In yet another embodiment, at least a portion of only one of the source and drain regions is masked, and at least a portion of the other of the source and drains regions is exposed for at least some of the peripheral circuitry n-type transistor devices.

Abstract: A method for forming a single gate having a dual work-function is described. A gate electrode is formed overlying a gate dielectric layer on a substrate. Sidewalls of the gate electrode are selectively doped whereby the doped sidewalls have a first work-function and whereby a central portion of the gate electrode not doped has a second work-function to complete formation of a single gate having multiple work-functions in the fabrication of integrated circuits.

Abstract: Offsets and timing skews in data signals captured in a data receiver are reduced by adaptively adjusting a transition threshold of the data receiver. A data corrector provides a set of adjustment vectors for adjusting the transition threshold of the data receiver. The data corrector uses differential clock signals and a reference voltage to generate the set of adjustment vectors to be provided to the data receivers. The data receiver is an improved receiver incorporating a trip point adjustor that receives the set of adjustment vectors from the data corrector to adjust its trip point relative to the reference voltage.